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1/*
2 * arch/arm/mach-at91/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h>
21#include <mach/cpu.h>
22#include <mach/at91_dbgu.h>
23#include <mach/at91sam9260.h>
24#include <mach/hardware.h>
25
26#include "at91_aic.h"
27#include "at91_rstc.h"
28#include "soc.h"
29#include "generic.h"
30#include "clock.h"
31#include "sam9_smc.h"
32#include "pm.h"
33
34/* --------------------------------------------------------------------
35 * Clocks
36 * -------------------------------------------------------------------- */
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk adc_clk = {
57 .name = "adc_clk",
58 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61
62static struct clk adc_op_clk = {
63 .name = "adc_op_clk",
64 .type = CLK_TYPE_PERIPHERAL,
65 .rate_hz = 5000000,
66};
67
68static struct clk usart0_clk = {
69 .name = "usart0_clk",
70 .pmc_mask = 1 << AT91SAM9260_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk usart1_clk = {
74 .name = "usart1_clk",
75 .pmc_mask = 1 << AT91SAM9260_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart2_clk = {
79 .name = "usart2_clk",
80 .pmc_mask = 1 << AT91SAM9260_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk mmc_clk = {
84 .name = "mci_clk",
85 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk udc_clk = {
89 .name = "udc_clk",
90 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk twi_clk = {
94 .name = "twi_clk",
95 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk spi0_clk = {
99 .name = "spi0_clk",
100 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk spi1_clk = {
104 .name = "spi1_clk",
105 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk ssc_clk = {
109 .name = "ssc_clk",
110 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk tc0_clk = {
114 .name = "tc0_clk",
115 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk tc1_clk = {
119 .name = "tc1_clk",
120 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk tc2_clk = {
124 .name = "tc2_clk",
125 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk ohci_clk = {
129 .name = "ohci_clk",
130 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk macb_clk = {
134 .name = "pclk",
135 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk isi_clk = {
139 .name = "isi_clk",
140 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk usart3_clk = {
144 .name = "usart3_clk",
145 .pmc_mask = 1 << AT91SAM9260_ID_US3,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk usart4_clk = {
149 .name = "usart4_clk",
150 .pmc_mask = 1 << AT91SAM9260_ID_US4,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk usart5_clk = {
154 .name = "usart5_clk",
155 .pmc_mask = 1 << AT91SAM9260_ID_US5,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk tc3_clk = {
159 .name = "tc3_clk",
160 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk tc4_clk = {
164 .name = "tc4_clk",
165 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk tc5_clk = {
169 .name = "tc5_clk",
170 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173
174static struct clk *periph_clocks[] __initdata = {
175 &pioA_clk,
176 &pioB_clk,
177 &pioC_clk,
178 &adc_clk,
179 &adc_op_clk,
180 &usart0_clk,
181 &usart1_clk,
182 &usart2_clk,
183 &mmc_clk,
184 &udc_clk,
185 &twi_clk,
186 &spi0_clk,
187 &spi1_clk,
188 &ssc_clk,
189 &tc0_clk,
190 &tc1_clk,
191 &tc2_clk,
192 &ohci_clk,
193 &macb_clk,
194 &isi_clk,
195 &usart3_clk,
196 &usart4_clk,
197 &usart5_clk,
198 &tc3_clk,
199 &tc4_clk,
200 &tc5_clk,
201 // irq0 .. irq2
202};
203
204static struct clk_lookup periph_clocks_lookups[] = {
205 /* One additional fake clock for macb_hclk */
206 CLKDEV_CON_ID("hclk", &macb_clk),
207 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
208 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
209 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
210 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
211 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
212 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
213 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
214 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
215 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
216 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
217 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
218 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
219 /* more usart lookup table for DT entries */
220 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
221 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
222 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
223 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
224 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
225 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
226 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
228 /* more tc lookup table for DT entries */
229 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
230 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
231 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
232 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
233 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
234 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
235 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
236 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
237 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
238 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
239 /* fake hclk clock */
240 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
241 CLKDEV_CON_ID("pioA", &pioA_clk),
242 CLKDEV_CON_ID("pioB", &pioB_clk),
243 CLKDEV_CON_ID("pioC", &pioC_clk),
244 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
247};
248
249static struct clk_lookup usart_clocks_lookups[] = {
250 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
251 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
252 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
253 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
254 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
255 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
256 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
257};
258
259/*
260 * The two programmable clocks.
261 * You must configure pin multiplexing to bring these signals out.
262 */
263static struct clk pck0 = {
264 .name = "pck0",
265 .pmc_mask = AT91_PMC_PCK0,
266 .type = CLK_TYPE_PROGRAMMABLE,
267 .id = 0,
268};
269static struct clk pck1 = {
270 .name = "pck1",
271 .pmc_mask = AT91_PMC_PCK1,
272 .type = CLK_TYPE_PROGRAMMABLE,
273 .id = 1,
274};
275
276static void __init at91sam9260_register_clocks(void)
277{
278 int i;
279
280 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
281 clk_register(periph_clocks[i]);
282
283 clkdev_add_table(periph_clocks_lookups,
284 ARRAY_SIZE(periph_clocks_lookups));
285 clkdev_add_table(usart_clocks_lookups,
286 ARRAY_SIZE(usart_clocks_lookups));
287
288 clk_register(&pck0);
289 clk_register(&pck1);
290}
291
292/* --------------------------------------------------------------------
293 * GPIO
294 * -------------------------------------------------------------------- */
295
296static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
297 {
298 .id = AT91SAM9260_ID_PIOA,
299 .regbase = AT91SAM9260_BASE_PIOA,
300 }, {
301 .id = AT91SAM9260_ID_PIOB,
302 .regbase = AT91SAM9260_BASE_PIOB,
303 }, {
304 .id = AT91SAM9260_ID_PIOC,
305 .regbase = AT91SAM9260_BASE_PIOC,
306 }
307};
308
309/* --------------------------------------------------------------------
310 * AT91SAM9260 processor initialization
311 * -------------------------------------------------------------------- */
312
313static void __init at91sam9xe_map_io(void)
314{
315 unsigned long sram_size;
316
317 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
318 case AT91_CIDR_SRAMSIZ_32K:
319 sram_size = 2 * SZ_16K;
320 break;
321 case AT91_CIDR_SRAMSIZ_16K:
322 default:
323 sram_size = SZ_16K;
324 }
325
326 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
327}
328
329static void __init at91sam9260_map_io(void)
330{
331 if (cpu_is_at91sam9xe())
332 at91sam9xe_map_io();
333 else if (cpu_is_at91sam9g20())
334 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
335 else
336 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
337}
338
339static void __init at91sam9260_ioremap_registers(void)
340{
341 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
342 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
343 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
344 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
345 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
346 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
347 at91_pm_set_standby(at91sam9_sdram_standby);
348}
349
350static void __init at91sam9260_initialize(void)
351{
352 arm_pm_idle = at91sam9_idle;
353 arm_pm_restart = at91sam9_alt_restart;
354
355 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
356
357 /* Register GPIO subsystem */
358 at91_gpio_init(at91sam9260_gpio, 3);
359}
360
361/* --------------------------------------------------------------------
362 * Interrupt initialization
363 * -------------------------------------------------------------------- */
364
365/*
366 * The default interrupt priority levels (0 = lowest, 7 = highest).
367 */
368static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
369 7, /* Advanced Interrupt Controller */
370 7, /* System Peripherals */
371 1, /* Parallel IO Controller A */
372 1, /* Parallel IO Controller B */
373 1, /* Parallel IO Controller C */
374 0, /* Analog-to-Digital Converter */
375 5, /* USART 0 */
376 5, /* USART 1 */
377 5, /* USART 2 */
378 0, /* Multimedia Card Interface */
379 2, /* USB Device Port */
380 6, /* Two-Wire Interface */
381 5, /* Serial Peripheral Interface 0 */
382 5, /* Serial Peripheral Interface 1 */
383 5, /* Serial Synchronous Controller */
384 0,
385 0,
386 0, /* Timer Counter 0 */
387 0, /* Timer Counter 1 */
388 0, /* Timer Counter 2 */
389 2, /* USB Host port */
390 3, /* Ethernet */
391 0, /* Image Sensor Interface */
392 5, /* USART 3 */
393 5, /* USART 4 */
394 5, /* USART 5 */
395 0, /* Timer Counter 3 */
396 0, /* Timer Counter 4 */
397 0, /* Timer Counter 5 */
398 0, /* Advanced Interrupt Controller */
399 0, /* Advanced Interrupt Controller */
400 0, /* Advanced Interrupt Controller */
401};
402
403AT91_SOC_START(at91sam9260)
404 .map_io = at91sam9260_map_io,
405 .default_irq_priority = at91sam9260_default_irq_priority,
406 .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
407 | (1 << AT91SAM9260_ID_IRQ2),
408 .ioremap_registers = at91sam9260_ioremap_registers,
409 .register_clocks = at91sam9260_register_clocks,
410 .init = at91sam9260_initialize,
411AT91_SOC_END