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1/*
2 * Setup code for AT91RM9200
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 * 2012 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include <linux/of.h>
12#include <linux/of_platform.h>
13
14#include <asm/mach/arch.h>
15
16#include "generic.h"
17#include "soc.h"
18
19static const struct at91_soc rm9200_socs[] = {
20 AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
21 { /* sentinel */ },
22};
23
24static void __init at91rm9200_dt_device_init(void)
25{
26 struct soc_device *soc;
27 struct device *soc_dev = NULL;
28
29 soc = at91_soc_init(rm9200_socs);
30 if (soc != NULL)
31 soc_dev = soc_device_to_device(soc);
32
33 of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
34
35 at91rm9200_pm_init();
36}
37
38static const char *const at91rm9200_dt_board_compat[] __initconst = {
39 "atmel,at91rm9200",
40 NULL
41};
42
43DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
44 .init_machine = at91rm9200_dt_device_init,
45 .dt_compat = at91rm9200_dt_board_compat,
46MACHINE_END
1/*
2 * arch/arm/mach-at91/at91rm9200.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/reboot.h>
15#include <linux/clk/at91_pmc.h>
16
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h>
21#include <mach/at91rm9200.h>
22#include <mach/at91_st.h>
23#include <mach/cpu.h>
24#include <mach/hardware.h>
25
26#include "at91_aic.h"
27#include "soc.h"
28#include "generic.h"
29#include "clock.h"
30#include "sam9_smc.h"
31#include "pm.h"
32
33/* --------------------------------------------------------------------
34 * Clocks
35 * -------------------------------------------------------------------- */
36
37/*
38 * The peripheral clocks.
39 */
40static struct clk udc_clk = {
41 .name = "udc_clk",
42 .pmc_mask = 1 << AT91RM9200_ID_UDP,
43 .type = CLK_TYPE_PERIPHERAL,
44};
45static struct clk ohci_clk = {
46 .name = "ohci_clk",
47 .pmc_mask = 1 << AT91RM9200_ID_UHP,
48 .type = CLK_TYPE_PERIPHERAL,
49};
50static struct clk ether_clk = {
51 .name = "ether_clk",
52 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk mmc_clk = {
56 .name = "mci_clk",
57 .pmc_mask = 1 << AT91RM9200_ID_MCI,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk twi_clk = {
61 .name = "twi_clk",
62 .pmc_mask = 1 << AT91RM9200_ID_TWI,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk usart0_clk = {
66 .name = "usart0_clk",
67 .pmc_mask = 1 << AT91RM9200_ID_US0,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk usart1_clk = {
71 .name = "usart1_clk",
72 .pmc_mask = 1 << AT91RM9200_ID_US1,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk usart2_clk = {
76 .name = "usart2_clk",
77 .pmc_mask = 1 << AT91RM9200_ID_US2,
78 .type = CLK_TYPE_PERIPHERAL,
79};
80static struct clk usart3_clk = {
81 .name = "usart3_clk",
82 .pmc_mask = 1 << AT91RM9200_ID_US3,
83 .type = CLK_TYPE_PERIPHERAL,
84};
85static struct clk spi_clk = {
86 .name = "spi_clk",
87 .pmc_mask = 1 << AT91RM9200_ID_SPI,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk pioA_clk = {
91 .name = "pioA_clk",
92 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk pioB_clk = {
96 .name = "pioB_clk",
97 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
98 .type = CLK_TYPE_PERIPHERAL,
99};
100static struct clk pioC_clk = {
101 .name = "pioC_clk",
102 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk pioD_clk = {
106 .name = "pioD_clk",
107 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk ssc0_clk = {
111 .name = "ssc0_clk",
112 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk ssc1_clk = {
116 .name = "ssc1_clk",
117 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk ssc2_clk = {
121 .name = "ssc2_clk",
122 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
123 .type = CLK_TYPE_PERIPHERAL,
124};
125static struct clk tc0_clk = {
126 .name = "tc0_clk",
127 .pmc_mask = 1 << AT91RM9200_ID_TC0,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk tc1_clk = {
131 .name = "tc1_clk",
132 .pmc_mask = 1 << AT91RM9200_ID_TC1,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk tc2_clk = {
136 .name = "tc2_clk",
137 .pmc_mask = 1 << AT91RM9200_ID_TC2,
138 .type = CLK_TYPE_PERIPHERAL,
139};
140static struct clk tc3_clk = {
141 .name = "tc3_clk",
142 .pmc_mask = 1 << AT91RM9200_ID_TC3,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk tc4_clk = {
146 .name = "tc4_clk",
147 .pmc_mask = 1 << AT91RM9200_ID_TC4,
148 .type = CLK_TYPE_PERIPHERAL,
149};
150static struct clk tc5_clk = {
151 .name = "tc5_clk",
152 .pmc_mask = 1 << AT91RM9200_ID_TC5,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155
156static struct clk *periph_clocks[] __initdata = {
157 &pioA_clk,
158 &pioB_clk,
159 &pioC_clk,
160 &pioD_clk,
161 &usart0_clk,
162 &usart1_clk,
163 &usart2_clk,
164 &usart3_clk,
165 &mmc_clk,
166 &udc_clk,
167 &twi_clk,
168 &spi_clk,
169 &ssc0_clk,
170 &ssc1_clk,
171 &ssc2_clk,
172 &tc0_clk,
173 &tc1_clk,
174 &tc2_clk,
175 &tc3_clk,
176 &tc4_clk,
177 &tc5_clk,
178 &ohci_clk,
179 ðer_clk,
180 // irq0 .. irq6
181};
182
183static struct clk_lookup periph_clocks_lookups[] = {
184 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
185 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
187 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
188 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
189 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
196 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
197 /* fake hclk clock */
198 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
199 CLKDEV_CON_ID("pioA", &pioA_clk),
200 CLKDEV_CON_ID("pioB", &pioB_clk),
201 CLKDEV_CON_ID("pioC", &pioC_clk),
202 CLKDEV_CON_ID("pioD", &pioD_clk),
203 /* usart lookup table for DT entries */
204 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
205 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
209 /* tc lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
211 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
212 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
213 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
217 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
219 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
224};
225
226static struct clk_lookup usart_clocks_lookups[] = {
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
232};
233
234/*
235 * The four programmable clocks.
236 * You must configure pin multiplexing to bring these signals out.
237 */
238static struct clk pck0 = {
239 .name = "pck0",
240 .pmc_mask = AT91_PMC_PCK0,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 0,
243};
244static struct clk pck1 = {
245 .name = "pck1",
246 .pmc_mask = AT91_PMC_PCK1,
247 .type = CLK_TYPE_PROGRAMMABLE,
248 .id = 1,
249};
250static struct clk pck2 = {
251 .name = "pck2",
252 .pmc_mask = AT91_PMC_PCK2,
253 .type = CLK_TYPE_PROGRAMMABLE,
254 .id = 2,
255};
256static struct clk pck3 = {
257 .name = "pck3",
258 .pmc_mask = AT91_PMC_PCK3,
259 .type = CLK_TYPE_PROGRAMMABLE,
260 .id = 3,
261};
262
263static void __init at91rm9200_register_clocks(void)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
268 clk_register(periph_clocks[i]);
269
270 clkdev_add_table(periph_clocks_lookups,
271 ARRAY_SIZE(periph_clocks_lookups));
272 clkdev_add_table(usart_clocks_lookups,
273 ARRAY_SIZE(usart_clocks_lookups));
274
275 clk_register(&pck0);
276 clk_register(&pck1);
277 clk_register(&pck2);
278 clk_register(&pck3);
279}
280
281/* --------------------------------------------------------------------
282 * GPIO
283 * -------------------------------------------------------------------- */
284
285static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
286 {
287 .id = AT91RM9200_ID_PIOA,
288 .regbase = AT91RM9200_BASE_PIOA,
289 }, {
290 .id = AT91RM9200_ID_PIOB,
291 .regbase = AT91RM9200_BASE_PIOB,
292 }, {
293 .id = AT91RM9200_ID_PIOC,
294 .regbase = AT91RM9200_BASE_PIOC,
295 }, {
296 .id = AT91RM9200_ID_PIOD,
297 .regbase = AT91RM9200_BASE_PIOD,
298 }
299};
300
301static void at91rm9200_idle(void)
302{
303 /*
304 * Disable the processor clock. The processor will be automatically
305 * re-enabled by an interrupt or by a reset.
306 */
307 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
308}
309
310static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
311{
312 /*
313 * Perform a hardware reset with the use of the Watchdog timer.
314 */
315 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
316 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
317}
318
319/* --------------------------------------------------------------------
320 * AT91RM9200 processor initialization
321 * -------------------------------------------------------------------- */
322static void __init at91rm9200_map_io(void)
323{
324 /* Map peripherals */
325 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
326}
327
328static void __init at91rm9200_ioremap_registers(void)
329{
330 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
331 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
332 at91_pm_set_standby(at91rm9200_standby);
333}
334
335static void __init at91rm9200_initialize(void)
336{
337 arm_pm_idle = at91rm9200_idle;
338 arm_pm_restart = at91rm9200_restart;
339
340 /* Initialize GPIO subsystem */
341 at91_gpio_init(at91rm9200_gpio,
342 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
343}
344
345
346/* --------------------------------------------------------------------
347 * Interrupt initialization
348 * -------------------------------------------------------------------- */
349
350/*
351 * The default interrupt priority levels (0 = lowest, 7 = highest).
352 */
353static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
354 7, /* Advanced Interrupt Controller (FIQ) */
355 7, /* System Peripherals */
356 1, /* Parallel IO Controller A */
357 1, /* Parallel IO Controller B */
358 1, /* Parallel IO Controller C */
359 1, /* Parallel IO Controller D */
360 5, /* USART 0 */
361 5, /* USART 1 */
362 5, /* USART 2 */
363 5, /* USART 3 */
364 0, /* Multimedia Card Interface */
365 2, /* USB Device Port */
366 6, /* Two-Wire Interface */
367 5, /* Serial Peripheral Interface */
368 4, /* Serial Synchronous Controller 0 */
369 4, /* Serial Synchronous Controller 1 */
370 4, /* Serial Synchronous Controller 2 */
371 0, /* Timer Counter 0 */
372 0, /* Timer Counter 1 */
373 0, /* Timer Counter 2 */
374 0, /* Timer Counter 3 */
375 0, /* Timer Counter 4 */
376 0, /* Timer Counter 5 */
377 2, /* USB Host port */
378 3, /* Ethernet MAC */
379 0, /* Advanced Interrupt Controller (IRQ0) */
380 0, /* Advanced Interrupt Controller (IRQ1) */
381 0, /* Advanced Interrupt Controller (IRQ2) */
382 0, /* Advanced Interrupt Controller (IRQ3) */
383 0, /* Advanced Interrupt Controller (IRQ4) */
384 0, /* Advanced Interrupt Controller (IRQ5) */
385 0 /* Advanced Interrupt Controller (IRQ6) */
386};
387
388AT91_SOC_START(at91rm9200)
389 .map_io = at91rm9200_map_io,
390 .default_irq_priority = at91rm9200_default_irq_priority,
391 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
392 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
393 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
394 | (1 << AT91RM9200_ID_IRQ6),
395 .ioremap_registers = at91rm9200_ioremap_registers,
396 .register_clocks = at91rm9200_register_clocks,
397 .init = at91rm9200_initialize,
398AT91_SOC_END