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1/*
2 * Broadcom BCM63xx SPI controller support
3 *
4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/spi/spi.h>
26#include <linux/completion.h>
27#include <linux/err.h>
28#include <linux/pm_runtime.h>
29
30/* BCM 6338/6348 SPI core */
31#define SPI_6348_RSET_SIZE 64
32#define SPI_6348_CMD 0x00 /* 16-bits register */
33#define SPI_6348_INT_STATUS 0x02
34#define SPI_6348_INT_MASK_ST 0x03
35#define SPI_6348_INT_MASK 0x04
36#define SPI_6348_ST 0x05
37#define SPI_6348_CLK_CFG 0x06
38#define SPI_6348_FILL_BYTE 0x07
39#define SPI_6348_MSG_TAIL 0x09
40#define SPI_6348_RX_TAIL 0x0b
41#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
42#define SPI_6348_MSG_CTL_WIDTH 8
43#define SPI_6348_MSG_DATA 0x41
44#define SPI_6348_MSG_DATA_SIZE 0x3f
45#define SPI_6348_RX_DATA 0x80
46#define SPI_6348_RX_DATA_SIZE 0x3f
47
48/* BCM 3368/6358/6262/6368 SPI core */
49#define SPI_6358_RSET_SIZE 1804
50#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
51#define SPI_6358_MSG_CTL_WIDTH 16
52#define SPI_6358_MSG_DATA 0x02
53#define SPI_6358_MSG_DATA_SIZE 0x21e
54#define SPI_6358_RX_DATA 0x400
55#define SPI_6358_RX_DATA_SIZE 0x220
56#define SPI_6358_CMD 0x700 /* 16-bits register */
57#define SPI_6358_INT_STATUS 0x702
58#define SPI_6358_INT_MASK_ST 0x703
59#define SPI_6358_INT_MASK 0x704
60#define SPI_6358_ST 0x705
61#define SPI_6358_CLK_CFG 0x706
62#define SPI_6358_FILL_BYTE 0x707
63#define SPI_6358_MSG_TAIL 0x709
64#define SPI_6358_RX_TAIL 0x70B
65
66/* Shared SPI definitions */
67
68/* Message configuration */
69#define SPI_FD_RW 0x00
70#define SPI_HD_W 0x01
71#define SPI_HD_R 0x02
72#define SPI_BYTE_CNT_SHIFT 0
73#define SPI_6348_MSG_TYPE_SHIFT 6
74#define SPI_6358_MSG_TYPE_SHIFT 14
75
76/* Command */
77#define SPI_CMD_NOOP 0x00
78#define SPI_CMD_SOFT_RESET 0x01
79#define SPI_CMD_HARD_RESET 0x02
80#define SPI_CMD_START_IMMEDIATE 0x03
81#define SPI_CMD_COMMAND_SHIFT 0
82#define SPI_CMD_COMMAND_MASK 0x000f
83#define SPI_CMD_DEVICE_ID_SHIFT 4
84#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
85#define SPI_CMD_ONE_BYTE_SHIFT 11
86#define SPI_CMD_ONE_WIRE_SHIFT 12
87#define SPI_DEV_ID_0 0
88#define SPI_DEV_ID_1 1
89#define SPI_DEV_ID_2 2
90#define SPI_DEV_ID_3 3
91
92/* Interrupt mask */
93#define SPI_INTR_CMD_DONE 0x01
94#define SPI_INTR_RX_OVERFLOW 0x02
95#define SPI_INTR_TX_UNDERFLOW 0x04
96#define SPI_INTR_TX_OVERFLOW 0x08
97#define SPI_INTR_RX_UNDERFLOW 0x10
98#define SPI_INTR_CLEAR_ALL 0x1f
99
100/* Status */
101#define SPI_RX_EMPTY 0x02
102#define SPI_CMD_BUSY 0x04
103#define SPI_SERIAL_BUSY 0x08
104
105/* Clock configuration */
106#define SPI_CLK_20MHZ 0x00
107#define SPI_CLK_0_391MHZ 0x01
108#define SPI_CLK_0_781MHZ 0x02 /* default */
109#define SPI_CLK_1_563MHZ 0x03
110#define SPI_CLK_3_125MHZ 0x04
111#define SPI_CLK_6_250MHZ 0x05
112#define SPI_CLK_12_50MHZ 0x06
113#define SPI_CLK_MASK 0x07
114#define SPI_SSOFFTIME_MASK 0x38
115#define SPI_SSOFFTIME_SHIFT 3
116#define SPI_BYTE_SWAP 0x80
117
118enum bcm63xx_regs_spi {
119 SPI_CMD,
120 SPI_INT_STATUS,
121 SPI_INT_MASK_ST,
122 SPI_INT_MASK,
123 SPI_ST,
124 SPI_CLK_CFG,
125 SPI_FILL_BYTE,
126 SPI_MSG_TAIL,
127 SPI_RX_TAIL,
128 SPI_MSG_CTL,
129 SPI_MSG_DATA,
130 SPI_RX_DATA,
131 SPI_MSG_TYPE_SHIFT,
132 SPI_MSG_CTL_WIDTH,
133 SPI_MSG_DATA_SIZE,
134};
135
136#define BCM63XX_SPI_MAX_PREPEND 15
137
138#define BCM63XX_SPI_MAX_CS 8
139#define BCM63XX_SPI_BUS_NUM 0
140
141struct bcm63xx_spi {
142 struct completion done;
143
144 void __iomem *regs;
145 int irq;
146
147 /* Platform data */
148 const unsigned long *reg_offsets;
149 unsigned fifo_size;
150 unsigned int msg_type_shift;
151 unsigned int msg_ctl_width;
152
153 /* data iomem */
154 u8 __iomem *tx_io;
155 const u8 __iomem *rx_io;
156
157 struct clk *clk;
158 struct platform_device *pdev;
159};
160
161static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
162 unsigned int offset)
163{
164 return readb(bs->regs + bs->reg_offsets[offset]);
165}
166
167static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
168 unsigned int offset)
169{
170#ifdef CONFIG_CPU_BIG_ENDIAN
171 return ioread16be(bs->regs + bs->reg_offsets[offset]);
172#else
173 return readw(bs->regs + bs->reg_offsets[offset]);
174#endif
175}
176
177static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
178 u8 value, unsigned int offset)
179{
180 writeb(value, bs->regs + bs->reg_offsets[offset]);
181}
182
183static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
184 u16 value, unsigned int offset)
185{
186#ifdef CONFIG_CPU_BIG_ENDIAN
187 iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
188#else
189 writew(value, bs->regs + bs->reg_offsets[offset]);
190#endif
191}
192
193static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
194 { 20000000, SPI_CLK_20MHZ },
195 { 12500000, SPI_CLK_12_50MHZ },
196 { 6250000, SPI_CLK_6_250MHZ },
197 { 3125000, SPI_CLK_3_125MHZ },
198 { 1563000, SPI_CLK_1_563MHZ },
199 { 781000, SPI_CLK_0_781MHZ },
200 { 391000, SPI_CLK_0_391MHZ }
201};
202
203static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
204 struct spi_transfer *t)
205{
206 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
207 u8 clk_cfg, reg;
208 int i;
209
210 /* Default to lowest clock configuration */
211 clk_cfg = SPI_CLK_0_391MHZ;
212
213 /* Find the closest clock configuration */
214 for (i = 0; i < SPI_CLK_MASK; i++) {
215 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
216 clk_cfg = bcm63xx_spi_freq_table[i][1];
217 break;
218 }
219 }
220
221 /* clear existing clock configuration bits of the register */
222 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
223 reg &= ~SPI_CLK_MASK;
224 reg |= clk_cfg;
225
226 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
227 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
228 clk_cfg, t->speed_hz);
229}
230
231/* the spi->mode bits understood by this driver: */
232#define MODEBITS (SPI_CPOL | SPI_CPHA)
233
234static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
235 unsigned int num_transfers)
236{
237 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
238 u16 msg_ctl;
239 u16 cmd;
240 unsigned int i, timeout = 0, prepend_len = 0, len = 0;
241 struct spi_transfer *t = first;
242 bool do_rx = false;
243 bool do_tx = false;
244
245 /* Disable the CMD_DONE interrupt */
246 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
247
248 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
249 t->tx_buf, t->rx_buf, t->len);
250
251 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
252 prepend_len = t->len;
253
254 /* prepare the buffer */
255 for (i = 0; i < num_transfers; i++) {
256 if (t->tx_buf) {
257 do_tx = true;
258 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
259
260 /* don't prepend more than one tx */
261 if (t != first)
262 prepend_len = 0;
263 }
264
265 if (t->rx_buf) {
266 do_rx = true;
267 /* prepend is half-duplex write only */
268 if (t == first)
269 prepend_len = 0;
270 }
271
272 len += t->len;
273
274 t = list_entry(t->transfer_list.next, struct spi_transfer,
275 transfer_list);
276 }
277
278 reinit_completion(&bs->done);
279
280 /* Fill in the Message control register */
281 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
282
283 if (do_rx && do_tx && prepend_len == 0)
284 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
285 else if (do_rx)
286 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
287 else if (do_tx)
288 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
289
290 switch (bs->msg_ctl_width) {
291 case 8:
292 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
293 break;
294 case 16:
295 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
296 break;
297 }
298
299 /* Issue the transfer */
300 cmd = SPI_CMD_START_IMMEDIATE;
301 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
302 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
303 bcm_spi_writew(bs, cmd, SPI_CMD);
304
305 /* Enable the CMD_DONE interrupt */
306 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
307
308 timeout = wait_for_completion_timeout(&bs->done, HZ);
309 if (!timeout)
310 return -ETIMEDOUT;
311
312 if (!do_rx)
313 return 0;
314
315 len = 0;
316 t = first;
317 /* Read out all the data */
318 for (i = 0; i < num_transfers; i++) {
319 if (t->rx_buf)
320 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
321
322 if (t != first || prepend_len == 0)
323 len += t->len;
324
325 t = list_entry(t->transfer_list.next, struct spi_transfer,
326 transfer_list);
327 }
328
329 return 0;
330}
331
332static int bcm63xx_spi_transfer_one(struct spi_master *master,
333 struct spi_message *m)
334{
335 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
336 struct spi_transfer *t, *first = NULL;
337 struct spi_device *spi = m->spi;
338 int status = 0;
339 unsigned int n_transfers = 0, total_len = 0;
340 bool can_use_prepend = false;
341
342 /*
343 * This SPI controller does not support keeping CS active after a
344 * transfer.
345 * Work around this by merging as many transfers we can into one big
346 * full-duplex transfers.
347 */
348 list_for_each_entry(t, &m->transfers, transfer_list) {
349 if (!first)
350 first = t;
351
352 n_transfers++;
353 total_len += t->len;
354
355 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
356 first->len <= BCM63XX_SPI_MAX_PREPEND)
357 can_use_prepend = true;
358 else if (can_use_prepend && t->tx_buf)
359 can_use_prepend = false;
360
361 /* we can only transfer one fifo worth of data */
362 if ((can_use_prepend &&
363 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
364 (!can_use_prepend && total_len > bs->fifo_size)) {
365 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
366 total_len, bs->fifo_size);
367 status = -EINVAL;
368 goto exit;
369 }
370
371 /* all combined transfers have to have the same speed */
372 if (t->speed_hz != first->speed_hz) {
373 dev_err(&spi->dev, "unable to change speed between transfers\n");
374 status = -EINVAL;
375 goto exit;
376 }
377
378 /* CS will be deasserted directly after transfer */
379 if (t->delay_usecs) {
380 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
381 status = -EINVAL;
382 goto exit;
383 }
384
385 if (t->cs_change ||
386 list_is_last(&t->transfer_list, &m->transfers)) {
387 /* configure adapter for a new transfer */
388 bcm63xx_spi_setup_transfer(spi, first);
389
390 /* send the data */
391 status = bcm63xx_txrx_bufs(spi, first, n_transfers);
392 if (status)
393 goto exit;
394
395 m->actual_length += total_len;
396
397 first = NULL;
398 n_transfers = 0;
399 total_len = 0;
400 can_use_prepend = false;
401 }
402 }
403exit:
404 m->status = status;
405 spi_finalize_current_message(master);
406
407 return 0;
408}
409
410/* This driver supports single master mode only. Hence
411 * CMD_DONE is the only interrupt we care about
412 */
413static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
414{
415 struct spi_master *master = (struct spi_master *)dev_id;
416 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
417 u8 intr;
418
419 /* Read interupts and clear them immediately */
420 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
421 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
422 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
423
424 /* A transfer completed */
425 if (intr & SPI_INTR_CMD_DONE)
426 complete(&bs->done);
427
428 return IRQ_HANDLED;
429}
430
431static const unsigned long bcm6348_spi_reg_offsets[] = {
432 [SPI_CMD] = SPI_6348_CMD,
433 [SPI_INT_STATUS] = SPI_6348_INT_STATUS,
434 [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
435 [SPI_INT_MASK] = SPI_6348_INT_MASK,
436 [SPI_ST] = SPI_6348_ST,
437 [SPI_CLK_CFG] = SPI_6348_CLK_CFG,
438 [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
439 [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
440 [SPI_RX_TAIL] = SPI_6348_RX_TAIL,
441 [SPI_MSG_CTL] = SPI_6348_MSG_CTL,
442 [SPI_MSG_DATA] = SPI_6348_MSG_DATA,
443 [SPI_RX_DATA] = SPI_6348_RX_DATA,
444 [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
445 [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
446 [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
447};
448
449static const unsigned long bcm6358_spi_reg_offsets[] = {
450 [SPI_CMD] = SPI_6358_CMD,
451 [SPI_INT_STATUS] = SPI_6358_INT_STATUS,
452 [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
453 [SPI_INT_MASK] = SPI_6358_INT_MASK,
454 [SPI_ST] = SPI_6358_ST,
455 [SPI_CLK_CFG] = SPI_6358_CLK_CFG,
456 [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
457 [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
458 [SPI_RX_TAIL] = SPI_6358_RX_TAIL,
459 [SPI_MSG_CTL] = SPI_6358_MSG_CTL,
460 [SPI_MSG_DATA] = SPI_6358_MSG_DATA,
461 [SPI_RX_DATA] = SPI_6358_RX_DATA,
462 [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
463 [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
464 [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
465};
466
467static const struct platform_device_id bcm63xx_spi_dev_match[] = {
468 {
469 .name = "bcm6348-spi",
470 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
471 },
472 {
473 .name = "bcm6358-spi",
474 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
475 },
476 {
477 },
478};
479
480static int bcm63xx_spi_probe(struct platform_device *pdev)
481{
482 struct resource *r;
483 const unsigned long *bcm63xx_spireg;
484 struct device *dev = &pdev->dev;
485 int irq;
486 struct spi_master *master;
487 struct clk *clk;
488 struct bcm63xx_spi *bs;
489 int ret;
490
491 if (!pdev->id_entry->driver_data)
492 return -EINVAL;
493
494 bcm63xx_spireg = (const unsigned long *)pdev->id_entry->driver_data;
495
496 irq = platform_get_irq(pdev, 0);
497 if (irq < 0) {
498 dev_err(dev, "no irq\n");
499 return -ENXIO;
500 }
501
502 clk = devm_clk_get(dev, "spi");
503 if (IS_ERR(clk)) {
504 dev_err(dev, "no clock for device\n");
505 return PTR_ERR(clk);
506 }
507
508 master = spi_alloc_master(dev, sizeof(*bs));
509 if (!master) {
510 dev_err(dev, "out of memory\n");
511 return -ENOMEM;
512 }
513
514 bs = spi_master_get_devdata(master);
515 init_completion(&bs->done);
516
517 platform_set_drvdata(pdev, master);
518 bs->pdev = pdev;
519
520 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521 bs->regs = devm_ioremap_resource(&pdev->dev, r);
522 if (IS_ERR(bs->regs)) {
523 ret = PTR_ERR(bs->regs);
524 goto out_err;
525 }
526
527 bs->irq = irq;
528 bs->clk = clk;
529 bs->reg_offsets = bcm63xx_spireg;
530 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
531
532 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
533 pdev->name, master);
534 if (ret) {
535 dev_err(dev, "unable to request irq\n");
536 goto out_err;
537 }
538
539 master->bus_num = BCM63XX_SPI_BUS_NUM;
540 master->num_chipselect = BCM63XX_SPI_MAX_CS;
541 master->transfer_one_message = bcm63xx_spi_transfer_one;
542 master->mode_bits = MODEBITS;
543 master->bits_per_word_mask = SPI_BPW_MASK(8);
544 master->auto_runtime_pm = true;
545 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
546 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
547 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
548 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
549
550 /* Initialize hardware */
551 ret = clk_prepare_enable(bs->clk);
552 if (ret)
553 goto out_err;
554
555 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
556
557 /* register and we are done */
558 ret = devm_spi_register_master(dev, master);
559 if (ret) {
560 dev_err(dev, "spi register failed\n");
561 goto out_clk_disable;
562 }
563
564 dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
565 r, irq, bs->fifo_size);
566
567 return 0;
568
569out_clk_disable:
570 clk_disable_unprepare(clk);
571out_err:
572 spi_master_put(master);
573 return ret;
574}
575
576static int bcm63xx_spi_remove(struct platform_device *pdev)
577{
578 struct spi_master *master = platform_get_drvdata(pdev);
579 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
580
581 /* reset spi block */
582 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
583
584 /* HW shutdown */
585 clk_disable_unprepare(bs->clk);
586
587 return 0;
588}
589
590#ifdef CONFIG_PM_SLEEP
591static int bcm63xx_spi_suspend(struct device *dev)
592{
593 struct spi_master *master = dev_get_drvdata(dev);
594 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
595
596 spi_master_suspend(master);
597
598 clk_disable_unprepare(bs->clk);
599
600 return 0;
601}
602
603static int bcm63xx_spi_resume(struct device *dev)
604{
605 struct spi_master *master = dev_get_drvdata(dev);
606 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
607 int ret;
608
609 ret = clk_prepare_enable(bs->clk);
610 if (ret)
611 return ret;
612
613 spi_master_resume(master);
614
615 return 0;
616}
617#endif
618
619static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
620 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
621};
622
623static struct platform_driver bcm63xx_spi_driver = {
624 .driver = {
625 .name = "bcm63xx-spi",
626 .pm = &bcm63xx_spi_pm_ops,
627 },
628 .id_table = bcm63xx_spi_dev_match,
629 .probe = bcm63xx_spi_probe,
630 .remove = bcm63xx_spi_remove,
631};
632
633module_platform_driver(bcm63xx_spi_driver);
634
635MODULE_ALIAS("platform:bcm63xx_spi");
636MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
637MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
638MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
639MODULE_LICENSE("GPL");
1/*
2 * Broadcom BCM63xx SPI controller support
3 *
4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 */
21
22#include <linux/kernel.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/spi/spi.h>
30#include <linux/completion.h>
31#include <linux/err.h>
32#include <linux/workqueue.h>
33#include <linux/pm_runtime.h>
34
35#include <bcm63xx_dev_spi.h>
36
37#define BCM63XX_SPI_MAX_PREPEND 15
38
39struct bcm63xx_spi {
40 struct completion done;
41
42 void __iomem *regs;
43 int irq;
44
45 /* Platform data */
46 unsigned fifo_size;
47 unsigned int msg_type_shift;
48 unsigned int msg_ctl_width;
49
50 /* data iomem */
51 u8 __iomem *tx_io;
52 const u8 __iomem *rx_io;
53
54 struct clk *clk;
55 struct platform_device *pdev;
56};
57
58static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
59 unsigned int offset)
60{
61 return bcm_readb(bs->regs + bcm63xx_spireg(offset));
62}
63
64static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
65 unsigned int offset)
66{
67 return bcm_readw(bs->regs + bcm63xx_spireg(offset));
68}
69
70static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
71 u8 value, unsigned int offset)
72{
73 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
74}
75
76static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
77 u16 value, unsigned int offset)
78{
79 bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
80}
81
82static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
83 { 20000000, SPI_CLK_20MHZ },
84 { 12500000, SPI_CLK_12_50MHZ },
85 { 6250000, SPI_CLK_6_250MHZ },
86 { 3125000, SPI_CLK_3_125MHZ },
87 { 1563000, SPI_CLK_1_563MHZ },
88 { 781000, SPI_CLK_0_781MHZ },
89 { 391000, SPI_CLK_0_391MHZ }
90};
91
92static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
93 struct spi_transfer *t)
94{
95 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
96 u8 clk_cfg, reg;
97 int i;
98
99 /* Find the closest clock configuration */
100 for (i = 0; i < SPI_CLK_MASK; i++) {
101 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
102 clk_cfg = bcm63xx_spi_freq_table[i][1];
103 break;
104 }
105 }
106
107 /* No matching configuration found, default to lowest */
108 if (i == SPI_CLK_MASK)
109 clk_cfg = SPI_CLK_0_391MHZ;
110
111 /* clear existing clock configuration bits of the register */
112 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
113 reg &= ~SPI_CLK_MASK;
114 reg |= clk_cfg;
115
116 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
117 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
118 clk_cfg, t->speed_hz);
119}
120
121/* the spi->mode bits understood by this driver: */
122#define MODEBITS (SPI_CPOL | SPI_CPHA)
123
124static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
125 unsigned int num_transfers)
126{
127 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
128 u16 msg_ctl;
129 u16 cmd;
130 u8 rx_tail;
131 unsigned int i, timeout = 0, prepend_len = 0, len = 0;
132 struct spi_transfer *t = first;
133 bool do_rx = false;
134 bool do_tx = false;
135
136 /* Disable the CMD_DONE interrupt */
137 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
138
139 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
140 t->tx_buf, t->rx_buf, t->len);
141
142 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
143 prepend_len = t->len;
144
145 /* prepare the buffer */
146 for (i = 0; i < num_transfers; i++) {
147 if (t->tx_buf) {
148 do_tx = true;
149 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
150
151 /* don't prepend more than one tx */
152 if (t != first)
153 prepend_len = 0;
154 }
155
156 if (t->rx_buf) {
157 do_rx = true;
158 /* prepend is half-duplex write only */
159 if (t == first)
160 prepend_len = 0;
161 }
162
163 len += t->len;
164
165 t = list_entry(t->transfer_list.next, struct spi_transfer,
166 transfer_list);
167 }
168
169 reinit_completion(&bs->done);
170
171 /* Fill in the Message control register */
172 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
173
174 if (do_rx && do_tx && prepend_len == 0)
175 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
176 else if (do_rx)
177 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
178 else if (do_tx)
179 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
180
181 switch (bs->msg_ctl_width) {
182 case 8:
183 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
184 break;
185 case 16:
186 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
187 break;
188 }
189
190 /* Issue the transfer */
191 cmd = SPI_CMD_START_IMMEDIATE;
192 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
193 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
194 bcm_spi_writew(bs, cmd, SPI_CMD);
195
196 /* Enable the CMD_DONE interrupt */
197 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
198
199 timeout = wait_for_completion_timeout(&bs->done, HZ);
200 if (!timeout)
201 return -ETIMEDOUT;
202
203 if (!do_rx)
204 return 0;
205
206 len = 0;
207 t = first;
208 /* Read out all the data */
209 for (i = 0; i < num_transfers; i++) {
210 if (t->rx_buf)
211 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
212
213 if (t != first || prepend_len == 0)
214 len += t->len;
215
216 t = list_entry(t->transfer_list.next, struct spi_transfer,
217 transfer_list);
218 }
219
220 return 0;
221}
222
223static int bcm63xx_spi_transfer_one(struct spi_master *master,
224 struct spi_message *m)
225{
226 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
227 struct spi_transfer *t, *first = NULL;
228 struct spi_device *spi = m->spi;
229 int status = 0;
230 unsigned int n_transfers = 0, total_len = 0;
231 bool can_use_prepend = false;
232
233 /*
234 * This SPI controller does not support keeping CS active after a
235 * transfer.
236 * Work around this by merging as many transfers we can into one big
237 * full-duplex transfers.
238 */
239 list_for_each_entry(t, &m->transfers, transfer_list) {
240 if (!first)
241 first = t;
242
243 n_transfers++;
244 total_len += t->len;
245
246 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
247 first->len <= BCM63XX_SPI_MAX_PREPEND)
248 can_use_prepend = true;
249 else if (can_use_prepend && t->tx_buf)
250 can_use_prepend = false;
251
252 /* we can only transfer one fifo worth of data */
253 if ((can_use_prepend &&
254 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
255 (!can_use_prepend && total_len > bs->fifo_size)) {
256 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
257 total_len, bs->fifo_size);
258 status = -EINVAL;
259 goto exit;
260 }
261
262 /* all combined transfers have to have the same speed */
263 if (t->speed_hz != first->speed_hz) {
264 dev_err(&spi->dev, "unable to change speed between transfers\n");
265 status = -EINVAL;
266 goto exit;
267 }
268
269 /* CS will be deasserted directly after transfer */
270 if (t->delay_usecs) {
271 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
272 status = -EINVAL;
273 goto exit;
274 }
275
276 if (t->cs_change ||
277 list_is_last(&t->transfer_list, &m->transfers)) {
278 /* configure adapter for a new transfer */
279 bcm63xx_spi_setup_transfer(spi, first);
280
281 /* send the data */
282 status = bcm63xx_txrx_bufs(spi, first, n_transfers);
283 if (status)
284 goto exit;
285
286 m->actual_length += total_len;
287
288 first = NULL;
289 n_transfers = 0;
290 total_len = 0;
291 can_use_prepend = false;
292 }
293 }
294exit:
295 m->status = status;
296 spi_finalize_current_message(master);
297
298 return 0;
299}
300
301/* This driver supports single master mode only. Hence
302 * CMD_DONE is the only interrupt we care about
303 */
304static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
305{
306 struct spi_master *master = (struct spi_master *)dev_id;
307 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
308 u8 intr;
309
310 /* Read interupts and clear them immediately */
311 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
312 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
313 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
314
315 /* A transfer completed */
316 if (intr & SPI_INTR_CMD_DONE)
317 complete(&bs->done);
318
319 return IRQ_HANDLED;
320}
321
322
323static int bcm63xx_spi_probe(struct platform_device *pdev)
324{
325 struct resource *r;
326 struct device *dev = &pdev->dev;
327 struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev);
328 int irq;
329 struct spi_master *master;
330 struct clk *clk;
331 struct bcm63xx_spi *bs;
332 int ret;
333
334 irq = platform_get_irq(pdev, 0);
335 if (irq < 0) {
336 dev_err(dev, "no irq\n");
337 return -ENXIO;
338 }
339
340 clk = devm_clk_get(dev, "spi");
341 if (IS_ERR(clk)) {
342 dev_err(dev, "no clock for device\n");
343 return PTR_ERR(clk);
344 }
345
346 master = spi_alloc_master(dev, sizeof(*bs));
347 if (!master) {
348 dev_err(dev, "out of memory\n");
349 return -ENOMEM;
350 }
351
352 bs = spi_master_get_devdata(master);
353 init_completion(&bs->done);
354
355 platform_set_drvdata(pdev, master);
356 bs->pdev = pdev;
357
358 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359 bs->regs = devm_ioremap_resource(&pdev->dev, r);
360 if (IS_ERR(bs->regs)) {
361 ret = PTR_ERR(bs->regs);
362 goto out_err;
363 }
364
365 bs->irq = irq;
366 bs->clk = clk;
367 bs->fifo_size = pdata->fifo_size;
368
369 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
370 pdev->name, master);
371 if (ret) {
372 dev_err(dev, "unable to request irq\n");
373 goto out_err;
374 }
375
376 master->bus_num = pdata->bus_num;
377 master->num_chipselect = pdata->num_chipselect;
378 master->transfer_one_message = bcm63xx_spi_transfer_one;
379 master->mode_bits = MODEBITS;
380 master->bits_per_word_mask = SPI_BPW_MASK(8);
381 master->auto_runtime_pm = true;
382 bs->msg_type_shift = pdata->msg_type_shift;
383 bs->msg_ctl_width = pdata->msg_ctl_width;
384 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
385 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
386
387 switch (bs->msg_ctl_width) {
388 case 8:
389 case 16:
390 break;
391 default:
392 dev_err(dev, "unsupported MSG_CTL width: %d\n",
393 bs->msg_ctl_width);
394 goto out_err;
395 }
396
397 /* Initialize hardware */
398 ret = clk_prepare_enable(bs->clk);
399 if (ret)
400 goto out_err;
401
402 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
403
404 /* register and we are done */
405 ret = devm_spi_register_master(dev, master);
406 if (ret) {
407 dev_err(dev, "spi register failed\n");
408 goto out_clk_disable;
409 }
410
411 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
412 r->start, irq, bs->fifo_size);
413
414 return 0;
415
416out_clk_disable:
417 clk_disable_unprepare(clk);
418out_err:
419 spi_master_put(master);
420 return ret;
421}
422
423static int bcm63xx_spi_remove(struct platform_device *pdev)
424{
425 struct spi_master *master = platform_get_drvdata(pdev);
426 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
427
428 /* reset spi block */
429 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
430
431 /* HW shutdown */
432 clk_disable_unprepare(bs->clk);
433
434 return 0;
435}
436
437#ifdef CONFIG_PM_SLEEP
438static int bcm63xx_spi_suspend(struct device *dev)
439{
440 struct spi_master *master = dev_get_drvdata(dev);
441 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
442
443 spi_master_suspend(master);
444
445 clk_disable_unprepare(bs->clk);
446
447 return 0;
448}
449
450static int bcm63xx_spi_resume(struct device *dev)
451{
452 struct spi_master *master = dev_get_drvdata(dev);
453 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
454 int ret;
455
456 ret = clk_prepare_enable(bs->clk);
457 if (ret)
458 return ret;
459
460 spi_master_resume(master);
461
462 return 0;
463}
464#endif
465
466static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
467 SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
468};
469
470static struct platform_driver bcm63xx_spi_driver = {
471 .driver = {
472 .name = "bcm63xx-spi",
473 .owner = THIS_MODULE,
474 .pm = &bcm63xx_spi_pm_ops,
475 },
476 .probe = bcm63xx_spi_probe,
477 .remove = bcm63xx_spi_remove,
478};
479
480module_platform_driver(bcm63xx_spi_driver);
481
482MODULE_ALIAS("platform:bcm63xx_spi");
483MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
484MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
485MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
486MODULE_LICENSE("GPL");