Loading...
1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/pwm.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22
23/* i.MX1 and i.MX21 share the same PWM function block: */
24
25#define MX1_PWMC 0x00 /* PWM Control Register */
26#define MX1_PWMS 0x04 /* PWM Sample Register */
27#define MX1_PWMP 0x08 /* PWM Period Register */
28
29#define MX1_PWMC_EN (1 << 4)
30
31/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
32
33#define MX3_PWMCR 0x00 /* PWM Control Register */
34#define MX3_PWMSR 0x04 /* PWM Status Register */
35#define MX3_PWMSAR 0x0C /* PWM Sample Register */
36#define MX3_PWMPR 0x10 /* PWM Period Register */
37#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
38#define MX3_PWMCR_DOZEEN (1 << 24)
39#define MX3_PWMCR_WAITEN (1 << 23)
40#define MX3_PWMCR_DBGEN (1 << 22)
41#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
42#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
43#define MX3_PWMCR_SWR (1 << 3)
44#define MX3_PWMCR_EN (1 << 0)
45#define MX3_PWMSR_FIFOAV_4WORDS 0x4
46#define MX3_PWMSR_FIFOAV_MASK 0x7
47
48#define MX3_PWM_SWR_LOOP 5
49
50struct imx_chip {
51 struct clk *clk_per;
52 struct clk *clk_ipg;
53
54 void __iomem *mmio_base;
55
56 struct pwm_chip chip;
57
58 int (*config)(struct pwm_chip *chip,
59 struct pwm_device *pwm, int duty_ns, int period_ns);
60 void (*set_enable)(struct pwm_chip *chip, bool enable);
61};
62
63#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
64
65static int imx_pwm_config_v1(struct pwm_chip *chip,
66 struct pwm_device *pwm, int duty_ns, int period_ns)
67{
68 struct imx_chip *imx = to_imx_chip(chip);
69
70 /*
71 * The PWM subsystem allows for exact frequencies. However,
72 * I cannot connect a scope on my device to the PWM line and
73 * thus cannot provide the program the PWM controller
74 * exactly. Instead, I'm relying on the fact that the
75 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
76 * function group already. So I'll just modify the PWM sample
77 * register to follow the ratio of duty_ns vs. period_ns
78 * accordingly.
79 *
80 * This is good enough for programming the brightness of
81 * the LCD backlight.
82 *
83 * The real implementation would divide PERCLK[0] first by
84 * both the prescaler (/1 .. /128) and then by CLKSEL
85 * (/2 .. /16).
86 */
87 u32 max = readl(imx->mmio_base + MX1_PWMP);
88 u32 p = max * duty_ns / period_ns;
89 writel(max - p, imx->mmio_base + MX1_PWMS);
90
91 return 0;
92}
93
94static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
95{
96 struct imx_chip *imx = to_imx_chip(chip);
97 u32 val;
98
99 val = readl(imx->mmio_base + MX1_PWMC);
100
101 if (enable)
102 val |= MX1_PWMC_EN;
103 else
104 val &= ~MX1_PWMC_EN;
105
106 writel(val, imx->mmio_base + MX1_PWMC);
107}
108
109static int imx_pwm_config_v2(struct pwm_chip *chip,
110 struct pwm_device *pwm, int duty_ns, int period_ns)
111{
112 struct imx_chip *imx = to_imx_chip(chip);
113 struct device *dev = chip->dev;
114 unsigned long long c;
115 unsigned long period_cycles, duty_cycles, prescale;
116 unsigned int period_ms;
117 bool enable = pwm_is_enabled(pwm);
118 int wait_count = 0, fifoav;
119 u32 cr, sr;
120
121 /*
122 * i.MX PWMv2 has a 4-word sample FIFO.
123 * In order to avoid FIFO overflow issue, we do software reset
124 * to clear all sample FIFO if the controller is disabled or
125 * wait for a full PWM cycle to get a relinquished FIFO slot
126 * when the controller is enabled and the FIFO is fully loaded.
127 */
128 if (enable) {
129 sr = readl(imx->mmio_base + MX3_PWMSR);
130 fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
131 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
132 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
133 NSEC_PER_MSEC);
134 msleep(period_ms);
135
136 sr = readl(imx->mmio_base + MX3_PWMSR);
137 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
138 dev_warn(dev, "there is no free FIFO slot\n");
139 }
140 } else {
141 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
142 do {
143 usleep_range(200, 1000);
144 cr = readl(imx->mmio_base + MX3_PWMCR);
145 } while ((cr & MX3_PWMCR_SWR) &&
146 (wait_count++ < MX3_PWM_SWR_LOOP));
147
148 if (cr & MX3_PWMCR_SWR)
149 dev_warn(dev, "software reset timeout\n");
150 }
151
152 c = clk_get_rate(imx->clk_per);
153 c = c * period_ns;
154 do_div(c, 1000000000);
155 period_cycles = c;
156
157 prescale = period_cycles / 0x10000 + 1;
158
159 period_cycles /= prescale;
160 c = (unsigned long long)period_cycles * duty_ns;
161 do_div(c, period_ns);
162 duty_cycles = c;
163
164 /*
165 * according to imx pwm RM, the real period value should be
166 * PERIOD value in PWMPR plus 2.
167 */
168 if (period_cycles > 2)
169 period_cycles -= 2;
170 else
171 period_cycles = 0;
172
173 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
174 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
175
176 cr = MX3_PWMCR_PRESCALER(prescale) |
177 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
178 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
179
180 if (enable)
181 cr |= MX3_PWMCR_EN;
182
183 writel(cr, imx->mmio_base + MX3_PWMCR);
184
185 return 0;
186}
187
188static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
189{
190 struct imx_chip *imx = to_imx_chip(chip);
191 u32 val;
192
193 val = readl(imx->mmio_base + MX3_PWMCR);
194
195 if (enable)
196 val |= MX3_PWMCR_EN;
197 else
198 val &= ~MX3_PWMCR_EN;
199
200 writel(val, imx->mmio_base + MX3_PWMCR);
201}
202
203static int imx_pwm_config(struct pwm_chip *chip,
204 struct pwm_device *pwm, int duty_ns, int period_ns)
205{
206 struct imx_chip *imx = to_imx_chip(chip);
207 int ret;
208
209 ret = clk_prepare_enable(imx->clk_ipg);
210 if (ret)
211 return ret;
212
213 ret = imx->config(chip, pwm, duty_ns, period_ns);
214
215 clk_disable_unprepare(imx->clk_ipg);
216
217 return ret;
218}
219
220static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
221{
222 struct imx_chip *imx = to_imx_chip(chip);
223 int ret;
224
225 ret = clk_prepare_enable(imx->clk_per);
226 if (ret)
227 return ret;
228
229 imx->set_enable(chip, true);
230
231 return 0;
232}
233
234static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
235{
236 struct imx_chip *imx = to_imx_chip(chip);
237
238 imx->set_enable(chip, false);
239
240 clk_disable_unprepare(imx->clk_per);
241}
242
243static struct pwm_ops imx_pwm_ops = {
244 .enable = imx_pwm_enable,
245 .disable = imx_pwm_disable,
246 .config = imx_pwm_config,
247 .owner = THIS_MODULE,
248};
249
250struct imx_pwm_data {
251 int (*config)(struct pwm_chip *chip,
252 struct pwm_device *pwm, int duty_ns, int period_ns);
253 void (*set_enable)(struct pwm_chip *chip, bool enable);
254};
255
256static struct imx_pwm_data imx_pwm_data_v1 = {
257 .config = imx_pwm_config_v1,
258 .set_enable = imx_pwm_set_enable_v1,
259};
260
261static struct imx_pwm_data imx_pwm_data_v2 = {
262 .config = imx_pwm_config_v2,
263 .set_enable = imx_pwm_set_enable_v2,
264};
265
266static const struct of_device_id imx_pwm_dt_ids[] = {
267 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
268 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
269 { /* sentinel */ }
270};
271MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
272
273static int imx_pwm_probe(struct platform_device *pdev)
274{
275 const struct of_device_id *of_id =
276 of_match_device(imx_pwm_dt_ids, &pdev->dev);
277 const struct imx_pwm_data *data;
278 struct imx_chip *imx;
279 struct resource *r;
280 int ret = 0;
281
282 if (!of_id)
283 return -ENODEV;
284
285 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
286 if (imx == NULL)
287 return -ENOMEM;
288
289 imx->clk_per = devm_clk_get(&pdev->dev, "per");
290 if (IS_ERR(imx->clk_per)) {
291 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
292 PTR_ERR(imx->clk_per));
293 return PTR_ERR(imx->clk_per);
294 }
295
296 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
297 if (IS_ERR(imx->clk_ipg)) {
298 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
299 PTR_ERR(imx->clk_ipg));
300 return PTR_ERR(imx->clk_ipg);
301 }
302
303 imx->chip.ops = &imx_pwm_ops;
304 imx->chip.dev = &pdev->dev;
305 imx->chip.base = -1;
306 imx->chip.npwm = 1;
307 imx->chip.can_sleep = true;
308
309 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
310 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
311 if (IS_ERR(imx->mmio_base))
312 return PTR_ERR(imx->mmio_base);
313
314 data = of_id->data;
315 imx->config = data->config;
316 imx->set_enable = data->set_enable;
317
318 ret = pwmchip_add(&imx->chip);
319 if (ret < 0)
320 return ret;
321
322 platform_set_drvdata(pdev, imx);
323 return 0;
324}
325
326static int imx_pwm_remove(struct platform_device *pdev)
327{
328 struct imx_chip *imx;
329
330 imx = platform_get_drvdata(pdev);
331 if (imx == NULL)
332 return -ENODEV;
333
334 return pwmchip_remove(&imx->chip);
335}
336
337static struct platform_driver imx_pwm_driver = {
338 .driver = {
339 .name = "imx-pwm",
340 .of_match_table = imx_pwm_dt_ids,
341 },
342 .probe = imx_pwm_probe,
343 .remove = imx_pwm_remove,
344};
345
346module_platform_driver(imx_pwm_driver);
347
348MODULE_LICENSE("GPL v2");
349MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/pwm.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21
22/* i.MX1 and i.MX21 share the same PWM function block: */
23
24#define MX1_PWMC 0x00 /* PWM Control Register */
25#define MX1_PWMS 0x04 /* PWM Sample Register */
26#define MX1_PWMP 0x08 /* PWM Period Register */
27
28#define MX1_PWMC_EN (1 << 4)
29
30/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
31
32#define MX3_PWMCR 0x00 /* PWM Control Register */
33#define MX3_PWMSAR 0x0C /* PWM Sample Register */
34#define MX3_PWMPR 0x10 /* PWM Period Register */
35#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
36#define MX3_PWMCR_DOZEEN (1 << 24)
37#define MX3_PWMCR_WAITEN (1 << 23)
38#define MX3_PWMCR_DBGEN (1 << 22)
39#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
41#define MX3_PWMCR_EN (1 << 0)
42
43struct imx_chip {
44 struct clk *clk_per;
45 struct clk *clk_ipg;
46
47 void __iomem *mmio_base;
48
49 struct pwm_chip chip;
50
51 int (*config)(struct pwm_chip *chip,
52 struct pwm_device *pwm, int duty_ns, int period_ns);
53 void (*set_enable)(struct pwm_chip *chip, bool enable);
54};
55
56#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
57
58static int imx_pwm_config_v1(struct pwm_chip *chip,
59 struct pwm_device *pwm, int duty_ns, int period_ns)
60{
61 struct imx_chip *imx = to_imx_chip(chip);
62
63 /*
64 * The PWM subsystem allows for exact frequencies. However,
65 * I cannot connect a scope on my device to the PWM line and
66 * thus cannot provide the program the PWM controller
67 * exactly. Instead, I'm relying on the fact that the
68 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
69 * function group already. So I'll just modify the PWM sample
70 * register to follow the ratio of duty_ns vs. period_ns
71 * accordingly.
72 *
73 * This is good enough for programming the brightness of
74 * the LCD backlight.
75 *
76 * The real implementation would divide PERCLK[0] first by
77 * both the prescaler (/1 .. /128) and then by CLKSEL
78 * (/2 .. /16).
79 */
80 u32 max = readl(imx->mmio_base + MX1_PWMP);
81 u32 p = max * duty_ns / period_ns;
82 writel(max - p, imx->mmio_base + MX1_PWMS);
83
84 return 0;
85}
86
87static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
88{
89 struct imx_chip *imx = to_imx_chip(chip);
90 u32 val;
91
92 val = readl(imx->mmio_base + MX1_PWMC);
93
94 if (enable)
95 val |= MX1_PWMC_EN;
96 else
97 val &= ~MX1_PWMC_EN;
98
99 writel(val, imx->mmio_base + MX1_PWMC);
100}
101
102static int imx_pwm_config_v2(struct pwm_chip *chip,
103 struct pwm_device *pwm, int duty_ns, int period_ns)
104{
105 struct imx_chip *imx = to_imx_chip(chip);
106 unsigned long long c;
107 unsigned long period_cycles, duty_cycles, prescale;
108 u32 cr;
109
110 c = clk_get_rate(imx->clk_per);
111 c = c * period_ns;
112 do_div(c, 1000000000);
113 period_cycles = c;
114
115 prescale = period_cycles / 0x10000 + 1;
116
117 period_cycles /= prescale;
118 c = (unsigned long long)period_cycles * duty_ns;
119 do_div(c, period_ns);
120 duty_cycles = c;
121
122 /*
123 * according to imx pwm RM, the real period value should be
124 * PERIOD value in PWMPR plus 2.
125 */
126 if (period_cycles > 2)
127 period_cycles -= 2;
128 else
129 period_cycles = 0;
130
131 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
132 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
133
134 cr = MX3_PWMCR_PRESCALER(prescale) |
135 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
136 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
137
138 if (test_bit(PWMF_ENABLED, &pwm->flags))
139 cr |= MX3_PWMCR_EN;
140
141 writel(cr, imx->mmio_base + MX3_PWMCR);
142
143 return 0;
144}
145
146static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
147{
148 struct imx_chip *imx = to_imx_chip(chip);
149 u32 val;
150
151 val = readl(imx->mmio_base + MX3_PWMCR);
152
153 if (enable)
154 val |= MX3_PWMCR_EN;
155 else
156 val &= ~MX3_PWMCR_EN;
157
158 writel(val, imx->mmio_base + MX3_PWMCR);
159}
160
161static int imx_pwm_config(struct pwm_chip *chip,
162 struct pwm_device *pwm, int duty_ns, int period_ns)
163{
164 struct imx_chip *imx = to_imx_chip(chip);
165 int ret;
166
167 ret = clk_prepare_enable(imx->clk_ipg);
168 if (ret)
169 return ret;
170
171 ret = imx->config(chip, pwm, duty_ns, period_ns);
172
173 clk_disable_unprepare(imx->clk_ipg);
174
175 return ret;
176}
177
178static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
179{
180 struct imx_chip *imx = to_imx_chip(chip);
181 int ret;
182
183 ret = clk_prepare_enable(imx->clk_per);
184 if (ret)
185 return ret;
186
187 imx->set_enable(chip, true);
188
189 return 0;
190}
191
192static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
193{
194 struct imx_chip *imx = to_imx_chip(chip);
195
196 imx->set_enable(chip, false);
197
198 clk_disable_unprepare(imx->clk_per);
199}
200
201static struct pwm_ops imx_pwm_ops = {
202 .enable = imx_pwm_enable,
203 .disable = imx_pwm_disable,
204 .config = imx_pwm_config,
205 .owner = THIS_MODULE,
206};
207
208struct imx_pwm_data {
209 int (*config)(struct pwm_chip *chip,
210 struct pwm_device *pwm, int duty_ns, int period_ns);
211 void (*set_enable)(struct pwm_chip *chip, bool enable);
212};
213
214static struct imx_pwm_data imx_pwm_data_v1 = {
215 .config = imx_pwm_config_v1,
216 .set_enable = imx_pwm_set_enable_v1,
217};
218
219static struct imx_pwm_data imx_pwm_data_v2 = {
220 .config = imx_pwm_config_v2,
221 .set_enable = imx_pwm_set_enable_v2,
222};
223
224static const struct of_device_id imx_pwm_dt_ids[] = {
225 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
226 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
227 { /* sentinel */ }
228};
229MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
230
231static int imx_pwm_probe(struct platform_device *pdev)
232{
233 const struct of_device_id *of_id =
234 of_match_device(imx_pwm_dt_ids, &pdev->dev);
235 const struct imx_pwm_data *data;
236 struct imx_chip *imx;
237 struct resource *r;
238 int ret = 0;
239
240 if (!of_id)
241 return -ENODEV;
242
243 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
244 if (imx == NULL) {
245 dev_err(&pdev->dev, "failed to allocate memory\n");
246 return -ENOMEM;
247 }
248
249 imx->clk_per = devm_clk_get(&pdev->dev, "per");
250 if (IS_ERR(imx->clk_per)) {
251 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
252 PTR_ERR(imx->clk_per));
253 return PTR_ERR(imx->clk_per);
254 }
255
256 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
257 if (IS_ERR(imx->clk_ipg)) {
258 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
259 PTR_ERR(imx->clk_ipg));
260 return PTR_ERR(imx->clk_ipg);
261 }
262
263 imx->chip.ops = &imx_pwm_ops;
264 imx->chip.dev = &pdev->dev;
265 imx->chip.base = -1;
266 imx->chip.npwm = 1;
267
268 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
270 if (IS_ERR(imx->mmio_base))
271 return PTR_ERR(imx->mmio_base);
272
273 data = of_id->data;
274 imx->config = data->config;
275 imx->set_enable = data->set_enable;
276
277 ret = pwmchip_add(&imx->chip);
278 if (ret < 0)
279 return ret;
280
281 platform_set_drvdata(pdev, imx);
282 return 0;
283}
284
285static int imx_pwm_remove(struct platform_device *pdev)
286{
287 struct imx_chip *imx;
288
289 imx = platform_get_drvdata(pdev);
290 if (imx == NULL)
291 return -ENODEV;
292
293 return pwmchip_remove(&imx->chip);
294}
295
296static struct platform_driver imx_pwm_driver = {
297 .driver = {
298 .name = "imx-pwm",
299 .owner = THIS_MODULE,
300 .of_match_table = imx_pwm_dt_ids,
301 },
302 .probe = imx_pwm_probe,
303 .remove = imx_pwm_remove,
304};
305
306module_platform_driver(imx_pwm_driver);
307
308MODULE_LICENSE("GPL v2");
309MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");