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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <drm/drmP.h>
30#include "radeon.h"
31
32/*
33 * Rings
34 * Most engines on the GPU are fed via ring buffers. Ring
35 * buffers are areas of GPU accessible memory that the host
36 * writes commands into and the GPU reads commands out of.
37 * There is a rptr (read pointer) that determines where the
38 * GPU is currently reading, and a wptr (write pointer)
39 * which determines where the host has written. When the
40 * pointers are equal, the ring is idle. When the host
41 * writes commands to the ring buffer, it increments the
42 * wptr. The GPU then starts fetching commands and executes
43 * them until the pointers are equal again.
44 */
45static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
46
47/**
48 * radeon_ring_supports_scratch_reg - check if the ring supports
49 * writing to scratch registers
50 *
51 * @rdev: radeon_device pointer
52 * @ring: radeon_ring structure holding ring information
53 *
54 * Check if a specific ring supports writing to scratch registers (all asics).
55 * Returns true if the ring supports writing to scratch regs, false if not.
56 */
57bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
58 struct radeon_ring *ring)
59{
60 switch (ring->idx) {
61 case RADEON_RING_TYPE_GFX_INDEX:
62 case CAYMAN_RING_TYPE_CP1_INDEX:
63 case CAYMAN_RING_TYPE_CP2_INDEX:
64 return true;
65 default:
66 return false;
67 }
68}
69
70/**
71 * radeon_ring_free_size - update the free size
72 *
73 * @rdev: radeon_device pointer
74 * @ring: radeon_ring structure holding ring information
75 *
76 * Update the free dw slots in the ring buffer (all asics).
77 */
78void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
79{
80 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
81
82 /* This works because ring_size is a power of 2 */
83 ring->ring_free_dw = rptr + (ring->ring_size / 4);
84 ring->ring_free_dw -= ring->wptr;
85 ring->ring_free_dw &= ring->ptr_mask;
86 if (!ring->ring_free_dw) {
87 /* this is an empty ring */
88 ring->ring_free_dw = ring->ring_size / 4;
89 /* update lockup info to avoid false positive */
90 radeon_ring_lockup_update(rdev, ring);
91 }
92}
93
94/**
95 * radeon_ring_alloc - allocate space on the ring buffer
96 *
97 * @rdev: radeon_device pointer
98 * @ring: radeon_ring structure holding ring information
99 * @ndw: number of dwords to allocate in the ring buffer
100 *
101 * Allocate @ndw dwords in the ring buffer (all asics).
102 * Returns 0 on success, error on failure.
103 */
104int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
105{
106 int r;
107
108 /* make sure we aren't trying to allocate more space than there is on the ring */
109 if (ndw > (ring->ring_size / 4))
110 return -ENOMEM;
111 /* Align requested size with padding so unlock_commit can
112 * pad safely */
113 radeon_ring_free_size(rdev, ring);
114 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
115 while (ndw > (ring->ring_free_dw - 1)) {
116 radeon_ring_free_size(rdev, ring);
117 if (ndw < ring->ring_free_dw) {
118 break;
119 }
120 r = radeon_fence_wait_next(rdev, ring->idx);
121 if (r)
122 return r;
123 }
124 ring->count_dw = ndw;
125 ring->wptr_old = ring->wptr;
126 return 0;
127}
128
129/**
130 * radeon_ring_lock - lock the ring and allocate space on it
131 *
132 * @rdev: radeon_device pointer
133 * @ring: radeon_ring structure holding ring information
134 * @ndw: number of dwords to allocate in the ring buffer
135 *
136 * Lock the ring and allocate @ndw dwords in the ring buffer
137 * (all asics).
138 * Returns 0 on success, error on failure.
139 */
140int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
141{
142 int r;
143
144 mutex_lock(&rdev->ring_lock);
145 r = radeon_ring_alloc(rdev, ring, ndw);
146 if (r) {
147 mutex_unlock(&rdev->ring_lock);
148 return r;
149 }
150 return 0;
151}
152
153/**
154 * radeon_ring_commit - tell the GPU to execute the new
155 * commands on the ring buffer
156 *
157 * @rdev: radeon_device pointer
158 * @ring: radeon_ring structure holding ring information
159 * @hdp_flush: Whether or not to perform an HDP cache flush
160 *
161 * Update the wptr (write pointer) to tell the GPU to
162 * execute new commands on the ring buffer (all asics).
163 */
164void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,
165 bool hdp_flush)
166{
167 /* If we are emitting the HDP flush via the ring buffer, we need to
168 * do it before padding.
169 */
170 if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)
171 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);
172 /* We pad to match fetch size */
173 while (ring->wptr & ring->align_mask) {
174 radeon_ring_write(ring, ring->nop);
175 }
176 mb();
177 /* If we are emitting the HDP flush via MMIO, we need to do it after
178 * all CPU writes to VRAM finished.
179 */
180 if (hdp_flush && rdev->asic->mmio_hdp_flush)
181 rdev->asic->mmio_hdp_flush(rdev);
182 radeon_ring_set_wptr(rdev, ring);
183}
184
185/**
186 * radeon_ring_unlock_commit - tell the GPU to execute the new
187 * commands on the ring buffer and unlock it
188 *
189 * @rdev: radeon_device pointer
190 * @ring: radeon_ring structure holding ring information
191 * @hdp_flush: Whether or not to perform an HDP cache flush
192 *
193 * Call radeon_ring_commit() then unlock the ring (all asics).
194 */
195void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,
196 bool hdp_flush)
197{
198 radeon_ring_commit(rdev, ring, hdp_flush);
199 mutex_unlock(&rdev->ring_lock);
200}
201
202/**
203 * radeon_ring_undo - reset the wptr
204 *
205 * @ring: radeon_ring structure holding ring information
206 *
207 * Reset the driver's copy of the wptr (all asics).
208 */
209void radeon_ring_undo(struct radeon_ring *ring)
210{
211 ring->wptr = ring->wptr_old;
212}
213
214/**
215 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
216 *
217 * @ring: radeon_ring structure holding ring information
218 *
219 * Call radeon_ring_undo() then unlock the ring (all asics).
220 */
221void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
222{
223 radeon_ring_undo(ring);
224 mutex_unlock(&rdev->ring_lock);
225}
226
227/**
228 * radeon_ring_lockup_update - update lockup variables
229 *
230 * @ring: radeon_ring structure holding ring information
231 *
232 * Update the last rptr value and timestamp (all asics).
233 */
234void radeon_ring_lockup_update(struct radeon_device *rdev,
235 struct radeon_ring *ring)
236{
237 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
238 atomic64_set(&ring->last_activity, jiffies_64);
239}
240
241/**
242 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
243 * @rdev: radeon device structure
244 * @ring: radeon_ring structure holding ring information
245 *
246 */
247bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
248{
249 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
250 uint64_t last = atomic64_read(&ring->last_activity);
251 uint64_t elapsed;
252
253 if (rptr != atomic_read(&ring->last_rptr)) {
254 /* ring is still working, no lockup */
255 radeon_ring_lockup_update(rdev, ring);
256 return false;
257 }
258
259 elapsed = jiffies_to_msecs(jiffies_64 - last);
260 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
261 dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
262 ring->idx, elapsed);
263 return true;
264 }
265 /* give a chance to the GPU ... */
266 return false;
267}
268
269/**
270 * radeon_ring_backup - Back up the content of a ring
271 *
272 * @rdev: radeon_device pointer
273 * @ring: the ring we want to back up
274 *
275 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
276 */
277unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
278 uint32_t **data)
279{
280 unsigned size, ptr, i;
281
282 /* just in case lock the ring */
283 mutex_lock(&rdev->ring_lock);
284 *data = NULL;
285
286 if (ring->ring_obj == NULL) {
287 mutex_unlock(&rdev->ring_lock);
288 return 0;
289 }
290
291 /* it doesn't make sense to save anything if all fences are signaled */
292 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
293 mutex_unlock(&rdev->ring_lock);
294 return 0;
295 }
296
297 /* calculate the number of dw on the ring */
298 if (ring->rptr_save_reg)
299 ptr = RREG32(ring->rptr_save_reg);
300 else if (rdev->wb.enabled)
301 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
302 else {
303 /* no way to read back the next rptr */
304 mutex_unlock(&rdev->ring_lock);
305 return 0;
306 }
307
308 size = ring->wptr + (ring->ring_size / 4);
309 size -= ptr;
310 size &= ring->ptr_mask;
311 if (size == 0) {
312 mutex_unlock(&rdev->ring_lock);
313 return 0;
314 }
315
316 /* and then save the content of the ring */
317 *data = drm_malloc_ab(size, sizeof(uint32_t));
318 if (!*data) {
319 mutex_unlock(&rdev->ring_lock);
320 return 0;
321 }
322 for (i = 0; i < size; ++i) {
323 (*data)[i] = ring->ring[ptr++];
324 ptr &= ring->ptr_mask;
325 }
326
327 mutex_unlock(&rdev->ring_lock);
328 return size;
329}
330
331/**
332 * radeon_ring_restore - append saved commands to the ring again
333 *
334 * @rdev: radeon_device pointer
335 * @ring: ring to append commands to
336 * @size: number of dwords we want to write
337 * @data: saved commands
338 *
339 * Allocates space on the ring and restore the previously saved commands.
340 */
341int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
342 unsigned size, uint32_t *data)
343{
344 int i, r;
345
346 if (!size || !data)
347 return 0;
348
349 /* restore the saved ring content */
350 r = radeon_ring_lock(rdev, ring, size);
351 if (r)
352 return r;
353
354 for (i = 0; i < size; ++i) {
355 radeon_ring_write(ring, data[i]);
356 }
357
358 radeon_ring_unlock_commit(rdev, ring, false);
359 drm_free_large(data);
360 return 0;
361}
362
363/**
364 * radeon_ring_init - init driver ring struct.
365 *
366 * @rdev: radeon_device pointer
367 * @ring: radeon_ring structure holding ring information
368 * @ring_size: size of the ring
369 * @rptr_offs: offset of the rptr writeback location in the WB buffer
370 * @nop: nop packet for this ring
371 *
372 * Initialize the driver information for the selected ring (all asics).
373 * Returns 0 on success, error on failure.
374 */
375int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
376 unsigned rptr_offs, u32 nop)
377{
378 int r;
379
380 ring->ring_size = ring_size;
381 ring->rptr_offs = rptr_offs;
382 ring->nop = nop;
383 /* Allocate ring buffer */
384 if (ring->ring_obj == NULL) {
385 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
386 RADEON_GEM_DOMAIN_GTT, 0, NULL,
387 NULL, &ring->ring_obj);
388 if (r) {
389 dev_err(rdev->dev, "(%d) ring create failed\n", r);
390 return r;
391 }
392 r = radeon_bo_reserve(ring->ring_obj, false);
393 if (unlikely(r != 0))
394 return r;
395 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
396 &ring->gpu_addr);
397 if (r) {
398 radeon_bo_unreserve(ring->ring_obj);
399 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
400 return r;
401 }
402 r = radeon_bo_kmap(ring->ring_obj,
403 (void **)&ring->ring);
404 radeon_bo_unreserve(ring->ring_obj);
405 if (r) {
406 dev_err(rdev->dev, "(%d) ring map failed\n", r);
407 return r;
408 }
409 }
410 ring->ptr_mask = (ring->ring_size / 4) - 1;
411 ring->ring_free_dw = ring->ring_size / 4;
412 if (rdev->wb.enabled) {
413 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
414 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
415 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
416 }
417 if (radeon_debugfs_ring_init(rdev, ring)) {
418 DRM_ERROR("Failed to register debugfs file for rings !\n");
419 }
420 radeon_ring_lockup_update(rdev, ring);
421 return 0;
422}
423
424/**
425 * radeon_ring_fini - tear down the driver ring struct.
426 *
427 * @rdev: radeon_device pointer
428 * @ring: radeon_ring structure holding ring information
429 *
430 * Tear down the driver information for the selected ring (all asics).
431 */
432void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
433{
434 int r;
435 struct radeon_bo *ring_obj;
436
437 mutex_lock(&rdev->ring_lock);
438 ring_obj = ring->ring_obj;
439 ring->ready = false;
440 ring->ring = NULL;
441 ring->ring_obj = NULL;
442 mutex_unlock(&rdev->ring_lock);
443
444 if (ring_obj) {
445 r = radeon_bo_reserve(ring_obj, false);
446 if (likely(r == 0)) {
447 radeon_bo_kunmap(ring_obj);
448 radeon_bo_unpin(ring_obj);
449 radeon_bo_unreserve(ring_obj);
450 }
451 radeon_bo_unref(&ring_obj);
452 }
453}
454
455/*
456 * Debugfs info
457 */
458#if defined(CONFIG_DEBUG_FS)
459
460static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
461{
462 struct drm_info_node *node = (struct drm_info_node *) m->private;
463 struct drm_device *dev = node->minor->dev;
464 struct radeon_device *rdev = dev->dev_private;
465 int ridx = *(int*)node->info_ent->data;
466 struct radeon_ring *ring = &rdev->ring[ridx];
467
468 uint32_t rptr, wptr, rptr_next;
469 unsigned count, i, j;
470
471 radeon_ring_free_size(rdev, ring);
472 count = (ring->ring_size / 4) - ring->ring_free_dw;
473
474 wptr = radeon_ring_get_wptr(rdev, ring);
475 seq_printf(m, "wptr: 0x%08x [%5d]\n",
476 wptr, wptr);
477
478 rptr = radeon_ring_get_rptr(rdev, ring);
479 seq_printf(m, "rptr: 0x%08x [%5d]\n",
480 rptr, rptr);
481
482 if (ring->rptr_save_reg) {
483 rptr_next = RREG32(ring->rptr_save_reg);
484 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
485 ring->rptr_save_reg, rptr_next, rptr_next);
486 } else
487 rptr_next = ~0;
488
489 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
490 ring->wptr, ring->wptr);
491 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
492 ring->last_semaphore_signal_addr);
493 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
494 ring->last_semaphore_wait_addr);
495 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
496 seq_printf(m, "%u dwords in ring\n", count);
497
498 if (!ring->ring)
499 return 0;
500
501 /* print 8 dw before current rptr as often it's the last executed
502 * packet that is the root issue
503 */
504 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
505 for (j = 0; j <= (count + 32); j++) {
506 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
507 if (rptr == i)
508 seq_puts(m, " *");
509 if (rptr_next == i)
510 seq_puts(m, " #");
511 seq_puts(m, "\n");
512 i = (i + 1) & ring->ptr_mask;
513 }
514 return 0;
515}
516
517static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
518static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
519static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
520static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
521static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
522static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
523static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
524static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
525
526static struct drm_info_list radeon_debugfs_ring_info_list[] = {
527 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
528 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
529 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
530 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
531 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
532 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
533 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
534 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
535};
536
537#endif
538
539static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
540{
541#if defined(CONFIG_DEBUG_FS)
542 unsigned i;
543 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
544 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
545 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
546 unsigned r;
547
548 if (&rdev->ring[ridx] != ring)
549 continue;
550
551 r = radeon_debugfs_add_files(rdev, info, 1);
552 if (r)
553 return r;
554 }
555#endif
556 return 0;
557}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <drm/drmP.h>
32#include <drm/radeon_drm.h>
33#include "radeon_reg.h"
34#include "radeon.h"
35#include "atom.h"
36
37/*
38 * IB
39 * IBs (Indirect Buffers) and areas of GPU accessible memory where
40 * commands are stored. You can put a pointer to the IB in the
41 * command ring and the hw will fetch the commands from the IB
42 * and execute them. Generally userspace acceleration drivers
43 * produce command buffers which are send to the kernel and
44 * put in IBs for execution by the requested ring.
45 */
46static int radeon_debugfs_sa_init(struct radeon_device *rdev);
47
48/**
49 * radeon_ib_get - request an IB (Indirect Buffer)
50 *
51 * @rdev: radeon_device pointer
52 * @ring: ring index the IB is associated with
53 * @ib: IB object returned
54 * @size: requested IB size
55 *
56 * Request an IB (all asics). IBs are allocated using the
57 * suballocator.
58 * Returns 0 on success, error on failure.
59 */
60int radeon_ib_get(struct radeon_device *rdev, int ring,
61 struct radeon_ib *ib, struct radeon_vm *vm,
62 unsigned size)
63{
64 int r;
65
66 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
67 if (r) {
68 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
69 return r;
70 }
71
72 r = radeon_semaphore_create(rdev, &ib->semaphore);
73 if (r) {
74 return r;
75 }
76
77 ib->ring = ring;
78 ib->fence = NULL;
79 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
80 ib->vm = vm;
81 if (vm) {
82 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
83 * space and soffset is the offset inside the pool bo
84 */
85 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
86 } else {
87 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
88 }
89 ib->is_const_ib = false;
90
91 return 0;
92}
93
94/**
95 * radeon_ib_free - free an IB (Indirect Buffer)
96 *
97 * @rdev: radeon_device pointer
98 * @ib: IB object to free
99 *
100 * Free an IB (all asics).
101 */
102void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
103{
104 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
105 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
106 radeon_fence_unref(&ib->fence);
107}
108
109/**
110 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
111 *
112 * @rdev: radeon_device pointer
113 * @ib: IB object to schedule
114 * @const_ib: Const IB to schedule (SI only)
115 *
116 * Schedule an IB on the associated ring (all asics).
117 * Returns 0 on success, error on failure.
118 *
119 * On SI, there are two parallel engines fed from the primary ring,
120 * the CE (Constant Engine) and the DE (Drawing Engine). Since
121 * resource descriptors have moved to memory, the CE allows you to
122 * prime the caches while the DE is updating register state so that
123 * the resource descriptors will be already in cache when the draw is
124 * processed. To accomplish this, the userspace driver submits two
125 * IBs, one for the CE and one for the DE. If there is a CE IB (called
126 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
127 * to SI there was just a DE IB.
128 */
129int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
130 struct radeon_ib *const_ib)
131{
132 struct radeon_ring *ring = &rdev->ring[ib->ring];
133 int r = 0;
134
135 if (!ib->length_dw || !ring->ready) {
136 /* TODO: Nothings in the ib we should report. */
137 dev_err(rdev->dev, "couldn't schedule ib\n");
138 return -EINVAL;
139 }
140
141 /* 64 dwords should be enough for fence too */
142 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
143 if (r) {
144 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
145 return r;
146 }
147
148 /* grab a vm id if necessary */
149 if (ib->vm) {
150 struct radeon_fence *vm_id_fence;
151 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
152 radeon_semaphore_sync_to(ib->semaphore, vm_id_fence);
153 }
154
155 /* sync with other rings */
156 r = radeon_semaphore_sync_rings(rdev, ib->semaphore, ib->ring);
157 if (r) {
158 dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
159 radeon_ring_unlock_undo(rdev, ring);
160 return r;
161 }
162
163 if (ib->vm)
164 radeon_vm_flush(rdev, ib->vm, ib->ring);
165
166 if (const_ib) {
167 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
168 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
169 }
170 radeon_ring_ib_execute(rdev, ib->ring, ib);
171 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
172 if (r) {
173 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
174 radeon_ring_unlock_undo(rdev, ring);
175 return r;
176 }
177 if (const_ib) {
178 const_ib->fence = radeon_fence_ref(ib->fence);
179 }
180
181 if (ib->vm)
182 radeon_vm_fence(rdev, ib->vm, ib->fence);
183
184 radeon_ring_unlock_commit(rdev, ring);
185 return 0;
186}
187
188/**
189 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
190 *
191 * @rdev: radeon_device pointer
192 *
193 * Initialize the suballocator to manage a pool of memory
194 * for use as IBs (all asics).
195 * Returns 0 on success, error on failure.
196 */
197int radeon_ib_pool_init(struct radeon_device *rdev)
198{
199 int r;
200
201 if (rdev->ib_pool_ready) {
202 return 0;
203 }
204 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
205 RADEON_IB_POOL_SIZE*64*1024,
206 RADEON_GPU_PAGE_SIZE,
207 RADEON_GEM_DOMAIN_GTT);
208 if (r) {
209 return r;
210 }
211
212 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
213 if (r) {
214 return r;
215 }
216
217 rdev->ib_pool_ready = true;
218 if (radeon_debugfs_sa_init(rdev)) {
219 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
220 }
221 return 0;
222}
223
224/**
225 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
226 *
227 * @rdev: radeon_device pointer
228 *
229 * Tear down the suballocator managing the pool of memory
230 * for use as IBs (all asics).
231 */
232void radeon_ib_pool_fini(struct radeon_device *rdev)
233{
234 if (rdev->ib_pool_ready) {
235 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
236 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
237 rdev->ib_pool_ready = false;
238 }
239}
240
241/**
242 * radeon_ib_ring_tests - test IBs on the rings
243 *
244 * @rdev: radeon_device pointer
245 *
246 * Test an IB (Indirect Buffer) on each ring.
247 * If the test fails, disable the ring.
248 * Returns 0 on success, error if the primary GFX ring
249 * IB test fails.
250 */
251int radeon_ib_ring_tests(struct radeon_device *rdev)
252{
253 unsigned i;
254 int r;
255
256 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
257 struct radeon_ring *ring = &rdev->ring[i];
258
259 if (!ring->ready)
260 continue;
261
262 r = radeon_ib_test(rdev, i, ring);
263 if (r) {
264 ring->ready = false;
265 rdev->needs_reset = false;
266
267 if (i == RADEON_RING_TYPE_GFX_INDEX) {
268 /* oh, oh, that's really bad */
269 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
270 rdev->accel_working = false;
271 return r;
272
273 } else {
274 /* still not good, but we can live with it */
275 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
276 }
277 }
278 }
279 return 0;
280}
281
282/*
283 * Rings
284 * Most engines on the GPU are fed via ring buffers. Ring
285 * buffers are areas of GPU accessible memory that the host
286 * writes commands into and the GPU reads commands out of.
287 * There is a rptr (read pointer) that determines where the
288 * GPU is currently reading, and a wptr (write pointer)
289 * which determines where the host has written. When the
290 * pointers are equal, the ring is idle. When the host
291 * writes commands to the ring buffer, it increments the
292 * wptr. The GPU then starts fetching commands and executes
293 * them until the pointers are equal again.
294 */
295static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
296
297/**
298 * radeon_ring_write - write a value to the ring
299 *
300 * @ring: radeon_ring structure holding ring information
301 * @v: dword (dw) value to write
302 *
303 * Write a value to the requested ring buffer (all asics).
304 */
305void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
306{
307#if DRM_DEBUG_CODE
308 if (ring->count_dw <= 0) {
309 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
310 }
311#endif
312 ring->ring[ring->wptr++] = v;
313 ring->wptr &= ring->ptr_mask;
314 ring->count_dw--;
315 ring->ring_free_dw--;
316}
317
318/**
319 * radeon_ring_supports_scratch_reg - check if the ring supports
320 * writing to scratch registers
321 *
322 * @rdev: radeon_device pointer
323 * @ring: radeon_ring structure holding ring information
324 *
325 * Check if a specific ring supports writing to scratch registers (all asics).
326 * Returns true if the ring supports writing to scratch regs, false if not.
327 */
328bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
329 struct radeon_ring *ring)
330{
331 switch (ring->idx) {
332 case RADEON_RING_TYPE_GFX_INDEX:
333 case CAYMAN_RING_TYPE_CP1_INDEX:
334 case CAYMAN_RING_TYPE_CP2_INDEX:
335 return true;
336 default:
337 return false;
338 }
339}
340
341/**
342 * radeon_ring_free_size - update the free size
343 *
344 * @rdev: radeon_device pointer
345 * @ring: radeon_ring structure holding ring information
346 *
347 * Update the free dw slots in the ring buffer (all asics).
348 */
349void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
350{
351 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
352
353 /* This works because ring_size is a power of 2 */
354 ring->ring_free_dw = rptr + (ring->ring_size / 4);
355 ring->ring_free_dw -= ring->wptr;
356 ring->ring_free_dw &= ring->ptr_mask;
357 if (!ring->ring_free_dw) {
358 /* this is an empty ring */
359 ring->ring_free_dw = ring->ring_size / 4;
360 /* update lockup info to avoid false positive */
361 radeon_ring_lockup_update(rdev, ring);
362 }
363}
364
365/**
366 * radeon_ring_alloc - allocate space on the ring buffer
367 *
368 * @rdev: radeon_device pointer
369 * @ring: radeon_ring structure holding ring information
370 * @ndw: number of dwords to allocate in the ring buffer
371 *
372 * Allocate @ndw dwords in the ring buffer (all asics).
373 * Returns 0 on success, error on failure.
374 */
375int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
376{
377 int r;
378
379 /* make sure we aren't trying to allocate more space than there is on the ring */
380 if (ndw > (ring->ring_size / 4))
381 return -ENOMEM;
382 /* Align requested size with padding so unlock_commit can
383 * pad safely */
384 radeon_ring_free_size(rdev, ring);
385 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
386 while (ndw > (ring->ring_free_dw - 1)) {
387 radeon_ring_free_size(rdev, ring);
388 if (ndw < ring->ring_free_dw) {
389 break;
390 }
391 r = radeon_fence_wait_next(rdev, ring->idx);
392 if (r)
393 return r;
394 }
395 ring->count_dw = ndw;
396 ring->wptr_old = ring->wptr;
397 return 0;
398}
399
400/**
401 * radeon_ring_lock - lock the ring and allocate space on it
402 *
403 * @rdev: radeon_device pointer
404 * @ring: radeon_ring structure holding ring information
405 * @ndw: number of dwords to allocate in the ring buffer
406 *
407 * Lock the ring and allocate @ndw dwords in the ring buffer
408 * (all asics).
409 * Returns 0 on success, error on failure.
410 */
411int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
412{
413 int r;
414
415 mutex_lock(&rdev->ring_lock);
416 r = radeon_ring_alloc(rdev, ring, ndw);
417 if (r) {
418 mutex_unlock(&rdev->ring_lock);
419 return r;
420 }
421 return 0;
422}
423
424/**
425 * radeon_ring_commit - tell the GPU to execute the new
426 * commands on the ring buffer
427 *
428 * @rdev: radeon_device pointer
429 * @ring: radeon_ring structure holding ring information
430 *
431 * Update the wptr (write pointer) to tell the GPU to
432 * execute new commands on the ring buffer (all asics).
433 */
434void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
435{
436 /* We pad to match fetch size */
437 while (ring->wptr & ring->align_mask) {
438 radeon_ring_write(ring, ring->nop);
439 }
440 mb();
441 radeon_ring_set_wptr(rdev, ring);
442}
443
444/**
445 * radeon_ring_unlock_commit - tell the GPU to execute the new
446 * commands on the ring buffer and unlock it
447 *
448 * @rdev: radeon_device pointer
449 * @ring: radeon_ring structure holding ring information
450 *
451 * Call radeon_ring_commit() then unlock the ring (all asics).
452 */
453void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
454{
455 radeon_ring_commit(rdev, ring);
456 mutex_unlock(&rdev->ring_lock);
457}
458
459/**
460 * radeon_ring_undo - reset the wptr
461 *
462 * @ring: radeon_ring structure holding ring information
463 *
464 * Reset the driver's copy of the wptr (all asics).
465 */
466void radeon_ring_undo(struct radeon_ring *ring)
467{
468 ring->wptr = ring->wptr_old;
469}
470
471/**
472 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
473 *
474 * @ring: radeon_ring structure holding ring information
475 *
476 * Call radeon_ring_undo() then unlock the ring (all asics).
477 */
478void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
479{
480 radeon_ring_undo(ring);
481 mutex_unlock(&rdev->ring_lock);
482}
483
484/**
485 * radeon_ring_lockup_update - update lockup variables
486 *
487 * @ring: radeon_ring structure holding ring information
488 *
489 * Update the last rptr value and timestamp (all asics).
490 */
491void radeon_ring_lockup_update(struct radeon_device *rdev,
492 struct radeon_ring *ring)
493{
494 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));
495 atomic64_set(&ring->last_activity, jiffies_64);
496}
497
498/**
499 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
500 * @rdev: radeon device structure
501 * @ring: radeon_ring structure holding ring information
502 *
503 */
504bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
505{
506 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);
507 uint64_t last = atomic64_read(&ring->last_activity);
508 uint64_t elapsed;
509
510 if (rptr != atomic_read(&ring->last_rptr)) {
511 /* ring is still working, no lockup */
512 radeon_ring_lockup_update(rdev, ring);
513 return false;
514 }
515
516 elapsed = jiffies_to_msecs(jiffies_64 - last);
517 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
518 dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",
519 ring->idx, elapsed);
520 return true;
521 }
522 /* give a chance to the GPU ... */
523 return false;
524}
525
526/**
527 * radeon_ring_backup - Back up the content of a ring
528 *
529 * @rdev: radeon_device pointer
530 * @ring: the ring we want to back up
531 *
532 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
533 */
534unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
535 uint32_t **data)
536{
537 unsigned size, ptr, i;
538
539 /* just in case lock the ring */
540 mutex_lock(&rdev->ring_lock);
541 *data = NULL;
542
543 if (ring->ring_obj == NULL) {
544 mutex_unlock(&rdev->ring_lock);
545 return 0;
546 }
547
548 /* it doesn't make sense to save anything if all fences are signaled */
549 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
550 mutex_unlock(&rdev->ring_lock);
551 return 0;
552 }
553
554 /* calculate the number of dw on the ring */
555 if (ring->rptr_save_reg)
556 ptr = RREG32(ring->rptr_save_reg);
557 else if (rdev->wb.enabled)
558 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
559 else {
560 /* no way to read back the next rptr */
561 mutex_unlock(&rdev->ring_lock);
562 return 0;
563 }
564
565 size = ring->wptr + (ring->ring_size / 4);
566 size -= ptr;
567 size &= ring->ptr_mask;
568 if (size == 0) {
569 mutex_unlock(&rdev->ring_lock);
570 return 0;
571 }
572
573 /* and then save the content of the ring */
574 *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
575 if (!*data) {
576 mutex_unlock(&rdev->ring_lock);
577 return 0;
578 }
579 for (i = 0; i < size; ++i) {
580 (*data)[i] = ring->ring[ptr++];
581 ptr &= ring->ptr_mask;
582 }
583
584 mutex_unlock(&rdev->ring_lock);
585 return size;
586}
587
588/**
589 * radeon_ring_restore - append saved commands to the ring again
590 *
591 * @rdev: radeon_device pointer
592 * @ring: ring to append commands to
593 * @size: number of dwords we want to write
594 * @data: saved commands
595 *
596 * Allocates space on the ring and restore the previously saved commands.
597 */
598int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
599 unsigned size, uint32_t *data)
600{
601 int i, r;
602
603 if (!size || !data)
604 return 0;
605
606 /* restore the saved ring content */
607 r = radeon_ring_lock(rdev, ring, size);
608 if (r)
609 return r;
610
611 for (i = 0; i < size; ++i) {
612 radeon_ring_write(ring, data[i]);
613 }
614
615 radeon_ring_unlock_commit(rdev, ring);
616 kfree(data);
617 return 0;
618}
619
620/**
621 * radeon_ring_init - init driver ring struct.
622 *
623 * @rdev: radeon_device pointer
624 * @ring: radeon_ring structure holding ring information
625 * @ring_size: size of the ring
626 * @rptr_offs: offset of the rptr writeback location in the WB buffer
627 * @nop: nop packet for this ring
628 *
629 * Initialize the driver information for the selected ring (all asics).
630 * Returns 0 on success, error on failure.
631 */
632int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
633 unsigned rptr_offs, u32 nop)
634{
635 int r;
636
637 ring->ring_size = ring_size;
638 ring->rptr_offs = rptr_offs;
639 ring->nop = nop;
640 /* Allocate ring buffer */
641 if (ring->ring_obj == NULL) {
642 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
643 RADEON_GEM_DOMAIN_GTT,
644 NULL, &ring->ring_obj);
645 if (r) {
646 dev_err(rdev->dev, "(%d) ring create failed\n", r);
647 return r;
648 }
649 r = radeon_bo_reserve(ring->ring_obj, false);
650 if (unlikely(r != 0))
651 return r;
652 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
653 &ring->gpu_addr);
654 if (r) {
655 radeon_bo_unreserve(ring->ring_obj);
656 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
657 return r;
658 }
659 r = radeon_bo_kmap(ring->ring_obj,
660 (void **)&ring->ring);
661 radeon_bo_unreserve(ring->ring_obj);
662 if (r) {
663 dev_err(rdev->dev, "(%d) ring map failed\n", r);
664 return r;
665 }
666 }
667 ring->ptr_mask = (ring->ring_size / 4) - 1;
668 ring->ring_free_dw = ring->ring_size / 4;
669 if (rdev->wb.enabled) {
670 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
671 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
672 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
673 }
674 if (radeon_debugfs_ring_init(rdev, ring)) {
675 DRM_ERROR("Failed to register debugfs file for rings !\n");
676 }
677 radeon_ring_lockup_update(rdev, ring);
678 return 0;
679}
680
681/**
682 * radeon_ring_fini - tear down the driver ring struct.
683 *
684 * @rdev: radeon_device pointer
685 * @ring: radeon_ring structure holding ring information
686 *
687 * Tear down the driver information for the selected ring (all asics).
688 */
689void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
690{
691 int r;
692 struct radeon_bo *ring_obj;
693
694 mutex_lock(&rdev->ring_lock);
695 ring_obj = ring->ring_obj;
696 ring->ready = false;
697 ring->ring = NULL;
698 ring->ring_obj = NULL;
699 mutex_unlock(&rdev->ring_lock);
700
701 if (ring_obj) {
702 r = radeon_bo_reserve(ring_obj, false);
703 if (likely(r == 0)) {
704 radeon_bo_kunmap(ring_obj);
705 radeon_bo_unpin(ring_obj);
706 radeon_bo_unreserve(ring_obj);
707 }
708 radeon_bo_unref(&ring_obj);
709 }
710}
711
712/*
713 * Debugfs info
714 */
715#if defined(CONFIG_DEBUG_FS)
716
717static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
718{
719 struct drm_info_node *node = (struct drm_info_node *) m->private;
720 struct drm_device *dev = node->minor->dev;
721 struct radeon_device *rdev = dev->dev_private;
722 int ridx = *(int*)node->info_ent->data;
723 struct radeon_ring *ring = &rdev->ring[ridx];
724
725 uint32_t rptr, wptr, rptr_next;
726 unsigned count, i, j;
727
728 radeon_ring_free_size(rdev, ring);
729 count = (ring->ring_size / 4) - ring->ring_free_dw;
730
731 wptr = radeon_ring_get_wptr(rdev, ring);
732 seq_printf(m, "wptr: 0x%08x [%5d]\n",
733 wptr, wptr);
734
735 rptr = radeon_ring_get_rptr(rdev, ring);
736 seq_printf(m, "rptr: 0x%08x [%5d]\n",
737 rptr, rptr);
738
739 if (ring->rptr_save_reg) {
740 rptr_next = RREG32(ring->rptr_save_reg);
741 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",
742 ring->rptr_save_reg, rptr_next, rptr_next);
743 } else
744 rptr_next = ~0;
745
746 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
747 ring->wptr, ring->wptr);
748 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",
749 ring->last_semaphore_signal_addr);
750 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",
751 ring->last_semaphore_wait_addr);
752 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
753 seq_printf(m, "%u dwords in ring\n", count);
754
755 if (!ring->ready)
756 return 0;
757
758 /* print 8 dw before current rptr as often it's the last executed
759 * packet that is the root issue
760 */
761 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
762 for (j = 0; j <= (count + 32); j++) {
763 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
764 if (rptr == i)
765 seq_puts(m, " *");
766 if (rptr_next == i)
767 seq_puts(m, " #");
768 seq_puts(m, "\n");
769 i = (i + 1) & ring->ptr_mask;
770 }
771 return 0;
772}
773
774static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
775static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
776static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
777static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
778static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
779static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
780static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
781static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
782
783static struct drm_info_list radeon_debugfs_ring_info_list[] = {
784 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
785 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
786 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
787 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
788 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
789 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
790 {"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
791 {"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
792};
793
794static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
795{
796 struct drm_info_node *node = (struct drm_info_node *) m->private;
797 struct drm_device *dev = node->minor->dev;
798 struct radeon_device *rdev = dev->dev_private;
799
800 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
801
802 return 0;
803
804}
805
806static struct drm_info_list radeon_debugfs_sa_list[] = {
807 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
808};
809
810#endif
811
812static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
813{
814#if defined(CONFIG_DEBUG_FS)
815 unsigned i;
816 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
817 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
818 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
819 unsigned r;
820
821 if (&rdev->ring[ridx] != ring)
822 continue;
823
824 r = radeon_debugfs_add_files(rdev, info, 1);
825 if (r)
826 return r;
827 }
828#endif
829 return 0;
830}
831
832static int radeon_debugfs_sa_init(struct radeon_device *rdev)
833{
834#if defined(CONFIG_DEBUG_FS)
835 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
836#else
837 return 0;
838#endif
839}