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1/*
2 * Copyright 2009 Ben Skeggs
3 * Copyright 2008 Stuart Bennett
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "nouveau_drm.h"
26#include "nouveau_dma.h"
27#include "nouveau_fbcon.h"
28
29int
30nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
31{
32 struct nouveau_fbdev *nfbdev = info->par;
33 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
34 struct nouveau_channel *chan = drm->channel;
35 int ret;
36
37 ret = RING_SPACE(chan, 4);
38 if (ret)
39 return ret;
40
41 BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
42 OUT_RING(chan, (region->sy << 16) | region->sx);
43 OUT_RING(chan, (region->dy << 16) | region->dx);
44 OUT_RING(chan, (region->height << 16) | region->width);
45 FIRE_RING(chan);
46 return 0;
47}
48
49int
50nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
51{
52 struct nouveau_fbdev *nfbdev = info->par;
53 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
54 struct nouveau_channel *chan = drm->channel;
55 int ret;
56
57 ret = RING_SPACE(chan, 7);
58 if (ret)
59 return ret;
60
61 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
62 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
63 BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
64 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
65 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
66 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
67 else
68 OUT_RING(chan, rect->color);
69 BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
70 OUT_RING(chan, (rect->dx << 16) | rect->dy);
71 OUT_RING(chan, (rect->width << 16) | rect->height);
72 FIRE_RING(chan);
73 return 0;
74}
75
76int
77nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
78{
79 struct nouveau_fbdev *nfbdev = info->par;
80 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
81 struct nouveau_channel *chan = drm->channel;
82 uint32_t fg;
83 uint32_t bg;
84 uint32_t dsize;
85 uint32_t width;
86 uint32_t *data = (uint32_t *)image->data;
87 int ret;
88
89 if (image->depth != 1)
90 return -ENODEV;
91
92 ret = RING_SPACE(chan, 8);
93 if (ret)
94 return ret;
95
96 width = ALIGN(image->width, 8);
97 dsize = ALIGN(width * image->height, 32) >> 5;
98
99 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
100 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
101 fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
102 bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
103 } else {
104 fg = image->fg_color;
105 bg = image->bg_color;
106 }
107
108 BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
109 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
110 OUT_RING(chan, ((image->dy + image->height) << 16) |
111 ((image->dx + image->width) & 0xffff));
112 OUT_RING(chan, bg);
113 OUT_RING(chan, fg);
114 OUT_RING(chan, (image->height << 16) | width);
115 OUT_RING(chan, (image->height << 16) | image->width);
116 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
117
118 while (dsize) {
119 int iter_len = dsize > 128 ? 128 : dsize;
120
121 ret = RING_SPACE(chan, iter_len + 1);
122 if (ret)
123 return ret;
124
125 BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
126 OUT_RINGp(chan, data, iter_len);
127 data += iter_len;
128 dsize -= iter_len;
129 }
130
131 FIRE_RING(chan);
132 return 0;
133}
134
135int
136nv04_fbcon_accel_init(struct fb_info *info)
137{
138 struct nouveau_fbdev *nfbdev = info->par;
139 struct drm_device *dev = nfbdev->dev;
140 struct nouveau_drm *drm = nouveau_drm(dev);
141 struct nouveau_channel *chan = drm->channel;
142 struct nvif_device *device = &drm->device;
143 int surface_fmt, pattern_fmt, rect_fmt;
144 int ret;
145
146 switch (info->var.bits_per_pixel) {
147 case 8:
148 surface_fmt = 1;
149 pattern_fmt = 3;
150 rect_fmt = 3;
151 break;
152 case 16:
153 surface_fmt = 4;
154 pattern_fmt = 1;
155 rect_fmt = 1;
156 break;
157 case 32:
158 switch (info->var.transp.length) {
159 case 0: /* depth 24 */
160 case 8: /* depth 32 */
161 break;
162 default:
163 return -EINVAL;
164 }
165
166 surface_fmt = 6;
167 pattern_fmt = 3;
168 rect_fmt = 3;
169 break;
170 default:
171 return -EINVAL;
172 }
173
174 ret = nvif_object_init(&chan->user, 0x0062,
175 device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
176 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
177 if (ret)
178 return ret;
179
180 ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0,
181 &nfbdev->clip);
182 if (ret)
183 return ret;
184
185 ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0,
186 &nfbdev->rop);
187 if (ret)
188 return ret;
189
190 ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0,
191 &nfbdev->patt);
192 if (ret)
193 return ret;
194
195 ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0,
196 &nfbdev->gdi);
197 if (ret)
198 return ret;
199
200 ret = nvif_object_init(&chan->user, 0x005f,
201 device->info.chipset >= 0x11 ? 0x009f : 0x005f,
202 NULL, 0, &nfbdev->blit);
203 if (ret)
204 return ret;
205
206 if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
207 nouveau_fbcon_gpu_lockup(info);
208 return 0;
209 }
210
211 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
212 OUT_RING(chan, nfbdev->surf2d.handle);
213 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
214 OUT_RING(chan, chan->vram.handle);
215 OUT_RING(chan, chan->vram.handle);
216 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
217 OUT_RING(chan, surface_fmt);
218 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
219 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
220 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
221
222 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
223 OUT_RING(chan, nfbdev->rop.handle);
224 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
225 OUT_RING(chan, 0x55);
226
227 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
228 OUT_RING(chan, nfbdev->patt.handle);
229 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
230 OUT_RING(chan, pattern_fmt);
231#ifdef __BIG_ENDIAN
232 OUT_RING(chan, 2);
233#else
234 OUT_RING(chan, 1);
235#endif
236 OUT_RING(chan, 0);
237 OUT_RING(chan, 1);
238 OUT_RING(chan, ~0);
239 OUT_RING(chan, ~0);
240 OUT_RING(chan, ~0);
241 OUT_RING(chan, ~0);
242
243 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
244 OUT_RING(chan, nfbdev->clip.handle);
245 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
246 OUT_RING(chan, 0);
247 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
248
249 BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
250 OUT_RING(chan, nfbdev->blit.handle);
251 BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
252 OUT_RING(chan, nfbdev->surf2d.handle);
253 BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
254 OUT_RING(chan, 3);
255 if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
256 BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
257 OUT_RING(chan, 0);
258 OUT_RING(chan, 1);
259 OUT_RING(chan, 2);
260 }
261
262 BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
263 OUT_RING(chan, nfbdev->gdi.handle);
264 BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
265 OUT_RING(chan, nfbdev->surf2d.handle);
266 BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
267 OUT_RING(chan, nfbdev->patt.handle);
268 OUT_RING(chan, nfbdev->rop.handle);
269 BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
270 OUT_RING(chan, 1);
271 BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
272 OUT_RING(chan, rect_fmt);
273 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
274 OUT_RING(chan, 3);
275
276 FIRE_RING(chan);
277
278 return 0;
279}
280
1/*
2 * Copyright 2009 Ben Skeggs
3 * Copyright 2008 Stuart Bennett
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <core/object.h>
26
27#include "nouveau_drm.h"
28#include "nouveau_dma.h"
29#include "nouveau_fbcon.h"
30
31int
32nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
33{
34 struct nouveau_fbdev *nfbdev = info->par;
35 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
36 struct nouveau_channel *chan = drm->channel;
37 int ret;
38
39 ret = RING_SPACE(chan, 4);
40 if (ret)
41 return ret;
42
43 BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
44 OUT_RING(chan, (region->sy << 16) | region->sx);
45 OUT_RING(chan, (region->dy << 16) | region->dx);
46 OUT_RING(chan, (region->height << 16) | region->width);
47 FIRE_RING(chan);
48 return 0;
49}
50
51int
52nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
53{
54 struct nouveau_fbdev *nfbdev = info->par;
55 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
56 struct nouveau_channel *chan = drm->channel;
57 int ret;
58
59 ret = RING_SPACE(chan, 7);
60 if (ret)
61 return ret;
62
63 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
64 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
65 BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
66 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
67 info->fix.visual == FB_VISUAL_DIRECTCOLOR)
68 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
69 else
70 OUT_RING(chan, rect->color);
71 BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
72 OUT_RING(chan, (rect->dx << 16) | rect->dy);
73 OUT_RING(chan, (rect->width << 16) | rect->height);
74 FIRE_RING(chan);
75 return 0;
76}
77
78int
79nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
80{
81 struct nouveau_fbdev *nfbdev = info->par;
82 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
83 struct nouveau_channel *chan = drm->channel;
84 uint32_t fg;
85 uint32_t bg;
86 uint32_t dsize;
87 uint32_t width;
88 uint32_t *data = (uint32_t *)image->data;
89 int ret;
90
91 if (image->depth != 1)
92 return -ENODEV;
93
94 ret = RING_SPACE(chan, 8);
95 if (ret)
96 return ret;
97
98 width = ALIGN(image->width, 8);
99 dsize = ALIGN(width * image->height, 32) >> 5;
100
101 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
102 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
103 fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
104 bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
105 } else {
106 fg = image->fg_color;
107 bg = image->bg_color;
108 }
109
110 BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
111 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
112 OUT_RING(chan, ((image->dy + image->height) << 16) |
113 ((image->dx + image->width) & 0xffff));
114 OUT_RING(chan, bg);
115 OUT_RING(chan, fg);
116 OUT_RING(chan, (image->height << 16) | width);
117 OUT_RING(chan, (image->height << 16) | image->width);
118 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
119
120 while (dsize) {
121 int iter_len = dsize > 128 ? 128 : dsize;
122
123 ret = RING_SPACE(chan, iter_len + 1);
124 if (ret)
125 return ret;
126
127 BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
128 OUT_RINGp(chan, data, iter_len);
129 data += iter_len;
130 dsize -= iter_len;
131 }
132
133 FIRE_RING(chan);
134 return 0;
135}
136
137int
138nv04_fbcon_accel_init(struct fb_info *info)
139{
140 struct nouveau_fbdev *nfbdev = info->par;
141 struct drm_device *dev = nfbdev->dev;
142 struct nouveau_drm *drm = nouveau_drm(dev);
143 struct nouveau_channel *chan = drm->channel;
144 struct nouveau_device *device = nv_device(drm->device);
145 struct nouveau_object *object;
146 int surface_fmt, pattern_fmt, rect_fmt;
147 int ret;
148
149 switch (info->var.bits_per_pixel) {
150 case 8:
151 surface_fmt = 1;
152 pattern_fmt = 3;
153 rect_fmt = 3;
154 break;
155 case 16:
156 surface_fmt = 4;
157 pattern_fmt = 1;
158 rect_fmt = 1;
159 break;
160 case 32:
161 switch (info->var.transp.length) {
162 case 0: /* depth 24 */
163 case 8: /* depth 32 */
164 break;
165 default:
166 return -EINVAL;
167 }
168
169 surface_fmt = 6;
170 pattern_fmt = 3;
171 rect_fmt = 3;
172 break;
173 default:
174 return -EINVAL;
175 }
176
177 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvCtxSurf2D,
178 device->card_type >= NV_10 ? 0x0062 : 0x0042,
179 NULL, 0, &object);
180 if (ret)
181 return ret;
182
183 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvClipRect,
184 0x0019, NULL, 0, &object);
185 if (ret)
186 return ret;
187
188 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvRop,
189 0x0043, NULL, 0, &object);
190 if (ret)
191 return ret;
192
193 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImagePatt,
194 0x0044, NULL, 0, &object);
195 if (ret)
196 return ret;
197
198 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvGdiRect,
199 0x004a, NULL, 0, &object);
200 if (ret)
201 return ret;
202
203 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImageBlit,
204 device->chipset >= 0x11 ? 0x009f : 0x005f,
205 NULL, 0, &object);
206 if (ret)
207 return ret;
208
209 if (RING_SPACE(chan, 49)) {
210 nouveau_fbcon_gpu_lockup(info);
211 return 0;
212 }
213
214 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
215 OUT_RING(chan, NvCtxSurf2D);
216 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
217 OUT_RING(chan, NvDmaFB);
218 OUT_RING(chan, NvDmaFB);
219 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
220 OUT_RING(chan, surface_fmt);
221 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
222 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
223 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
224
225 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
226 OUT_RING(chan, NvRop);
227 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
228 OUT_RING(chan, 0x55);
229
230 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
231 OUT_RING(chan, NvImagePatt);
232 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
233 OUT_RING(chan, pattern_fmt);
234#ifdef __BIG_ENDIAN
235 OUT_RING(chan, 2);
236#else
237 OUT_RING(chan, 1);
238#endif
239 OUT_RING(chan, 0);
240 OUT_RING(chan, 1);
241 OUT_RING(chan, ~0);
242 OUT_RING(chan, ~0);
243 OUT_RING(chan, ~0);
244 OUT_RING(chan, ~0);
245
246 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
247 OUT_RING(chan, NvClipRect);
248 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
249 OUT_RING(chan, 0);
250 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
251
252 BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
253 OUT_RING(chan, NvImageBlit);
254 BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
255 OUT_RING(chan, NvCtxSurf2D);
256 BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
257 OUT_RING(chan, 3);
258 if (device->chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
259 BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
260 OUT_RING(chan, 0);
261 OUT_RING(chan, 1);
262 OUT_RING(chan, 2);
263 }
264
265 BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
266 OUT_RING(chan, NvGdiRect);
267 BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
268 OUT_RING(chan, NvCtxSurf2D);
269 BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
270 OUT_RING(chan, NvImagePatt);
271 OUT_RING(chan, NvRop);
272 BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
273 OUT_RING(chan, 1);
274 BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
275 OUT_RING(chan, rect_fmt);
276 BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
277 OUT_RING(chan, 3);
278
279 FIRE_RING(chan);
280
281 return 0;
282}
283