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1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include <linux/clk.h>
19#include <linux/pm_runtime.h>
20#include <linux/of.h>
21#include <linux/spinlock.h>
22
23#include <drm/drmP.h>
24#include <drm/exynos_drm.h>
25#include "regs-fimc.h"
26#include "exynos_drm_drv.h"
27#include "exynos_drm_ipp.h"
28#include "exynos_drm_fimc.h"
29
30/*
31 * FIMC stands for Fully Interactive Mobile Camera and
32 * supports image scaler/rotator and input/output DMA operations.
33 * input DMA reads image data from the memory.
34 * output DMA writes image data to memory.
35 * FIMC supports image rotation and image effect functions.
36 *
37 * M2M operation : supports crop/scale/rotation/csc so on.
38 * Memory ----> FIMC H/W ----> Memory.
39 * Writeback operation : supports cloned screen with FIMD.
40 * FIMD ----> FIMC H/W ----> Memory.
41 * Output operation : supports direct display using local path.
42 * Memory ----> FIMC H/W ----> FIMD.
43 */
44
45/*
46 * TODO
47 * 1. check suspend/resume api if needed.
48 * 2. need to check use case platform_device_id.
49 * 3. check src/dst size with, height.
50 * 4. added check_prepare api for right register.
51 * 5. need to add supported list in prop_list.
52 * 6. check prescaler/scaler optimization.
53 */
54
55#define FIMC_MAX_DEVS 4
56#define FIMC_MAX_SRC 2
57#define FIMC_MAX_DST 32
58#define FIMC_SHFACTOR 10
59#define FIMC_BUF_STOP 1
60#define FIMC_BUF_START 2
61#define FIMC_WIDTH_ITU_709 1280
62#define FIMC_REFRESH_MAX 60
63#define FIMC_REFRESH_MIN 12
64#define FIMC_CROP_MAX 8192
65#define FIMC_CROP_MIN 32
66#define FIMC_SCALE_MAX 4224
67#define FIMC_SCALE_MIN 32
68
69#define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
70#define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
71 struct fimc_context, ippdrv);
72enum fimc_wb {
73 FIMC_WB_NONE,
74 FIMC_WB_A,
75 FIMC_WB_B,
76};
77
78enum {
79 FIMC_CLK_LCLK,
80 FIMC_CLK_GATE,
81 FIMC_CLK_WB_A,
82 FIMC_CLK_WB_B,
83 FIMC_CLK_MUX,
84 FIMC_CLK_PARENT,
85 FIMC_CLKS_MAX
86};
87
88static const char * const fimc_clock_names[] = {
89 [FIMC_CLK_LCLK] = "sclk_fimc",
90 [FIMC_CLK_GATE] = "fimc",
91 [FIMC_CLK_WB_A] = "pxl_async0",
92 [FIMC_CLK_WB_B] = "pxl_async1",
93 [FIMC_CLK_MUX] = "mux",
94 [FIMC_CLK_PARENT] = "parent",
95};
96
97#define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
98
99/*
100 * A structure of scaler.
101 *
102 * @range: narrow, wide.
103 * @bypass: unused scaler path.
104 * @up_h: horizontal scale up.
105 * @up_v: vertical scale up.
106 * @hratio: horizontal ratio.
107 * @vratio: vertical ratio.
108 */
109struct fimc_scaler {
110 bool range;
111 bool bypass;
112 bool up_h;
113 bool up_v;
114 u32 hratio;
115 u32 vratio;
116};
117
118/*
119 * A structure of scaler capability.
120 *
121 * find user manual table 43-1.
122 * @in_hori: scaler input horizontal size.
123 * @bypass: scaler bypass mode.
124 * @dst_h_wo_rot: target horizontal size without output rotation.
125 * @dst_h_rot: target horizontal size with output rotation.
126 * @rl_w_wo_rot: real width without input rotation.
127 * @rl_h_rot: real height without output rotation.
128 */
129struct fimc_capability {
130 /* scaler */
131 u32 in_hori;
132 u32 bypass;
133 /* output rotator */
134 u32 dst_h_wo_rot;
135 u32 dst_h_rot;
136 /* input rotator */
137 u32 rl_w_wo_rot;
138 u32 rl_h_rot;
139};
140
141/*
142 * A structure of fimc context.
143 *
144 * @ippdrv: prepare initialization using ippdrv.
145 * @regs_res: register resources.
146 * @regs: memory mapped io registers.
147 * @lock: locking of operations.
148 * @clocks: fimc clocks.
149 * @clk_frequency: LCLK clock frequency.
150 * @sysreg: handle to SYSREG block regmap.
151 * @sc: scaler infomations.
152 * @pol: porarity of writeback.
153 * @id: fimc id.
154 * @irq: irq number.
155 * @suspended: qos operations.
156 */
157struct fimc_context {
158 struct exynos_drm_ippdrv ippdrv;
159 struct resource *regs_res;
160 void __iomem *regs;
161 spinlock_t lock;
162 struct clk *clocks[FIMC_CLKS_MAX];
163 u32 clk_frequency;
164 struct regmap *sysreg;
165 struct fimc_scaler sc;
166 int id;
167 int irq;
168 bool suspended;
169};
170
171static u32 fimc_read(struct fimc_context *ctx, u32 reg)
172{
173 return readl(ctx->regs + reg);
174}
175
176static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
177{
178 writel(val, ctx->regs + reg);
179}
180
181static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
182{
183 void __iomem *r = ctx->regs + reg;
184
185 writel(readl(r) | bits, r);
186}
187
188static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
189{
190 void __iomem *r = ctx->regs + reg;
191
192 writel(readl(r) & ~bits, r);
193}
194
195static void fimc_sw_reset(struct fimc_context *ctx)
196{
197 u32 cfg;
198
199 /* stop dma operation */
200 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
201 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
202 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
203
204 fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
205
206 /* disable image capture */
207 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
208 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
209
210 /* s/w reset */
211 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
212
213 /* s/w reset complete */
214 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
215
216 /* reset sequence */
217 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
218}
219
220static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
221{
222 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
223 SYSREG_FIMD0WB_DEST_MASK,
224 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
225}
226
227static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
228{
229 u32 cfg;
230
231 DRM_DEBUG_KMS("wb[%d]\n", wb);
232
233 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
234 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
235 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
236 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
237 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
238 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
239 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
240
241 switch (wb) {
242 case FIMC_WB_A:
243 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
244 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
245 break;
246 case FIMC_WB_B:
247 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
248 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
249 break;
250 case FIMC_WB_NONE:
251 default:
252 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
253 EXYNOS_CIGCTRL_SELWRITEBACK_A |
254 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
255 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
256 break;
257 }
258
259 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
260}
261
262static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
263{
264 u32 cfg;
265
266 DRM_DEBUG_KMS("enable[%d]\n", enable);
267
268 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
269 if (enable)
270 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
271 else
272 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
273
274 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
275}
276
277static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
278{
279 u32 cfg;
280
281 DRM_DEBUG_KMS("enable[%d]\n", enable);
282
283 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
284 if (enable) {
285 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
286 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
287 } else
288 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
289 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
290}
291
292static void fimc_clear_irq(struct fimc_context *ctx)
293{
294 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
295}
296
297static bool fimc_check_ovf(struct fimc_context *ctx)
298{
299 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
300 u32 status, flag;
301
302 status = fimc_read(ctx, EXYNOS_CISTATUS);
303 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
304 EXYNOS_CISTATUS_OVFICR;
305
306 DRM_DEBUG_KMS("flag[0x%x]\n", flag);
307
308 if (status & flag) {
309 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
310 EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
311 EXYNOS_CIWDOFST_CLROVFICR);
312
313 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
314 ctx->id, status);
315 return true;
316 }
317
318 return false;
319}
320
321static bool fimc_check_frame_end(struct fimc_context *ctx)
322{
323 u32 cfg;
324
325 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
326
327 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
328
329 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
330 return false;
331
332 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
333 fimc_write(ctx, cfg, EXYNOS_CISTATUS);
334
335 return true;
336}
337
338static int fimc_get_buf_id(struct fimc_context *ctx)
339{
340 u32 cfg;
341 int frame_cnt, buf_id;
342
343 cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
344 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
345
346 if (frame_cnt == 0)
347 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
348
349 DRM_DEBUG_KMS("present[%d]before[%d]\n",
350 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
351 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
352
353 if (frame_cnt == 0) {
354 DRM_ERROR("failed to get frame count.\n");
355 return -EIO;
356 }
357
358 buf_id = frame_cnt - 1;
359 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
360
361 return buf_id;
362}
363
364static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
365{
366 u32 cfg;
367
368 DRM_DEBUG_KMS("enable[%d]\n", enable);
369
370 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
371 if (enable)
372 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
373 else
374 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
375
376 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
377}
378
379
380static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
381{
382 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
383 u32 cfg;
384
385 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
386
387 /* RGB */
388 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
389 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
390
391 switch (fmt) {
392 case DRM_FORMAT_RGB565:
393 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
394 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
395 return 0;
396 case DRM_FORMAT_RGB888:
397 case DRM_FORMAT_XRGB8888:
398 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
399 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
400 return 0;
401 default:
402 /* bypass */
403 break;
404 }
405
406 /* YUV */
407 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
408 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
409 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
410 EXYNOS_MSCTRL_ORDER422_YCBYCR);
411
412 switch (fmt) {
413 case DRM_FORMAT_YUYV:
414 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
415 break;
416 case DRM_FORMAT_YVYU:
417 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
418 break;
419 case DRM_FORMAT_UYVY:
420 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
421 break;
422 case DRM_FORMAT_VYUY:
423 case DRM_FORMAT_YUV444:
424 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
425 break;
426 case DRM_FORMAT_NV21:
427 case DRM_FORMAT_NV61:
428 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
429 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
430 break;
431 case DRM_FORMAT_YUV422:
432 case DRM_FORMAT_YUV420:
433 case DRM_FORMAT_YVU420:
434 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
435 break;
436 case DRM_FORMAT_NV12:
437 case DRM_FORMAT_NV16:
438 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
439 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
440 break;
441 default:
442 dev_err(ippdrv->dev, "invalid source yuv order 0x%x.\n", fmt);
443 return -EINVAL;
444 }
445
446 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
447
448 return 0;
449}
450
451static int fimc_src_set_fmt(struct device *dev, u32 fmt)
452{
453 struct fimc_context *ctx = get_fimc_context(dev);
454 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
455 u32 cfg;
456
457 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
458
459 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
460 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
461
462 switch (fmt) {
463 case DRM_FORMAT_RGB565:
464 case DRM_FORMAT_RGB888:
465 case DRM_FORMAT_XRGB8888:
466 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
467 break;
468 case DRM_FORMAT_YUV444:
469 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
470 break;
471 case DRM_FORMAT_YUYV:
472 case DRM_FORMAT_YVYU:
473 case DRM_FORMAT_UYVY:
474 case DRM_FORMAT_VYUY:
475 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
476 break;
477 case DRM_FORMAT_NV16:
478 case DRM_FORMAT_NV61:
479 case DRM_FORMAT_YUV422:
480 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
481 break;
482 case DRM_FORMAT_YUV420:
483 case DRM_FORMAT_YVU420:
484 case DRM_FORMAT_NV12:
485 case DRM_FORMAT_NV21:
486 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
487 break;
488 default:
489 dev_err(ippdrv->dev, "invalid source format 0x%x.\n", fmt);
490 return -EINVAL;
491 }
492
493 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
494
495 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
496 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
497
498 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
499
500 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
501
502 return fimc_src_set_fmt_order(ctx, fmt);
503}
504
505static int fimc_src_set_transf(struct device *dev,
506 enum drm_exynos_degree degree,
507 enum drm_exynos_flip flip, bool *swap)
508{
509 struct fimc_context *ctx = get_fimc_context(dev);
510 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
511 u32 cfg1, cfg2;
512
513 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
514
515 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
516 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
517 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
518
519 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
520 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
521
522 switch (degree) {
523 case EXYNOS_DRM_DEGREE_0:
524 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
525 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
526 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
527 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
528 break;
529 case EXYNOS_DRM_DEGREE_90:
530 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
531 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
532 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
533 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
534 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
535 break;
536 case EXYNOS_DRM_DEGREE_180:
537 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
538 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
539 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
540 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
541 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
542 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
543 break;
544 case EXYNOS_DRM_DEGREE_270:
545 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
546 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
547 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
548 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
549 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
550 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
551 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
552 break;
553 default:
554 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
555 return -EINVAL;
556 }
557
558 fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
559 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
560 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
561
562 return 0;
563}
564
565static int fimc_set_window(struct fimc_context *ctx,
566 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
567{
568 u32 cfg, h1, h2, v1, v2;
569
570 /* cropped image */
571 h1 = pos->x;
572 h2 = sz->hsize - pos->w - pos->x;
573 v1 = pos->y;
574 v2 = sz->vsize - pos->h - pos->y;
575
576 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
577 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
578 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
579
580 /*
581 * set window offset 1, 2 size
582 * check figure 43-21 in user manual
583 */
584 cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
585 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
586 EXYNOS_CIWDOFST_WINVEROFST_MASK);
587 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
588 EXYNOS_CIWDOFST_WINVEROFST(v1));
589 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
590 fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
591
592 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
593 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
594 fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
595
596 return 0;
597}
598
599static int fimc_src_set_size(struct device *dev, int swap,
600 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
601{
602 struct fimc_context *ctx = get_fimc_context(dev);
603 struct drm_exynos_pos img_pos = *pos;
604 struct drm_exynos_sz img_sz = *sz;
605 u32 cfg;
606
607 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
608 swap, sz->hsize, sz->vsize);
609
610 /* original size */
611 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
612 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
613
614 fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
615
616 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
617
618 if (swap) {
619 img_pos.w = pos->h;
620 img_pos.h = pos->w;
621 img_sz.hsize = sz->vsize;
622 img_sz.vsize = sz->hsize;
623 }
624
625 /* set input DMA image size */
626 cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
627 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
628 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
629 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
630 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
631 fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
632
633 /*
634 * set input FIFO image size
635 * for now, we support only ITU601 8 bit mode
636 */
637 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
638 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
639 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
640 fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
641
642 /* offset Y(RGB), Cb, Cr */
643 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
644 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
645 fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
646 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
647 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
648 fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
649 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
650 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
651 fimc_write(ctx, cfg, EXYNOS_CIICROFF);
652
653 return fimc_set_window(ctx, &img_pos, &img_sz);
654}
655
656static int fimc_src_set_addr(struct device *dev,
657 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
658 enum drm_exynos_ipp_buf_type buf_type)
659{
660 struct fimc_context *ctx = get_fimc_context(dev);
661 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
662 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
663 struct drm_exynos_ipp_property *property;
664 struct drm_exynos_ipp_config *config;
665
666 if (!c_node) {
667 DRM_ERROR("failed to get c_node.\n");
668 return -EINVAL;
669 }
670
671 property = &c_node->property;
672
673 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
674 property->prop_id, buf_id, buf_type);
675
676 if (buf_id > FIMC_MAX_SRC) {
677 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
678 return -ENOMEM;
679 }
680
681 /* address register set */
682 switch (buf_type) {
683 case IPP_BUF_ENQUEUE:
684 config = &property->config[EXYNOS_DRM_OPS_SRC];
685 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
686 EXYNOS_CIIYSA0);
687
688 if (config->fmt == DRM_FORMAT_YVU420) {
689 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
690 EXYNOS_CIICBSA0);
691 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
692 EXYNOS_CIICRSA0);
693 } else {
694 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
695 EXYNOS_CIICBSA0);
696 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
697 EXYNOS_CIICRSA0);
698 }
699 break;
700 case IPP_BUF_DEQUEUE:
701 fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
702 fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
703 fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
704 break;
705 default:
706 /* bypass */
707 break;
708 }
709
710 return 0;
711}
712
713static struct exynos_drm_ipp_ops fimc_src_ops = {
714 .set_fmt = fimc_src_set_fmt,
715 .set_transf = fimc_src_set_transf,
716 .set_size = fimc_src_set_size,
717 .set_addr = fimc_src_set_addr,
718};
719
720static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
721{
722 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
723 u32 cfg;
724
725 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
726
727 /* RGB */
728 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
729 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
730
731 switch (fmt) {
732 case DRM_FORMAT_RGB565:
733 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
734 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
735 return 0;
736 case DRM_FORMAT_RGB888:
737 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
738 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
739 return 0;
740 case DRM_FORMAT_XRGB8888:
741 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
742 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
743 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
744 break;
745 default:
746 /* bypass */
747 break;
748 }
749
750 /* YUV */
751 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
752 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
753 EXYNOS_CIOCTRL_ORDER422_MASK |
754 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
755
756 switch (fmt) {
757 case DRM_FORMAT_XRGB8888:
758 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
759 break;
760 case DRM_FORMAT_YUYV:
761 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
762 break;
763 case DRM_FORMAT_YVYU:
764 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
765 break;
766 case DRM_FORMAT_UYVY:
767 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
768 break;
769 case DRM_FORMAT_VYUY:
770 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
771 break;
772 case DRM_FORMAT_NV21:
773 case DRM_FORMAT_NV61:
774 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
775 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
776 break;
777 case DRM_FORMAT_YUV422:
778 case DRM_FORMAT_YUV420:
779 case DRM_FORMAT_YVU420:
780 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
781 break;
782 case DRM_FORMAT_NV12:
783 case DRM_FORMAT_NV16:
784 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
785 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
786 break;
787 default:
788 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
789 return -EINVAL;
790 }
791
792 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
793
794 return 0;
795}
796
797static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
798{
799 struct fimc_context *ctx = get_fimc_context(dev);
800 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
801 u32 cfg;
802
803 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
804
805 cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
806
807 if (fmt == DRM_FORMAT_AYUV) {
808 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
809 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
810 } else {
811 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
812 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
813
814 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
815 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
816
817 switch (fmt) {
818 case DRM_FORMAT_RGB565:
819 case DRM_FORMAT_RGB888:
820 case DRM_FORMAT_XRGB8888:
821 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
822 break;
823 case DRM_FORMAT_YUYV:
824 case DRM_FORMAT_YVYU:
825 case DRM_FORMAT_UYVY:
826 case DRM_FORMAT_VYUY:
827 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
828 break;
829 case DRM_FORMAT_NV16:
830 case DRM_FORMAT_NV61:
831 case DRM_FORMAT_YUV422:
832 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
833 break;
834 case DRM_FORMAT_YUV420:
835 case DRM_FORMAT_YVU420:
836 case DRM_FORMAT_NV12:
837 case DRM_FORMAT_NV21:
838 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
839 break;
840 default:
841 dev_err(ippdrv->dev, "invalid target format 0x%x.\n",
842 fmt);
843 return -EINVAL;
844 }
845
846 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
847 }
848
849 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
850 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
851
852 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
853
854 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
855
856 return fimc_dst_set_fmt_order(ctx, fmt);
857}
858
859static int fimc_dst_set_transf(struct device *dev,
860 enum drm_exynos_degree degree,
861 enum drm_exynos_flip flip, bool *swap)
862{
863 struct fimc_context *ctx = get_fimc_context(dev);
864 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
865 u32 cfg;
866
867 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
868
869 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
870 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
871 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
872
873 switch (degree) {
874 case EXYNOS_DRM_DEGREE_0:
875 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
876 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
877 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
878 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
879 break;
880 case EXYNOS_DRM_DEGREE_90:
881 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
882 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
883 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
884 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
885 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
886 break;
887 case EXYNOS_DRM_DEGREE_180:
888 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
889 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
890 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
891 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
892 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
893 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
894 break;
895 case EXYNOS_DRM_DEGREE_270:
896 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
897 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
898 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
899 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
900 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
901 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
902 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
903 break;
904 default:
905 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
906 return -EINVAL;
907 }
908
909 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
910 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
911
912 return 0;
913}
914
915static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
916 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
917{
918 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
919 u32 cfg, cfg_ext, shfactor;
920 u32 pre_dst_width, pre_dst_height;
921 u32 hfactor, vfactor;
922 int ret = 0;
923 u32 src_w, src_h, dst_w, dst_h;
924
925 cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
926 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
927 src_w = src->h;
928 src_h = src->w;
929 } else {
930 src_w = src->w;
931 src_h = src->h;
932 }
933
934 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
935 dst_w = dst->h;
936 dst_h = dst->w;
937 } else {
938 dst_w = dst->w;
939 dst_h = dst->h;
940 }
941
942 /* fimc_ippdrv_check_property assures that dividers are not null */
943 hfactor = fls(src_w / dst_w / 2);
944 if (hfactor > FIMC_SHFACTOR / 2) {
945 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
946 return -EINVAL;
947 }
948
949 vfactor = fls(src_h / dst_h / 2);
950 if (vfactor > FIMC_SHFACTOR / 2) {
951 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
952 return -EINVAL;
953 }
954
955 pre_dst_width = src_w >> hfactor;
956 pre_dst_height = src_h >> vfactor;
957 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
958 pre_dst_width, pre_dst_height);
959 DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
960
961 sc->hratio = (src_w << 14) / (dst_w << hfactor);
962 sc->vratio = (src_h << 14) / (dst_h << vfactor);
963 sc->up_h = (dst_w >= src_w) ? true : false;
964 sc->up_v = (dst_h >= src_h) ? true : false;
965 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
966 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
967
968 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
969 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
970
971 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
972 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
973 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
974 fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
975
976 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
977 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
978 fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
979
980 return ret;
981}
982
983static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
984{
985 u32 cfg, cfg_ext;
986
987 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
988 sc->range, sc->bypass, sc->up_h, sc->up_v);
989 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
990 sc->hratio, sc->vratio);
991
992 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
993 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
994 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
995 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
996 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
997 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
998 EXYNOS_CISCCTRL_CSCY2R_WIDE);
999
1000 if (sc->range)
1001 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1002 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1003 if (sc->bypass)
1004 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1005 if (sc->up_h)
1006 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1007 if (sc->up_v)
1008 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1009
1010 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1011 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1012 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1013
1014 cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1015 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1016 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1017 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1018 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1019 fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1020}
1021
1022static int fimc_dst_set_size(struct device *dev, int swap,
1023 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1024{
1025 struct fimc_context *ctx = get_fimc_context(dev);
1026 struct drm_exynos_pos img_pos = *pos;
1027 struct drm_exynos_sz img_sz = *sz;
1028 u32 cfg;
1029
1030 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1031 swap, sz->hsize, sz->vsize);
1032
1033 /* original size */
1034 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1035 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1036
1037 fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1038
1039 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1040
1041 /* CSC ITU */
1042 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1043 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1044
1045 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1046 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1047 else
1048 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1049
1050 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1051
1052 if (swap) {
1053 img_pos.w = pos->h;
1054 img_pos.h = pos->w;
1055 img_sz.hsize = sz->vsize;
1056 img_sz.vsize = sz->hsize;
1057 }
1058
1059 /* target image size */
1060 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1061 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1062 EXYNOS_CITRGFMT_TARGETV_MASK);
1063 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1064 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1065 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1066
1067 /* target area */
1068 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1069 fimc_write(ctx, cfg, EXYNOS_CITAREA);
1070
1071 /* offset Y(RGB), Cb, Cr */
1072 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1073 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1074 fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1075 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1076 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1077 fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1078 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1079 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1080 fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1081
1082 return 0;
1083}
1084
1085static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1086 enum drm_exynos_ipp_buf_type buf_type)
1087{
1088 unsigned long flags;
1089 u32 buf_num;
1090 u32 cfg;
1091
1092 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1093
1094 spin_lock_irqsave(&ctx->lock, flags);
1095
1096 cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1097
1098 if (buf_type == IPP_BUF_ENQUEUE)
1099 cfg |= (1 << buf_id);
1100 else
1101 cfg &= ~(1 << buf_id);
1102
1103 fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1104
1105 buf_num = hweight32(cfg);
1106
1107 if (buf_type == IPP_BUF_ENQUEUE && buf_num >= FIMC_BUF_START)
1108 fimc_mask_irq(ctx, true);
1109 else if (buf_type == IPP_BUF_DEQUEUE && buf_num <= FIMC_BUF_STOP)
1110 fimc_mask_irq(ctx, false);
1111
1112 spin_unlock_irqrestore(&ctx->lock, flags);
1113}
1114
1115static int fimc_dst_set_addr(struct device *dev,
1116 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1117 enum drm_exynos_ipp_buf_type buf_type)
1118{
1119 struct fimc_context *ctx = get_fimc_context(dev);
1120 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1121 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1122 struct drm_exynos_ipp_property *property;
1123 struct drm_exynos_ipp_config *config;
1124
1125 if (!c_node) {
1126 DRM_ERROR("failed to get c_node.\n");
1127 return -EINVAL;
1128 }
1129
1130 property = &c_node->property;
1131
1132 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1133 property->prop_id, buf_id, buf_type);
1134
1135 if (buf_id > FIMC_MAX_DST) {
1136 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
1137 return -ENOMEM;
1138 }
1139
1140 /* address register set */
1141 switch (buf_type) {
1142 case IPP_BUF_ENQUEUE:
1143 config = &property->config[EXYNOS_DRM_OPS_DST];
1144
1145 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1146 EXYNOS_CIOYSA(buf_id));
1147
1148 if (config->fmt == DRM_FORMAT_YVU420) {
1149 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1150 EXYNOS_CIOCBSA(buf_id));
1151 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1152 EXYNOS_CIOCRSA(buf_id));
1153 } else {
1154 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1155 EXYNOS_CIOCBSA(buf_id));
1156 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1157 EXYNOS_CIOCRSA(buf_id));
1158 }
1159 break;
1160 case IPP_BUF_DEQUEUE:
1161 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1162 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1163 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1164 break;
1165 default:
1166 /* bypass */
1167 break;
1168 }
1169
1170 fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1171
1172 return 0;
1173}
1174
1175static struct exynos_drm_ipp_ops fimc_dst_ops = {
1176 .set_fmt = fimc_dst_set_fmt,
1177 .set_transf = fimc_dst_set_transf,
1178 .set_size = fimc_dst_set_size,
1179 .set_addr = fimc_dst_set_addr,
1180};
1181
1182static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1183{
1184 struct fimc_context *ctx = dev_id;
1185 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1186 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1187 struct drm_exynos_ipp_event_work *event_work =
1188 c_node->event_work;
1189 int buf_id;
1190
1191 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1192
1193 fimc_clear_irq(ctx);
1194 if (fimc_check_ovf(ctx))
1195 return IRQ_NONE;
1196
1197 if (!fimc_check_frame_end(ctx))
1198 return IRQ_NONE;
1199
1200 buf_id = fimc_get_buf_id(ctx);
1201 if (buf_id < 0)
1202 return IRQ_HANDLED;
1203
1204 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1205
1206 fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1207
1208 event_work->ippdrv = ippdrv;
1209 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1210 queue_work(ippdrv->event_workq, &event_work->work);
1211
1212 return IRQ_HANDLED;
1213}
1214
1215static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1216{
1217 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1218
1219 prop_list->version = 1;
1220 prop_list->writeback = 1;
1221 prop_list->refresh_min = FIMC_REFRESH_MIN;
1222 prop_list->refresh_max = FIMC_REFRESH_MAX;
1223 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1224 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1225 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1226 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1227 (1 << EXYNOS_DRM_DEGREE_90) |
1228 (1 << EXYNOS_DRM_DEGREE_180) |
1229 (1 << EXYNOS_DRM_DEGREE_270);
1230 prop_list->csc = 1;
1231 prop_list->crop = 1;
1232 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1233 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1234 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1235 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1236 prop_list->scale = 1;
1237 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1238 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1239 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1240 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1241
1242 return 0;
1243}
1244
1245static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1246{
1247 switch (flip) {
1248 case EXYNOS_DRM_FLIP_NONE:
1249 case EXYNOS_DRM_FLIP_VERTICAL:
1250 case EXYNOS_DRM_FLIP_HORIZONTAL:
1251 case EXYNOS_DRM_FLIP_BOTH:
1252 return true;
1253 default:
1254 DRM_DEBUG_KMS("invalid flip\n");
1255 return false;
1256 }
1257}
1258
1259static int fimc_ippdrv_check_property(struct device *dev,
1260 struct drm_exynos_ipp_property *property)
1261{
1262 struct fimc_context *ctx = get_fimc_context(dev);
1263 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1264 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1265 struct drm_exynos_ipp_config *config;
1266 struct drm_exynos_pos *pos;
1267 struct drm_exynos_sz *sz;
1268 bool swap;
1269 int i;
1270
1271 for_each_ipp_ops(i) {
1272 if ((i == EXYNOS_DRM_OPS_SRC) &&
1273 (property->cmd == IPP_CMD_WB))
1274 continue;
1275
1276 config = &property->config[i];
1277 pos = &config->pos;
1278 sz = &config->sz;
1279
1280 /* check for flip */
1281 if (!fimc_check_drm_flip(config->flip)) {
1282 DRM_ERROR("invalid flip.\n");
1283 goto err_property;
1284 }
1285
1286 /* check for degree */
1287 switch (config->degree) {
1288 case EXYNOS_DRM_DEGREE_90:
1289 case EXYNOS_DRM_DEGREE_270:
1290 swap = true;
1291 break;
1292 case EXYNOS_DRM_DEGREE_0:
1293 case EXYNOS_DRM_DEGREE_180:
1294 swap = false;
1295 break;
1296 default:
1297 DRM_ERROR("invalid degree.\n");
1298 goto err_property;
1299 }
1300
1301 /* check for buffer bound */
1302 if ((pos->x + pos->w > sz->hsize) ||
1303 (pos->y + pos->h > sz->vsize)) {
1304 DRM_ERROR("out of buf bound.\n");
1305 goto err_property;
1306 }
1307
1308 /* check for crop */
1309 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1310 if (swap) {
1311 if ((pos->h < pp->crop_min.hsize) ||
1312 (sz->vsize > pp->crop_max.hsize) ||
1313 (pos->w < pp->crop_min.vsize) ||
1314 (sz->hsize > pp->crop_max.vsize)) {
1315 DRM_ERROR("out of crop size.\n");
1316 goto err_property;
1317 }
1318 } else {
1319 if ((pos->w < pp->crop_min.hsize) ||
1320 (sz->hsize > pp->crop_max.hsize) ||
1321 (pos->h < pp->crop_min.vsize) ||
1322 (sz->vsize > pp->crop_max.vsize)) {
1323 DRM_ERROR("out of crop size.\n");
1324 goto err_property;
1325 }
1326 }
1327 }
1328
1329 /* check for scale */
1330 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1331 if (swap) {
1332 if ((pos->h < pp->scale_min.hsize) ||
1333 (sz->vsize > pp->scale_max.hsize) ||
1334 (pos->w < pp->scale_min.vsize) ||
1335 (sz->hsize > pp->scale_max.vsize)) {
1336 DRM_ERROR("out of scale size.\n");
1337 goto err_property;
1338 }
1339 } else {
1340 if ((pos->w < pp->scale_min.hsize) ||
1341 (sz->hsize > pp->scale_max.hsize) ||
1342 (pos->h < pp->scale_min.vsize) ||
1343 (sz->vsize > pp->scale_max.vsize)) {
1344 DRM_ERROR("out of scale size.\n");
1345 goto err_property;
1346 }
1347 }
1348 }
1349 }
1350
1351 return 0;
1352
1353err_property:
1354 for_each_ipp_ops(i) {
1355 if ((i == EXYNOS_DRM_OPS_SRC) &&
1356 (property->cmd == IPP_CMD_WB))
1357 continue;
1358
1359 config = &property->config[i];
1360 pos = &config->pos;
1361 sz = &config->sz;
1362
1363 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1364 i ? "dst" : "src", config->flip, config->degree,
1365 pos->x, pos->y, pos->w, pos->h,
1366 sz->hsize, sz->vsize);
1367 }
1368
1369 return -EINVAL;
1370}
1371
1372static void fimc_clear_addr(struct fimc_context *ctx)
1373{
1374 int i;
1375
1376 for (i = 0; i < FIMC_MAX_SRC; i++) {
1377 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1378 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1379 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1380 }
1381
1382 for (i = 0; i < FIMC_MAX_DST; i++) {
1383 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1384 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1385 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1386 }
1387}
1388
1389static int fimc_ippdrv_reset(struct device *dev)
1390{
1391 struct fimc_context *ctx = get_fimc_context(dev);
1392
1393 /* reset h/w block */
1394 fimc_sw_reset(ctx);
1395
1396 /* reset scaler capability */
1397 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1398
1399 fimc_clear_addr(ctx);
1400
1401 return 0;
1402}
1403
1404static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1405{
1406 struct fimc_context *ctx = get_fimc_context(dev);
1407 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1408 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1409 struct drm_exynos_ipp_property *property;
1410 struct drm_exynos_ipp_config *config;
1411 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1412 struct drm_exynos_ipp_set_wb set_wb;
1413 int ret, i;
1414 u32 cfg0, cfg1;
1415
1416 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1417
1418 if (!c_node) {
1419 DRM_ERROR("failed to get c_node.\n");
1420 return -EINVAL;
1421 }
1422
1423 property = &c_node->property;
1424
1425 fimc_mask_irq(ctx, true);
1426
1427 for_each_ipp_ops(i) {
1428 config = &property->config[i];
1429 img_pos[i] = config->pos;
1430 }
1431
1432 ret = fimc_set_prescaler(ctx, &ctx->sc,
1433 &img_pos[EXYNOS_DRM_OPS_SRC],
1434 &img_pos[EXYNOS_DRM_OPS_DST]);
1435 if (ret) {
1436 dev_err(dev, "failed to set precalser.\n");
1437 return ret;
1438 }
1439
1440 /* If set ture, we can save jpeg about screen */
1441 fimc_handle_jpeg(ctx, false);
1442 fimc_set_scaler(ctx, &ctx->sc);
1443
1444 switch (cmd) {
1445 case IPP_CMD_M2M:
1446 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1447 fimc_handle_lastend(ctx, false);
1448
1449 /* setup dma */
1450 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1451 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1452 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1453 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1454 break;
1455 case IPP_CMD_WB:
1456 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1457 fimc_handle_lastend(ctx, true);
1458
1459 /* setup FIMD */
1460 ret = fimc_set_camblk_fimd0_wb(ctx);
1461 if (ret < 0) {
1462 dev_err(dev, "camblk setup failed.\n");
1463 return ret;
1464 }
1465
1466 set_wb.enable = 1;
1467 set_wb.refresh = property->refresh_rate;
1468 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1469 break;
1470 case IPP_CMD_OUTPUT:
1471 default:
1472 ret = -EINVAL;
1473 dev_err(dev, "invalid operations.\n");
1474 return ret;
1475 }
1476
1477 /* Reset status */
1478 fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1479
1480 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1481 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1482 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1483
1484 /* Scaler */
1485 cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1486 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1487 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1488 EXYNOS_CISCCTRL_SCALERSTART);
1489
1490 fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1491
1492 /* Enable image capture*/
1493 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1494 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1495
1496 /* Disable frame end irq */
1497 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1498
1499 fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1500
1501 if (cmd == IPP_CMD_M2M)
1502 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1503
1504 return 0;
1505}
1506
1507static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1508{
1509 struct fimc_context *ctx = get_fimc_context(dev);
1510 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1511 u32 cfg;
1512
1513 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1514
1515 switch (cmd) {
1516 case IPP_CMD_M2M:
1517 /* Source clear */
1518 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1519 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1520 cfg &= ~EXYNOS_MSCTRL_ENVID;
1521 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1522 break;
1523 case IPP_CMD_WB:
1524 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1525 break;
1526 case IPP_CMD_OUTPUT:
1527 default:
1528 dev_err(dev, "invalid operations.\n");
1529 break;
1530 }
1531
1532 fimc_mask_irq(ctx, false);
1533
1534 /* reset sequence */
1535 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1536
1537 /* Scaler disable */
1538 fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1539
1540 /* Disable image capture */
1541 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1542 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1543
1544 /* Enable frame end irq */
1545 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1546}
1547
1548static void fimc_put_clocks(struct fimc_context *ctx)
1549{
1550 int i;
1551
1552 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1553 if (IS_ERR(ctx->clocks[i]))
1554 continue;
1555 clk_put(ctx->clocks[i]);
1556 ctx->clocks[i] = ERR_PTR(-EINVAL);
1557 }
1558}
1559
1560static int fimc_setup_clocks(struct fimc_context *ctx)
1561{
1562 struct device *fimc_dev = ctx->ippdrv.dev;
1563 struct device *dev;
1564 int ret, i;
1565
1566 for (i = 0; i < FIMC_CLKS_MAX; i++)
1567 ctx->clocks[i] = ERR_PTR(-EINVAL);
1568
1569 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1570 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1571 dev = fimc_dev->parent;
1572 else
1573 dev = fimc_dev;
1574
1575 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1576 if (IS_ERR(ctx->clocks[i])) {
1577 if (i >= FIMC_CLK_MUX)
1578 break;
1579 ret = PTR_ERR(ctx->clocks[i]);
1580 dev_err(fimc_dev, "failed to get clock: %s\n",
1581 fimc_clock_names[i]);
1582 goto e_clk_free;
1583 }
1584 }
1585
1586 /* Optional FIMC LCLK parent clock setting */
1587 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1588 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1589 ctx->clocks[FIMC_CLK_PARENT]);
1590 if (ret < 0) {
1591 dev_err(fimc_dev, "failed to set parent.\n");
1592 goto e_clk_free;
1593 }
1594 }
1595
1596 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1597 if (ret < 0)
1598 goto e_clk_free;
1599
1600 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1601 if (!ret)
1602 return ret;
1603e_clk_free:
1604 fimc_put_clocks(ctx);
1605 return ret;
1606}
1607
1608static int fimc_parse_dt(struct fimc_context *ctx)
1609{
1610 struct device_node *node = ctx->ippdrv.dev->of_node;
1611
1612 /* Handle only devices that support the LCD Writeback data path */
1613 if (!of_property_read_bool(node, "samsung,lcd-wb"))
1614 return -ENODEV;
1615
1616 if (of_property_read_u32(node, "clock-frequency",
1617 &ctx->clk_frequency))
1618 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1619
1620 ctx->id = of_alias_get_id(node, "fimc");
1621
1622 if (ctx->id < 0) {
1623 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1624 return -EINVAL;
1625 }
1626
1627 return 0;
1628}
1629
1630static int fimc_probe(struct platform_device *pdev)
1631{
1632 struct device *dev = &pdev->dev;
1633 struct fimc_context *ctx;
1634 struct resource *res;
1635 struct exynos_drm_ippdrv *ippdrv;
1636 int ret;
1637
1638 if (!dev->of_node) {
1639 dev_err(dev, "device tree node not found.\n");
1640 return -ENODEV;
1641 }
1642
1643 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1644 if (!ctx)
1645 return -ENOMEM;
1646
1647 ctx->ippdrv.dev = dev;
1648
1649 ret = fimc_parse_dt(ctx);
1650 if (ret < 0)
1651 return ret;
1652
1653 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1654 "samsung,sysreg");
1655 if (IS_ERR(ctx->sysreg)) {
1656 dev_err(dev, "syscon regmap lookup failed.\n");
1657 return PTR_ERR(ctx->sysreg);
1658 }
1659
1660 /* resource memory */
1661 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1662 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1663 if (IS_ERR(ctx->regs))
1664 return PTR_ERR(ctx->regs);
1665
1666 /* resource irq */
1667 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1668 if (!res) {
1669 dev_err(dev, "failed to request irq resource.\n");
1670 return -ENOENT;
1671 }
1672
1673 ctx->irq = res->start;
1674 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1675 IRQF_ONESHOT, "drm_fimc", ctx);
1676 if (ret < 0) {
1677 dev_err(dev, "failed to request irq.\n");
1678 return ret;
1679 }
1680
1681 ret = fimc_setup_clocks(ctx);
1682 if (ret < 0)
1683 return ret;
1684
1685 ippdrv = &ctx->ippdrv;
1686 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1687 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1688 ippdrv->check_property = fimc_ippdrv_check_property;
1689 ippdrv->reset = fimc_ippdrv_reset;
1690 ippdrv->start = fimc_ippdrv_start;
1691 ippdrv->stop = fimc_ippdrv_stop;
1692 ret = fimc_init_prop_list(ippdrv);
1693 if (ret < 0) {
1694 dev_err(dev, "failed to init property list.\n");
1695 goto err_put_clk;
1696 }
1697
1698 DRM_DEBUG_KMS("id[%d]ippdrv[%p]\n", ctx->id, ippdrv);
1699
1700 spin_lock_init(&ctx->lock);
1701 platform_set_drvdata(pdev, ctx);
1702
1703 pm_runtime_enable(dev);
1704
1705 ret = exynos_drm_ippdrv_register(ippdrv);
1706 if (ret < 0) {
1707 dev_err(dev, "failed to register drm fimc device.\n");
1708 goto err_pm_dis;
1709 }
1710
1711 dev_info(dev, "drm fimc registered successfully.\n");
1712
1713 return 0;
1714
1715err_pm_dis:
1716 pm_runtime_disable(dev);
1717err_put_clk:
1718 fimc_put_clocks(ctx);
1719
1720 return ret;
1721}
1722
1723static int fimc_remove(struct platform_device *pdev)
1724{
1725 struct device *dev = &pdev->dev;
1726 struct fimc_context *ctx = get_fimc_context(dev);
1727 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1728
1729 exynos_drm_ippdrv_unregister(ippdrv);
1730
1731 fimc_put_clocks(ctx);
1732 pm_runtime_set_suspended(dev);
1733 pm_runtime_disable(dev);
1734
1735 return 0;
1736}
1737
1738#ifdef CONFIG_PM
1739static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1740{
1741 DRM_DEBUG_KMS("enable[%d]\n", enable);
1742
1743 if (enable) {
1744 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1745 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1746 ctx->suspended = false;
1747 } else {
1748 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1749 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1750 ctx->suspended = true;
1751 }
1752
1753 return 0;
1754}
1755
1756#ifdef CONFIG_PM_SLEEP
1757static int fimc_suspend(struct device *dev)
1758{
1759 struct fimc_context *ctx = get_fimc_context(dev);
1760
1761 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1762
1763 if (pm_runtime_suspended(dev))
1764 return 0;
1765
1766 return fimc_clk_ctrl(ctx, false);
1767}
1768
1769static int fimc_resume(struct device *dev)
1770{
1771 struct fimc_context *ctx = get_fimc_context(dev);
1772
1773 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1774
1775 if (!pm_runtime_suspended(dev))
1776 return fimc_clk_ctrl(ctx, true);
1777
1778 return 0;
1779}
1780#endif
1781
1782static int fimc_runtime_suspend(struct device *dev)
1783{
1784 struct fimc_context *ctx = get_fimc_context(dev);
1785
1786 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1787
1788 return fimc_clk_ctrl(ctx, false);
1789}
1790
1791static int fimc_runtime_resume(struct device *dev)
1792{
1793 struct fimc_context *ctx = get_fimc_context(dev);
1794
1795 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1796
1797 return fimc_clk_ctrl(ctx, true);
1798}
1799#endif
1800
1801static const struct dev_pm_ops fimc_pm_ops = {
1802 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1803 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1804};
1805
1806static const struct of_device_id fimc_of_match[] = {
1807 { .compatible = "samsung,exynos4210-fimc" },
1808 { .compatible = "samsung,exynos4212-fimc" },
1809 { },
1810};
1811MODULE_DEVICE_TABLE(of, fimc_of_match);
1812
1813struct platform_driver fimc_driver = {
1814 .probe = fimc_probe,
1815 .remove = fimc_remove,
1816 .driver = {
1817 .of_match_table = fimc_of_match,
1818 .name = "exynos-drm-fimc",
1819 .owner = THIS_MODULE,
1820 .pm = &fimc_pm_ops,
1821 },
1822};
1823
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include <linux/clk.h>
19#include <linux/pm_runtime.h>
20#include <linux/of.h>
21
22#include <drm/drmP.h>
23#include <drm/exynos_drm.h>
24#include "regs-fimc.h"
25#include "exynos_drm_drv.h"
26#include "exynos_drm_ipp.h"
27#include "exynos_drm_fimc.h"
28
29/*
30 * FIMC stands for Fully Interactive Mobile Camera and
31 * supports image scaler/rotator and input/output DMA operations.
32 * input DMA reads image data from the memory.
33 * output DMA writes image data to memory.
34 * FIMC supports image rotation and image effect functions.
35 *
36 * M2M operation : supports crop/scale/rotation/csc so on.
37 * Memory ----> FIMC H/W ----> Memory.
38 * Writeback operation : supports cloned screen with FIMD.
39 * FIMD ----> FIMC H/W ----> Memory.
40 * Output operation : supports direct display using local path.
41 * Memory ----> FIMC H/W ----> FIMD.
42 */
43
44/*
45 * TODO
46 * 1. check suspend/resume api if needed.
47 * 2. need to check use case platform_device_id.
48 * 3. check src/dst size with, height.
49 * 4. added check_prepare api for right register.
50 * 5. need to add supported list in prop_list.
51 * 6. check prescaler/scaler optimization.
52 */
53
54#define FIMC_MAX_DEVS 4
55#define FIMC_MAX_SRC 2
56#define FIMC_MAX_DST 32
57#define FIMC_SHFACTOR 10
58#define FIMC_BUF_STOP 1
59#define FIMC_BUF_START 2
60#define FIMC_REG_SZ 32
61#define FIMC_WIDTH_ITU_709 1280
62#define FIMC_REFRESH_MAX 60
63#define FIMC_REFRESH_MIN 12
64#define FIMC_CROP_MAX 8192
65#define FIMC_CROP_MIN 32
66#define FIMC_SCALE_MAX 4224
67#define FIMC_SCALE_MIN 32
68
69#define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
70#define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
71 struct fimc_context, ippdrv);
72#define fimc_read(offset) readl(ctx->regs + (offset))
73#define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
74
75enum fimc_wb {
76 FIMC_WB_NONE,
77 FIMC_WB_A,
78 FIMC_WB_B,
79};
80
81enum {
82 FIMC_CLK_LCLK,
83 FIMC_CLK_GATE,
84 FIMC_CLK_WB_A,
85 FIMC_CLK_WB_B,
86 FIMC_CLK_MUX,
87 FIMC_CLK_PARENT,
88 FIMC_CLKS_MAX
89};
90
91static const char * const fimc_clock_names[] = {
92 [FIMC_CLK_LCLK] = "sclk_fimc",
93 [FIMC_CLK_GATE] = "fimc",
94 [FIMC_CLK_WB_A] = "pxl_async0",
95 [FIMC_CLK_WB_B] = "pxl_async1",
96 [FIMC_CLK_MUX] = "mux",
97 [FIMC_CLK_PARENT] = "parent",
98};
99
100#define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
101
102/*
103 * A structure of scaler.
104 *
105 * @range: narrow, wide.
106 * @bypass: unused scaler path.
107 * @up_h: horizontal scale up.
108 * @up_v: vertical scale up.
109 * @hratio: horizontal ratio.
110 * @vratio: vertical ratio.
111 */
112struct fimc_scaler {
113 bool range;
114 bool bypass;
115 bool up_h;
116 bool up_v;
117 u32 hratio;
118 u32 vratio;
119};
120
121/*
122 * A structure of scaler capability.
123 *
124 * find user manual table 43-1.
125 * @in_hori: scaler input horizontal size.
126 * @bypass: scaler bypass mode.
127 * @dst_h_wo_rot: target horizontal size without output rotation.
128 * @dst_h_rot: target horizontal size with output rotation.
129 * @rl_w_wo_rot: real width without input rotation.
130 * @rl_h_rot: real height without output rotation.
131 */
132struct fimc_capability {
133 /* scaler */
134 u32 in_hori;
135 u32 bypass;
136 /* output rotator */
137 u32 dst_h_wo_rot;
138 u32 dst_h_rot;
139 /* input rotator */
140 u32 rl_w_wo_rot;
141 u32 rl_h_rot;
142};
143
144/*
145 * A structure of fimc context.
146 *
147 * @ippdrv: prepare initialization using ippdrv.
148 * @regs_res: register resources.
149 * @regs: memory mapped io registers.
150 * @lock: locking of operations.
151 * @clocks: fimc clocks.
152 * @clk_frequency: LCLK clock frequency.
153 * @sysreg: handle to SYSREG block regmap.
154 * @sc: scaler infomations.
155 * @pol: porarity of writeback.
156 * @id: fimc id.
157 * @irq: irq number.
158 * @suspended: qos operations.
159 */
160struct fimc_context {
161 struct exynos_drm_ippdrv ippdrv;
162 struct resource *regs_res;
163 void __iomem *regs;
164 struct mutex lock;
165 struct clk *clocks[FIMC_CLKS_MAX];
166 u32 clk_frequency;
167 struct regmap *sysreg;
168 struct fimc_scaler sc;
169 struct exynos_drm_ipp_pol pol;
170 int id;
171 int irq;
172 bool suspended;
173};
174
175static void fimc_sw_reset(struct fimc_context *ctx)
176{
177 u32 cfg;
178
179 /* stop dma operation */
180 cfg = fimc_read(EXYNOS_CISTATUS);
181 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
182 cfg = fimc_read(EXYNOS_MSCTRL);
183 cfg &= ~EXYNOS_MSCTRL_ENVID;
184 fimc_write(cfg, EXYNOS_MSCTRL);
185 }
186
187 cfg = fimc_read(EXYNOS_CISRCFMT);
188 cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
189 fimc_write(cfg, EXYNOS_CISRCFMT);
190
191 /* disable image capture */
192 cfg = fimc_read(EXYNOS_CIIMGCPT);
193 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
194 fimc_write(cfg, EXYNOS_CIIMGCPT);
195
196 /* s/w reset */
197 cfg = fimc_read(EXYNOS_CIGCTRL);
198 cfg |= (EXYNOS_CIGCTRL_SWRST);
199 fimc_write(cfg, EXYNOS_CIGCTRL);
200
201 /* s/w reset complete */
202 cfg = fimc_read(EXYNOS_CIGCTRL);
203 cfg &= ~EXYNOS_CIGCTRL_SWRST;
204 fimc_write(cfg, EXYNOS_CIGCTRL);
205
206 /* reset sequence */
207 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
208}
209
210static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
211{
212 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
213 SYSREG_FIMD0WB_DEST_MASK,
214 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
215}
216
217static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
218{
219 u32 cfg;
220
221 DRM_DEBUG_KMS("wb[%d]\n", wb);
222
223 cfg = fimc_read(EXYNOS_CIGCTRL);
224 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
225 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
226 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
227 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
228 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
229 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
230
231 switch (wb) {
232 case FIMC_WB_A:
233 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
234 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
235 break;
236 case FIMC_WB_B:
237 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
238 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
239 break;
240 case FIMC_WB_NONE:
241 default:
242 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
243 EXYNOS_CIGCTRL_SELWRITEBACK_A |
244 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
245 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
246 break;
247 }
248
249 fimc_write(cfg, EXYNOS_CIGCTRL);
250}
251
252static void fimc_set_polarity(struct fimc_context *ctx,
253 struct exynos_drm_ipp_pol *pol)
254{
255 u32 cfg;
256
257 DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
258 pol->inv_pclk, pol->inv_vsync);
259 DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
260 pol->inv_href, pol->inv_hsync);
261
262 cfg = fimc_read(EXYNOS_CIGCTRL);
263 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
264 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
265
266 if (pol->inv_pclk)
267 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
268 if (pol->inv_vsync)
269 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
270 if (pol->inv_href)
271 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
272 if (pol->inv_hsync)
273 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
274
275 fimc_write(cfg, EXYNOS_CIGCTRL);
276}
277
278static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
279{
280 u32 cfg;
281
282 DRM_DEBUG_KMS("enable[%d]\n", enable);
283
284 cfg = fimc_read(EXYNOS_CIGCTRL);
285 if (enable)
286 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
287 else
288 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
289
290 fimc_write(cfg, EXYNOS_CIGCTRL);
291}
292
293static void fimc_handle_irq(struct fimc_context *ctx, bool enable,
294 bool overflow, bool level)
295{
296 u32 cfg;
297
298 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
299 enable, overflow, level);
300
301 cfg = fimc_read(EXYNOS_CIGCTRL);
302 if (enable) {
303 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL);
304 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE;
305 if (overflow)
306 cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN;
307 if (level)
308 cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL;
309 } else
310 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE);
311
312 fimc_write(cfg, EXYNOS_CIGCTRL);
313}
314
315static void fimc_clear_irq(struct fimc_context *ctx)
316{
317 u32 cfg;
318
319 cfg = fimc_read(EXYNOS_CIGCTRL);
320 cfg |= EXYNOS_CIGCTRL_IRQ_CLR;
321 fimc_write(cfg, EXYNOS_CIGCTRL);
322}
323
324static bool fimc_check_ovf(struct fimc_context *ctx)
325{
326 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
327 u32 cfg, status, flag;
328
329 status = fimc_read(EXYNOS_CISTATUS);
330 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
331 EXYNOS_CISTATUS_OVFICR;
332
333 DRM_DEBUG_KMS("flag[0x%x]\n", flag);
334
335 if (status & flag) {
336 cfg = fimc_read(EXYNOS_CIWDOFST);
337 cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
338 EXYNOS_CIWDOFST_CLROVFICR);
339
340 fimc_write(cfg, EXYNOS_CIWDOFST);
341
342 cfg = fimc_read(EXYNOS_CIWDOFST);
343 cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
344 EXYNOS_CIWDOFST_CLROVFICR);
345
346 fimc_write(cfg, EXYNOS_CIWDOFST);
347
348 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
349 ctx->id, status);
350 return true;
351 }
352
353 return false;
354}
355
356static bool fimc_check_frame_end(struct fimc_context *ctx)
357{
358 u32 cfg;
359
360 cfg = fimc_read(EXYNOS_CISTATUS);
361
362 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
363
364 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
365 return false;
366
367 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
368 fimc_write(cfg, EXYNOS_CISTATUS);
369
370 return true;
371}
372
373static int fimc_get_buf_id(struct fimc_context *ctx)
374{
375 u32 cfg;
376 int frame_cnt, buf_id;
377
378 cfg = fimc_read(EXYNOS_CISTATUS2);
379 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
380
381 if (frame_cnt == 0)
382 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
383
384 DRM_DEBUG_KMS("present[%d]before[%d]\n",
385 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
386 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
387
388 if (frame_cnt == 0) {
389 DRM_ERROR("failed to get frame count.\n");
390 return -EIO;
391 }
392
393 buf_id = frame_cnt - 1;
394 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
395
396 return buf_id;
397}
398
399static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
400{
401 u32 cfg;
402
403 DRM_DEBUG_KMS("enable[%d]\n", enable);
404
405 cfg = fimc_read(EXYNOS_CIOCTRL);
406 if (enable)
407 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
408 else
409 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
410
411 fimc_write(cfg, EXYNOS_CIOCTRL);
412}
413
414
415static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
416{
417 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
418 u32 cfg;
419
420 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
421
422 /* RGB */
423 cfg = fimc_read(EXYNOS_CISCCTRL);
424 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
425
426 switch (fmt) {
427 case DRM_FORMAT_RGB565:
428 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
429 fimc_write(cfg, EXYNOS_CISCCTRL);
430 return 0;
431 case DRM_FORMAT_RGB888:
432 case DRM_FORMAT_XRGB8888:
433 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
434 fimc_write(cfg, EXYNOS_CISCCTRL);
435 return 0;
436 default:
437 /* bypass */
438 break;
439 }
440
441 /* YUV */
442 cfg = fimc_read(EXYNOS_MSCTRL);
443 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
444 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
445 EXYNOS_MSCTRL_ORDER422_YCBYCR);
446
447 switch (fmt) {
448 case DRM_FORMAT_YUYV:
449 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
450 break;
451 case DRM_FORMAT_YVYU:
452 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
453 break;
454 case DRM_FORMAT_UYVY:
455 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
456 break;
457 case DRM_FORMAT_VYUY:
458 case DRM_FORMAT_YUV444:
459 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
460 break;
461 case DRM_FORMAT_NV21:
462 case DRM_FORMAT_NV61:
463 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
464 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
465 break;
466 case DRM_FORMAT_YUV422:
467 case DRM_FORMAT_YUV420:
468 case DRM_FORMAT_YVU420:
469 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
470 break;
471 case DRM_FORMAT_NV12:
472 case DRM_FORMAT_NV12MT:
473 case DRM_FORMAT_NV16:
474 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
475 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
476 break;
477 default:
478 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
479 return -EINVAL;
480 }
481
482 fimc_write(cfg, EXYNOS_MSCTRL);
483
484 return 0;
485}
486
487static int fimc_src_set_fmt(struct device *dev, u32 fmt)
488{
489 struct fimc_context *ctx = get_fimc_context(dev);
490 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
491 u32 cfg;
492
493 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
494
495 cfg = fimc_read(EXYNOS_MSCTRL);
496 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
497
498 switch (fmt) {
499 case DRM_FORMAT_RGB565:
500 case DRM_FORMAT_RGB888:
501 case DRM_FORMAT_XRGB8888:
502 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
503 break;
504 case DRM_FORMAT_YUV444:
505 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
506 break;
507 case DRM_FORMAT_YUYV:
508 case DRM_FORMAT_YVYU:
509 case DRM_FORMAT_UYVY:
510 case DRM_FORMAT_VYUY:
511 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
512 break;
513 case DRM_FORMAT_NV16:
514 case DRM_FORMAT_NV61:
515 case DRM_FORMAT_YUV422:
516 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
517 break;
518 case DRM_FORMAT_YUV420:
519 case DRM_FORMAT_YVU420:
520 case DRM_FORMAT_NV12:
521 case DRM_FORMAT_NV21:
522 case DRM_FORMAT_NV12MT:
523 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
524 break;
525 default:
526 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
527 return -EINVAL;
528 }
529
530 fimc_write(cfg, EXYNOS_MSCTRL);
531
532 cfg = fimc_read(EXYNOS_CIDMAPARAM);
533 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
534
535 if (fmt == DRM_FORMAT_NV12MT)
536 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
537 else
538 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
539
540 fimc_write(cfg, EXYNOS_CIDMAPARAM);
541
542 return fimc_src_set_fmt_order(ctx, fmt);
543}
544
545static int fimc_src_set_transf(struct device *dev,
546 enum drm_exynos_degree degree,
547 enum drm_exynos_flip flip, bool *swap)
548{
549 struct fimc_context *ctx = get_fimc_context(dev);
550 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
551 u32 cfg1, cfg2;
552
553 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
554
555 cfg1 = fimc_read(EXYNOS_MSCTRL);
556 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
557 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
558
559 cfg2 = fimc_read(EXYNOS_CITRGFMT);
560 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
561
562 switch (degree) {
563 case EXYNOS_DRM_DEGREE_0:
564 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
565 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
566 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
567 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
568 break;
569 case EXYNOS_DRM_DEGREE_90:
570 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
571 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
572 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
573 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
574 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
575 break;
576 case EXYNOS_DRM_DEGREE_180:
577 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
578 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
579 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
580 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
581 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
582 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
583 break;
584 case EXYNOS_DRM_DEGREE_270:
585 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
586 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
587 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
588 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
589 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
590 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
591 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
592 break;
593 default:
594 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
595 return -EINVAL;
596 }
597
598 fimc_write(cfg1, EXYNOS_MSCTRL);
599 fimc_write(cfg2, EXYNOS_CITRGFMT);
600 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
601
602 return 0;
603}
604
605static int fimc_set_window(struct fimc_context *ctx,
606 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
607{
608 u32 cfg, h1, h2, v1, v2;
609
610 /* cropped image */
611 h1 = pos->x;
612 h2 = sz->hsize - pos->w - pos->x;
613 v1 = pos->y;
614 v2 = sz->vsize - pos->h - pos->y;
615
616 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
617 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
618 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
619
620 /*
621 * set window offset 1, 2 size
622 * check figure 43-21 in user manual
623 */
624 cfg = fimc_read(EXYNOS_CIWDOFST);
625 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
626 EXYNOS_CIWDOFST_WINVEROFST_MASK);
627 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
628 EXYNOS_CIWDOFST_WINVEROFST(v1));
629 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
630 fimc_write(cfg, EXYNOS_CIWDOFST);
631
632 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
633 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
634 fimc_write(cfg, EXYNOS_CIWDOFST2);
635
636 return 0;
637}
638
639static int fimc_src_set_size(struct device *dev, int swap,
640 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
641{
642 struct fimc_context *ctx = get_fimc_context(dev);
643 struct drm_exynos_pos img_pos = *pos;
644 struct drm_exynos_sz img_sz = *sz;
645 u32 cfg;
646
647 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
648 swap, sz->hsize, sz->vsize);
649
650 /* original size */
651 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
652 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
653
654 fimc_write(cfg, EXYNOS_ORGISIZE);
655
656 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
657
658 if (swap) {
659 img_pos.w = pos->h;
660 img_pos.h = pos->w;
661 img_sz.hsize = sz->vsize;
662 img_sz.vsize = sz->hsize;
663 }
664
665 /* set input DMA image size */
666 cfg = fimc_read(EXYNOS_CIREAL_ISIZE);
667 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
668 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
669 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
670 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
671 fimc_write(cfg, EXYNOS_CIREAL_ISIZE);
672
673 /*
674 * set input FIFO image size
675 * for now, we support only ITU601 8 bit mode
676 */
677 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
678 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
679 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
680 fimc_write(cfg, EXYNOS_CISRCFMT);
681
682 /* offset Y(RGB), Cb, Cr */
683 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
684 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
685 fimc_write(cfg, EXYNOS_CIIYOFF);
686 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
687 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
688 fimc_write(cfg, EXYNOS_CIICBOFF);
689 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
690 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
691 fimc_write(cfg, EXYNOS_CIICROFF);
692
693 return fimc_set_window(ctx, &img_pos, &img_sz);
694}
695
696static int fimc_src_set_addr(struct device *dev,
697 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
698 enum drm_exynos_ipp_buf_type buf_type)
699{
700 struct fimc_context *ctx = get_fimc_context(dev);
701 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
702 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
703 struct drm_exynos_ipp_property *property;
704 struct drm_exynos_ipp_config *config;
705
706 if (!c_node) {
707 DRM_ERROR("failed to get c_node.\n");
708 return -EINVAL;
709 }
710
711 property = &c_node->property;
712
713 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
714 property->prop_id, buf_id, buf_type);
715
716 if (buf_id > FIMC_MAX_SRC) {
717 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
718 return -ENOMEM;
719 }
720
721 /* address register set */
722 switch (buf_type) {
723 case IPP_BUF_ENQUEUE:
724 config = &property->config[EXYNOS_DRM_OPS_SRC];
725 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
726 EXYNOS_CIIYSA(buf_id));
727
728 if (config->fmt == DRM_FORMAT_YVU420) {
729 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
730 EXYNOS_CIICBSA(buf_id));
731 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
732 EXYNOS_CIICRSA(buf_id));
733 } else {
734 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
735 EXYNOS_CIICBSA(buf_id));
736 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
737 EXYNOS_CIICRSA(buf_id));
738 }
739 break;
740 case IPP_BUF_DEQUEUE:
741 fimc_write(0x0, EXYNOS_CIIYSA(buf_id));
742 fimc_write(0x0, EXYNOS_CIICBSA(buf_id));
743 fimc_write(0x0, EXYNOS_CIICRSA(buf_id));
744 break;
745 default:
746 /* bypass */
747 break;
748 }
749
750 return 0;
751}
752
753static struct exynos_drm_ipp_ops fimc_src_ops = {
754 .set_fmt = fimc_src_set_fmt,
755 .set_transf = fimc_src_set_transf,
756 .set_size = fimc_src_set_size,
757 .set_addr = fimc_src_set_addr,
758};
759
760static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
761{
762 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
763 u32 cfg;
764
765 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
766
767 /* RGB */
768 cfg = fimc_read(EXYNOS_CISCCTRL);
769 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
770
771 switch (fmt) {
772 case DRM_FORMAT_RGB565:
773 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
774 fimc_write(cfg, EXYNOS_CISCCTRL);
775 return 0;
776 case DRM_FORMAT_RGB888:
777 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
778 fimc_write(cfg, EXYNOS_CISCCTRL);
779 return 0;
780 case DRM_FORMAT_XRGB8888:
781 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
782 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
783 fimc_write(cfg, EXYNOS_CISCCTRL);
784 break;
785 default:
786 /* bypass */
787 break;
788 }
789
790 /* YUV */
791 cfg = fimc_read(EXYNOS_CIOCTRL);
792 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
793 EXYNOS_CIOCTRL_ORDER422_MASK |
794 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
795
796 switch (fmt) {
797 case DRM_FORMAT_XRGB8888:
798 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
799 break;
800 case DRM_FORMAT_YUYV:
801 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
802 break;
803 case DRM_FORMAT_YVYU:
804 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
805 break;
806 case DRM_FORMAT_UYVY:
807 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
808 break;
809 case DRM_FORMAT_VYUY:
810 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
811 break;
812 case DRM_FORMAT_NV21:
813 case DRM_FORMAT_NV61:
814 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
815 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
816 break;
817 case DRM_FORMAT_YUV422:
818 case DRM_FORMAT_YUV420:
819 case DRM_FORMAT_YVU420:
820 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
821 break;
822 case DRM_FORMAT_NV12:
823 case DRM_FORMAT_NV12MT:
824 case DRM_FORMAT_NV16:
825 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
826 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
827 break;
828 default:
829 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
830 return -EINVAL;
831 }
832
833 fimc_write(cfg, EXYNOS_CIOCTRL);
834
835 return 0;
836}
837
838static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
839{
840 struct fimc_context *ctx = get_fimc_context(dev);
841 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
842 u32 cfg;
843
844 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
845
846 cfg = fimc_read(EXYNOS_CIEXTEN);
847
848 if (fmt == DRM_FORMAT_AYUV) {
849 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
850 fimc_write(cfg, EXYNOS_CIEXTEN);
851 } else {
852 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
853 fimc_write(cfg, EXYNOS_CIEXTEN);
854
855 cfg = fimc_read(EXYNOS_CITRGFMT);
856 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
857
858 switch (fmt) {
859 case DRM_FORMAT_RGB565:
860 case DRM_FORMAT_RGB888:
861 case DRM_FORMAT_XRGB8888:
862 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
863 break;
864 case DRM_FORMAT_YUYV:
865 case DRM_FORMAT_YVYU:
866 case DRM_FORMAT_UYVY:
867 case DRM_FORMAT_VYUY:
868 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
869 break;
870 case DRM_FORMAT_NV16:
871 case DRM_FORMAT_NV61:
872 case DRM_FORMAT_YUV422:
873 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
874 break;
875 case DRM_FORMAT_YUV420:
876 case DRM_FORMAT_YVU420:
877 case DRM_FORMAT_NV12:
878 case DRM_FORMAT_NV12MT:
879 case DRM_FORMAT_NV21:
880 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
881 break;
882 default:
883 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
884 fmt);
885 return -EINVAL;
886 }
887
888 fimc_write(cfg, EXYNOS_CITRGFMT);
889 }
890
891 cfg = fimc_read(EXYNOS_CIDMAPARAM);
892 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
893
894 if (fmt == DRM_FORMAT_NV12MT)
895 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
896 else
897 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
898
899 fimc_write(cfg, EXYNOS_CIDMAPARAM);
900
901 return fimc_dst_set_fmt_order(ctx, fmt);
902}
903
904static int fimc_dst_set_transf(struct device *dev,
905 enum drm_exynos_degree degree,
906 enum drm_exynos_flip flip, bool *swap)
907{
908 struct fimc_context *ctx = get_fimc_context(dev);
909 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
910 u32 cfg;
911
912 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
913
914 cfg = fimc_read(EXYNOS_CITRGFMT);
915 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
916 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
917
918 switch (degree) {
919 case EXYNOS_DRM_DEGREE_0:
920 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
921 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
922 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
923 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
924 break;
925 case EXYNOS_DRM_DEGREE_90:
926 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
927 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
928 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
929 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
930 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
931 break;
932 case EXYNOS_DRM_DEGREE_180:
933 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
934 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
935 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
936 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
937 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
938 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
939 break;
940 case EXYNOS_DRM_DEGREE_270:
941 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
942 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
943 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
944 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
945 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
946 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
947 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
948 break;
949 default:
950 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
951 return -EINVAL;
952 }
953
954 fimc_write(cfg, EXYNOS_CITRGFMT);
955 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
956
957 return 0;
958}
959
960static int fimc_get_ratio_shift(u32 src, u32 dst, u32 *ratio, u32 *shift)
961{
962 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
963
964 if (src >= dst * 64) {
965 DRM_ERROR("failed to make ratio and shift.\n");
966 return -EINVAL;
967 } else if (src >= dst * 32) {
968 *ratio = 32;
969 *shift = 5;
970 } else if (src >= dst * 16) {
971 *ratio = 16;
972 *shift = 4;
973 } else if (src >= dst * 8) {
974 *ratio = 8;
975 *shift = 3;
976 } else if (src >= dst * 4) {
977 *ratio = 4;
978 *shift = 2;
979 } else if (src >= dst * 2) {
980 *ratio = 2;
981 *shift = 1;
982 } else {
983 *ratio = 1;
984 *shift = 0;
985 }
986
987 return 0;
988}
989
990static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
991 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
992{
993 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
994 u32 cfg, cfg_ext, shfactor;
995 u32 pre_dst_width, pre_dst_height;
996 u32 pre_hratio, hfactor, pre_vratio, vfactor;
997 int ret = 0;
998 u32 src_w, src_h, dst_w, dst_h;
999
1000 cfg_ext = fimc_read(EXYNOS_CITRGFMT);
1001 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
1002 src_w = src->h;
1003 src_h = src->w;
1004 } else {
1005 src_w = src->w;
1006 src_h = src->h;
1007 }
1008
1009 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
1010 dst_w = dst->h;
1011 dst_h = dst->w;
1012 } else {
1013 dst_w = dst->w;
1014 dst_h = dst->h;
1015 }
1016
1017 ret = fimc_get_ratio_shift(src_w, dst_w, &pre_hratio, &hfactor);
1018 if (ret) {
1019 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
1020 return ret;
1021 }
1022
1023 ret = fimc_get_ratio_shift(src_h, dst_h, &pre_vratio, &vfactor);
1024 if (ret) {
1025 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
1026 return ret;
1027 }
1028
1029 pre_dst_width = src_w / pre_hratio;
1030 pre_dst_height = src_h / pre_vratio;
1031 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
1032 pre_dst_width, pre_dst_height);
1033 DRM_DEBUG_KMS("pre_hratio[%d]hfactor[%d]pre_vratio[%d]vfactor[%d]\n",
1034 pre_hratio, hfactor, pre_vratio, vfactor);
1035
1036 sc->hratio = (src_w << 14) / (dst_w << hfactor);
1037 sc->vratio = (src_h << 14) / (dst_h << vfactor);
1038 sc->up_h = (dst_w >= src_w) ? true : false;
1039 sc->up_v = (dst_h >= src_h) ? true : false;
1040 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1041 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1042
1043 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1044 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1045
1046 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1047 EXYNOS_CISCPRERATIO_PREHORRATIO(pre_hratio) |
1048 EXYNOS_CISCPRERATIO_PREVERRATIO(pre_vratio));
1049 fimc_write(cfg, EXYNOS_CISCPRERATIO);
1050
1051 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1052 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1053 fimc_write(cfg, EXYNOS_CISCPREDST);
1054
1055 return ret;
1056}
1057
1058static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1059{
1060 u32 cfg, cfg_ext;
1061
1062 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1063 sc->range, sc->bypass, sc->up_h, sc->up_v);
1064 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1065 sc->hratio, sc->vratio);
1066
1067 cfg = fimc_read(EXYNOS_CISCCTRL);
1068 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1069 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1070 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1071 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1072 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1073 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1074
1075 if (sc->range)
1076 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1077 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1078 if (sc->bypass)
1079 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1080 if (sc->up_h)
1081 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1082 if (sc->up_v)
1083 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1084
1085 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1086 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1087 fimc_write(cfg, EXYNOS_CISCCTRL);
1088
1089 cfg_ext = fimc_read(EXYNOS_CIEXTEN);
1090 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1091 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1092 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1093 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1094 fimc_write(cfg_ext, EXYNOS_CIEXTEN);
1095}
1096
1097static int fimc_dst_set_size(struct device *dev, int swap,
1098 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1099{
1100 struct fimc_context *ctx = get_fimc_context(dev);
1101 struct drm_exynos_pos img_pos = *pos;
1102 struct drm_exynos_sz img_sz = *sz;
1103 u32 cfg;
1104
1105 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1106 swap, sz->hsize, sz->vsize);
1107
1108 /* original size */
1109 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1110 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1111
1112 fimc_write(cfg, EXYNOS_ORGOSIZE);
1113
1114 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1115
1116 /* CSC ITU */
1117 cfg = fimc_read(EXYNOS_CIGCTRL);
1118 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1119
1120 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1121 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1122 else
1123 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1124
1125 fimc_write(cfg, EXYNOS_CIGCTRL);
1126
1127 if (swap) {
1128 img_pos.w = pos->h;
1129 img_pos.h = pos->w;
1130 img_sz.hsize = sz->vsize;
1131 img_sz.vsize = sz->hsize;
1132 }
1133
1134 /* target image size */
1135 cfg = fimc_read(EXYNOS_CITRGFMT);
1136 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1137 EXYNOS_CITRGFMT_TARGETV_MASK);
1138 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1139 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1140 fimc_write(cfg, EXYNOS_CITRGFMT);
1141
1142 /* target area */
1143 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1144 fimc_write(cfg, EXYNOS_CITAREA);
1145
1146 /* offset Y(RGB), Cb, Cr */
1147 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1148 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1149 fimc_write(cfg, EXYNOS_CIOYOFF);
1150 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1151 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1152 fimc_write(cfg, EXYNOS_CIOCBOFF);
1153 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1154 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1155 fimc_write(cfg, EXYNOS_CIOCROFF);
1156
1157 return 0;
1158}
1159
1160static int fimc_dst_get_buf_seq(struct fimc_context *ctx)
1161{
1162 u32 cfg, i, buf_num = 0;
1163 u32 mask = 0x00000001;
1164
1165 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1166
1167 for (i = 0; i < FIMC_REG_SZ; i++)
1168 if (cfg & (mask << i))
1169 buf_num++;
1170
1171 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1172
1173 return buf_num;
1174}
1175
1176static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1177 enum drm_exynos_ipp_buf_type buf_type)
1178{
1179 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1180 bool enable;
1181 u32 cfg;
1182 u32 mask = 0x00000001 << buf_id;
1183 int ret = 0;
1184
1185 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1186
1187 mutex_lock(&ctx->lock);
1188
1189 /* mask register set */
1190 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1191
1192 switch (buf_type) {
1193 case IPP_BUF_ENQUEUE:
1194 enable = true;
1195 break;
1196 case IPP_BUF_DEQUEUE:
1197 enable = false;
1198 break;
1199 default:
1200 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1201 ret = -EINVAL;
1202 goto err_unlock;
1203 }
1204
1205 /* sequence id */
1206 cfg &= ~mask;
1207 cfg |= (enable << buf_id);
1208 fimc_write(cfg, EXYNOS_CIFCNTSEQ);
1209
1210 /* interrupt enable */
1211 if (buf_type == IPP_BUF_ENQUEUE &&
1212 fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START)
1213 fimc_handle_irq(ctx, true, false, true);
1214
1215 /* interrupt disable */
1216 if (buf_type == IPP_BUF_DEQUEUE &&
1217 fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP)
1218 fimc_handle_irq(ctx, false, false, true);
1219
1220err_unlock:
1221 mutex_unlock(&ctx->lock);
1222 return ret;
1223}
1224
1225static int fimc_dst_set_addr(struct device *dev,
1226 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1227 enum drm_exynos_ipp_buf_type buf_type)
1228{
1229 struct fimc_context *ctx = get_fimc_context(dev);
1230 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1231 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1232 struct drm_exynos_ipp_property *property;
1233 struct drm_exynos_ipp_config *config;
1234
1235 if (!c_node) {
1236 DRM_ERROR("failed to get c_node.\n");
1237 return -EINVAL;
1238 }
1239
1240 property = &c_node->property;
1241
1242 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1243 property->prop_id, buf_id, buf_type);
1244
1245 if (buf_id > FIMC_MAX_DST) {
1246 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1247 return -ENOMEM;
1248 }
1249
1250 /* address register set */
1251 switch (buf_type) {
1252 case IPP_BUF_ENQUEUE:
1253 config = &property->config[EXYNOS_DRM_OPS_DST];
1254
1255 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1256 EXYNOS_CIOYSA(buf_id));
1257
1258 if (config->fmt == DRM_FORMAT_YVU420) {
1259 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1260 EXYNOS_CIOCBSA(buf_id));
1261 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1262 EXYNOS_CIOCRSA(buf_id));
1263 } else {
1264 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1265 EXYNOS_CIOCBSA(buf_id));
1266 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1267 EXYNOS_CIOCRSA(buf_id));
1268 }
1269 break;
1270 case IPP_BUF_DEQUEUE:
1271 fimc_write(0x0, EXYNOS_CIOYSA(buf_id));
1272 fimc_write(0x0, EXYNOS_CIOCBSA(buf_id));
1273 fimc_write(0x0, EXYNOS_CIOCRSA(buf_id));
1274 break;
1275 default:
1276 /* bypass */
1277 break;
1278 }
1279
1280 return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1281}
1282
1283static struct exynos_drm_ipp_ops fimc_dst_ops = {
1284 .set_fmt = fimc_dst_set_fmt,
1285 .set_transf = fimc_dst_set_transf,
1286 .set_size = fimc_dst_set_size,
1287 .set_addr = fimc_dst_set_addr,
1288};
1289
1290static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1291{
1292 DRM_DEBUG_KMS("enable[%d]\n", enable);
1293
1294 if (enable) {
1295 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1296 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1297 ctx->suspended = false;
1298 } else {
1299 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1300 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1301 ctx->suspended = true;
1302 }
1303
1304 return 0;
1305}
1306
1307static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1308{
1309 struct fimc_context *ctx = dev_id;
1310 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1311 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1312 struct drm_exynos_ipp_event_work *event_work =
1313 c_node->event_work;
1314 int buf_id;
1315
1316 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1317
1318 fimc_clear_irq(ctx);
1319 if (fimc_check_ovf(ctx))
1320 return IRQ_NONE;
1321
1322 if (!fimc_check_frame_end(ctx))
1323 return IRQ_NONE;
1324
1325 buf_id = fimc_get_buf_id(ctx);
1326 if (buf_id < 0)
1327 return IRQ_HANDLED;
1328
1329 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1330
1331 if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1332 DRM_ERROR("failed to dequeue.\n");
1333 return IRQ_HANDLED;
1334 }
1335
1336 event_work->ippdrv = ippdrv;
1337 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1338 queue_work(ippdrv->event_workq, (struct work_struct *)event_work);
1339
1340 return IRQ_HANDLED;
1341}
1342
1343static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1344{
1345 struct drm_exynos_ipp_prop_list *prop_list;
1346
1347 prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
1348 if (!prop_list)
1349 return -ENOMEM;
1350
1351 prop_list->version = 1;
1352 prop_list->writeback = 1;
1353 prop_list->refresh_min = FIMC_REFRESH_MIN;
1354 prop_list->refresh_max = FIMC_REFRESH_MAX;
1355 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1356 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1357 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1358 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1359 (1 << EXYNOS_DRM_DEGREE_90) |
1360 (1 << EXYNOS_DRM_DEGREE_180) |
1361 (1 << EXYNOS_DRM_DEGREE_270);
1362 prop_list->csc = 1;
1363 prop_list->crop = 1;
1364 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1365 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1366 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1367 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1368 prop_list->scale = 1;
1369 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1370 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1371 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1372 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1373
1374 ippdrv->prop_list = prop_list;
1375
1376 return 0;
1377}
1378
1379static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1380{
1381 switch (flip) {
1382 case EXYNOS_DRM_FLIP_NONE:
1383 case EXYNOS_DRM_FLIP_VERTICAL:
1384 case EXYNOS_DRM_FLIP_HORIZONTAL:
1385 case EXYNOS_DRM_FLIP_BOTH:
1386 return true;
1387 default:
1388 DRM_DEBUG_KMS("invalid flip\n");
1389 return false;
1390 }
1391}
1392
1393static int fimc_ippdrv_check_property(struct device *dev,
1394 struct drm_exynos_ipp_property *property)
1395{
1396 struct fimc_context *ctx = get_fimc_context(dev);
1397 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1398 struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
1399 struct drm_exynos_ipp_config *config;
1400 struct drm_exynos_pos *pos;
1401 struct drm_exynos_sz *sz;
1402 bool swap;
1403 int i;
1404
1405 for_each_ipp_ops(i) {
1406 if ((i == EXYNOS_DRM_OPS_SRC) &&
1407 (property->cmd == IPP_CMD_WB))
1408 continue;
1409
1410 config = &property->config[i];
1411 pos = &config->pos;
1412 sz = &config->sz;
1413
1414 /* check for flip */
1415 if (!fimc_check_drm_flip(config->flip)) {
1416 DRM_ERROR("invalid flip.\n");
1417 goto err_property;
1418 }
1419
1420 /* check for degree */
1421 switch (config->degree) {
1422 case EXYNOS_DRM_DEGREE_90:
1423 case EXYNOS_DRM_DEGREE_270:
1424 swap = true;
1425 break;
1426 case EXYNOS_DRM_DEGREE_0:
1427 case EXYNOS_DRM_DEGREE_180:
1428 swap = false;
1429 break;
1430 default:
1431 DRM_ERROR("invalid degree.\n");
1432 goto err_property;
1433 }
1434
1435 /* check for buffer bound */
1436 if ((pos->x + pos->w > sz->hsize) ||
1437 (pos->y + pos->h > sz->vsize)) {
1438 DRM_ERROR("out of buf bound.\n");
1439 goto err_property;
1440 }
1441
1442 /* check for crop */
1443 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1444 if (swap) {
1445 if ((pos->h < pp->crop_min.hsize) ||
1446 (sz->vsize > pp->crop_max.hsize) ||
1447 (pos->w < pp->crop_min.vsize) ||
1448 (sz->hsize > pp->crop_max.vsize)) {
1449 DRM_ERROR("out of crop size.\n");
1450 goto err_property;
1451 }
1452 } else {
1453 if ((pos->w < pp->crop_min.hsize) ||
1454 (sz->hsize > pp->crop_max.hsize) ||
1455 (pos->h < pp->crop_min.vsize) ||
1456 (sz->vsize > pp->crop_max.vsize)) {
1457 DRM_ERROR("out of crop size.\n");
1458 goto err_property;
1459 }
1460 }
1461 }
1462
1463 /* check for scale */
1464 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1465 if (swap) {
1466 if ((pos->h < pp->scale_min.hsize) ||
1467 (sz->vsize > pp->scale_max.hsize) ||
1468 (pos->w < pp->scale_min.vsize) ||
1469 (sz->hsize > pp->scale_max.vsize)) {
1470 DRM_ERROR("out of scale size.\n");
1471 goto err_property;
1472 }
1473 } else {
1474 if ((pos->w < pp->scale_min.hsize) ||
1475 (sz->hsize > pp->scale_max.hsize) ||
1476 (pos->h < pp->scale_min.vsize) ||
1477 (sz->vsize > pp->scale_max.vsize)) {
1478 DRM_ERROR("out of scale size.\n");
1479 goto err_property;
1480 }
1481 }
1482 }
1483 }
1484
1485 return 0;
1486
1487err_property:
1488 for_each_ipp_ops(i) {
1489 if ((i == EXYNOS_DRM_OPS_SRC) &&
1490 (property->cmd == IPP_CMD_WB))
1491 continue;
1492
1493 config = &property->config[i];
1494 pos = &config->pos;
1495 sz = &config->sz;
1496
1497 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1498 i ? "dst" : "src", config->flip, config->degree,
1499 pos->x, pos->y, pos->w, pos->h,
1500 sz->hsize, sz->vsize);
1501 }
1502
1503 return -EINVAL;
1504}
1505
1506static void fimc_clear_addr(struct fimc_context *ctx)
1507{
1508 int i;
1509
1510 for (i = 0; i < FIMC_MAX_SRC; i++) {
1511 fimc_write(0, EXYNOS_CIIYSA(i));
1512 fimc_write(0, EXYNOS_CIICBSA(i));
1513 fimc_write(0, EXYNOS_CIICRSA(i));
1514 }
1515
1516 for (i = 0; i < FIMC_MAX_DST; i++) {
1517 fimc_write(0, EXYNOS_CIOYSA(i));
1518 fimc_write(0, EXYNOS_CIOCBSA(i));
1519 fimc_write(0, EXYNOS_CIOCRSA(i));
1520 }
1521}
1522
1523static int fimc_ippdrv_reset(struct device *dev)
1524{
1525 struct fimc_context *ctx = get_fimc_context(dev);
1526
1527 /* reset h/w block */
1528 fimc_sw_reset(ctx);
1529
1530 /* reset scaler capability */
1531 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1532
1533 fimc_clear_addr(ctx);
1534
1535 return 0;
1536}
1537
1538static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1539{
1540 struct fimc_context *ctx = get_fimc_context(dev);
1541 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1542 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1543 struct drm_exynos_ipp_property *property;
1544 struct drm_exynos_ipp_config *config;
1545 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1546 struct drm_exynos_ipp_set_wb set_wb;
1547 int ret, i;
1548 u32 cfg0, cfg1;
1549
1550 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1551
1552 if (!c_node) {
1553 DRM_ERROR("failed to get c_node.\n");
1554 return -EINVAL;
1555 }
1556
1557 property = &c_node->property;
1558
1559 fimc_handle_irq(ctx, true, false, true);
1560
1561 for_each_ipp_ops(i) {
1562 config = &property->config[i];
1563 img_pos[i] = config->pos;
1564 }
1565
1566 ret = fimc_set_prescaler(ctx, &ctx->sc,
1567 &img_pos[EXYNOS_DRM_OPS_SRC],
1568 &img_pos[EXYNOS_DRM_OPS_DST]);
1569 if (ret) {
1570 dev_err(dev, "failed to set precalser.\n");
1571 return ret;
1572 }
1573
1574 /* If set ture, we can save jpeg about screen */
1575 fimc_handle_jpeg(ctx, false);
1576 fimc_set_scaler(ctx, &ctx->sc);
1577 fimc_set_polarity(ctx, &ctx->pol);
1578
1579 switch (cmd) {
1580 case IPP_CMD_M2M:
1581 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1582 fimc_handle_lastend(ctx, false);
1583
1584 /* setup dma */
1585 cfg0 = fimc_read(EXYNOS_MSCTRL);
1586 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1587 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1588 fimc_write(cfg0, EXYNOS_MSCTRL);
1589 break;
1590 case IPP_CMD_WB:
1591 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1592 fimc_handle_lastend(ctx, true);
1593
1594 /* setup FIMD */
1595 ret = fimc_set_camblk_fimd0_wb(ctx);
1596 if (ret < 0) {
1597 dev_err(dev, "camblk setup failed.\n");
1598 return ret;
1599 }
1600
1601 set_wb.enable = 1;
1602 set_wb.refresh = property->refresh_rate;
1603 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1604 break;
1605 case IPP_CMD_OUTPUT:
1606 default:
1607 ret = -EINVAL;
1608 dev_err(dev, "invalid operations.\n");
1609 return ret;
1610 }
1611
1612 /* Reset status */
1613 fimc_write(0x0, EXYNOS_CISTATUS);
1614
1615 cfg0 = fimc_read(EXYNOS_CIIMGCPT);
1616 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1617 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1618
1619 /* Scaler */
1620 cfg1 = fimc_read(EXYNOS_CISCCTRL);
1621 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1622 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1623 EXYNOS_CISCCTRL_SCALERSTART);
1624
1625 fimc_write(cfg1, EXYNOS_CISCCTRL);
1626
1627 /* Enable image capture*/
1628 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1629 fimc_write(cfg0, EXYNOS_CIIMGCPT);
1630
1631 /* Disable frame end irq */
1632 cfg0 = fimc_read(EXYNOS_CIGCTRL);
1633 cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1634 fimc_write(cfg0, EXYNOS_CIGCTRL);
1635
1636 cfg0 = fimc_read(EXYNOS_CIOCTRL);
1637 cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK;
1638 fimc_write(cfg0, EXYNOS_CIOCTRL);
1639
1640 if (cmd == IPP_CMD_M2M) {
1641 cfg0 = fimc_read(EXYNOS_MSCTRL);
1642 cfg0 |= EXYNOS_MSCTRL_ENVID;
1643 fimc_write(cfg0, EXYNOS_MSCTRL);
1644
1645 cfg0 = fimc_read(EXYNOS_MSCTRL);
1646 cfg0 |= EXYNOS_MSCTRL_ENVID;
1647 fimc_write(cfg0, EXYNOS_MSCTRL);
1648 }
1649
1650 return 0;
1651}
1652
1653static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1654{
1655 struct fimc_context *ctx = get_fimc_context(dev);
1656 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1657 u32 cfg;
1658
1659 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1660
1661 switch (cmd) {
1662 case IPP_CMD_M2M:
1663 /* Source clear */
1664 cfg = fimc_read(EXYNOS_MSCTRL);
1665 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1666 cfg &= ~EXYNOS_MSCTRL_ENVID;
1667 fimc_write(cfg, EXYNOS_MSCTRL);
1668 break;
1669 case IPP_CMD_WB:
1670 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1671 break;
1672 case IPP_CMD_OUTPUT:
1673 default:
1674 dev_err(dev, "invalid operations.\n");
1675 break;
1676 }
1677
1678 fimc_handle_irq(ctx, false, false, true);
1679
1680 /* reset sequence */
1681 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
1682
1683 /* Scaler disable */
1684 cfg = fimc_read(EXYNOS_CISCCTRL);
1685 cfg &= ~EXYNOS_CISCCTRL_SCALERSTART;
1686 fimc_write(cfg, EXYNOS_CISCCTRL);
1687
1688 /* Disable image capture */
1689 cfg = fimc_read(EXYNOS_CIIMGCPT);
1690 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1691 fimc_write(cfg, EXYNOS_CIIMGCPT);
1692
1693 /* Enable frame end irq */
1694 cfg = fimc_read(EXYNOS_CIGCTRL);
1695 cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1696 fimc_write(cfg, EXYNOS_CIGCTRL);
1697}
1698
1699static void fimc_put_clocks(struct fimc_context *ctx)
1700{
1701 int i;
1702
1703 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1704 if (IS_ERR(ctx->clocks[i]))
1705 continue;
1706 clk_put(ctx->clocks[i]);
1707 ctx->clocks[i] = ERR_PTR(-EINVAL);
1708 }
1709}
1710
1711static int fimc_setup_clocks(struct fimc_context *ctx)
1712{
1713 struct device *fimc_dev = ctx->ippdrv.dev;
1714 struct device *dev;
1715 int ret, i;
1716
1717 for (i = 0; i < FIMC_CLKS_MAX; i++)
1718 ctx->clocks[i] = ERR_PTR(-EINVAL);
1719
1720 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1721 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1722 dev = fimc_dev->parent;
1723 else
1724 dev = fimc_dev;
1725
1726 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1727 if (IS_ERR(ctx->clocks[i])) {
1728 if (i >= FIMC_CLK_MUX)
1729 break;
1730 ret = PTR_ERR(ctx->clocks[i]);
1731 dev_err(fimc_dev, "failed to get clock: %s\n",
1732 fimc_clock_names[i]);
1733 goto e_clk_free;
1734 }
1735 }
1736
1737 /* Optional FIMC LCLK parent clock setting */
1738 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1739 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1740 ctx->clocks[FIMC_CLK_PARENT]);
1741 if (ret < 0) {
1742 dev_err(fimc_dev, "failed to set parent.\n");
1743 goto e_clk_free;
1744 }
1745 }
1746
1747 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1748 if (ret < 0)
1749 goto e_clk_free;
1750
1751 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1752 if (!ret)
1753 return ret;
1754e_clk_free:
1755 fimc_put_clocks(ctx);
1756 return ret;
1757}
1758
1759static int fimc_parse_dt(struct fimc_context *ctx)
1760{
1761 struct device_node *node = ctx->ippdrv.dev->of_node;
1762
1763 /* Handle only devices that support the LCD Writeback data path */
1764 if (!of_property_read_bool(node, "samsung,lcd-wb"))
1765 return -ENODEV;
1766
1767 if (of_property_read_u32(node, "clock-frequency",
1768 &ctx->clk_frequency))
1769 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1770
1771 ctx->id = of_alias_get_id(node, "fimc");
1772
1773 if (ctx->id < 0) {
1774 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1775 return -EINVAL;
1776 }
1777
1778 return 0;
1779}
1780
1781static int fimc_probe(struct platform_device *pdev)
1782{
1783 struct device *dev = &pdev->dev;
1784 struct fimc_context *ctx;
1785 struct resource *res;
1786 struct exynos_drm_ippdrv *ippdrv;
1787 int ret;
1788
1789 if (!dev->of_node) {
1790 dev_err(dev, "device tree node not found.\n");
1791 return -ENODEV;
1792 }
1793
1794 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1795 if (!ctx)
1796 return -ENOMEM;
1797
1798 ctx->ippdrv.dev = dev;
1799
1800 ret = fimc_parse_dt(ctx);
1801 if (ret < 0)
1802 return ret;
1803
1804 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1805 "samsung,sysreg");
1806 if (IS_ERR(ctx->sysreg)) {
1807 dev_err(dev, "syscon regmap lookup failed.\n");
1808 return PTR_ERR(ctx->sysreg);
1809 }
1810
1811 /* resource memory */
1812 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1813 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1814 if (IS_ERR(ctx->regs))
1815 return PTR_ERR(ctx->regs);
1816
1817 /* resource irq */
1818 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1819 if (!res) {
1820 dev_err(dev, "failed to request irq resource.\n");
1821 return -ENOENT;
1822 }
1823
1824 ctx->irq = res->start;
1825 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1826 IRQF_ONESHOT, "drm_fimc", ctx);
1827 if (ret < 0) {
1828 dev_err(dev, "failed to request irq.\n");
1829 return ret;
1830 }
1831
1832 ret = fimc_setup_clocks(ctx);
1833 if (ret < 0)
1834 return ret;
1835
1836 ippdrv = &ctx->ippdrv;
1837 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1838 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1839 ippdrv->check_property = fimc_ippdrv_check_property;
1840 ippdrv->reset = fimc_ippdrv_reset;
1841 ippdrv->start = fimc_ippdrv_start;
1842 ippdrv->stop = fimc_ippdrv_stop;
1843 ret = fimc_init_prop_list(ippdrv);
1844 if (ret < 0) {
1845 dev_err(dev, "failed to init property list.\n");
1846 goto err_put_clk;
1847 }
1848
1849 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1850
1851 mutex_init(&ctx->lock);
1852 platform_set_drvdata(pdev, ctx);
1853
1854 pm_runtime_set_active(dev);
1855 pm_runtime_enable(dev);
1856
1857 ret = exynos_drm_ippdrv_register(ippdrv);
1858 if (ret < 0) {
1859 dev_err(dev, "failed to register drm fimc device.\n");
1860 goto err_pm_dis;
1861 }
1862
1863 dev_info(dev, "drm fimc registered successfully.\n");
1864
1865 return 0;
1866
1867err_pm_dis:
1868 pm_runtime_disable(dev);
1869err_put_clk:
1870 fimc_put_clocks(ctx);
1871
1872 return ret;
1873}
1874
1875static int fimc_remove(struct platform_device *pdev)
1876{
1877 struct device *dev = &pdev->dev;
1878 struct fimc_context *ctx = get_fimc_context(dev);
1879 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1880
1881 exynos_drm_ippdrv_unregister(ippdrv);
1882 mutex_destroy(&ctx->lock);
1883
1884 fimc_put_clocks(ctx);
1885 pm_runtime_set_suspended(dev);
1886 pm_runtime_disable(dev);
1887
1888 return 0;
1889}
1890
1891#ifdef CONFIG_PM_SLEEP
1892static int fimc_suspend(struct device *dev)
1893{
1894 struct fimc_context *ctx = get_fimc_context(dev);
1895
1896 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1897
1898 if (pm_runtime_suspended(dev))
1899 return 0;
1900
1901 return fimc_clk_ctrl(ctx, false);
1902}
1903
1904static int fimc_resume(struct device *dev)
1905{
1906 struct fimc_context *ctx = get_fimc_context(dev);
1907
1908 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1909
1910 if (!pm_runtime_suspended(dev))
1911 return fimc_clk_ctrl(ctx, true);
1912
1913 return 0;
1914}
1915#endif
1916
1917#ifdef CONFIG_PM_RUNTIME
1918static int fimc_runtime_suspend(struct device *dev)
1919{
1920 struct fimc_context *ctx = get_fimc_context(dev);
1921
1922 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1923
1924 return fimc_clk_ctrl(ctx, false);
1925}
1926
1927static int fimc_runtime_resume(struct device *dev)
1928{
1929 struct fimc_context *ctx = get_fimc_context(dev);
1930
1931 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1932
1933 return fimc_clk_ctrl(ctx, true);
1934}
1935#endif
1936
1937static const struct dev_pm_ops fimc_pm_ops = {
1938 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1939 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1940};
1941
1942static const struct of_device_id fimc_of_match[] = {
1943 { .compatible = "samsung,exynos4210-fimc" },
1944 { .compatible = "samsung,exynos4212-fimc" },
1945 { },
1946};
1947
1948struct platform_driver fimc_driver = {
1949 .probe = fimc_probe,
1950 .remove = fimc_remove,
1951 .driver = {
1952 .of_match_table = fimc_of_match,
1953 .name = "exynos-drm-fimc",
1954 .owner = THIS_MODULE,
1955 .pm = &fimc_pm_ops,
1956 },
1957};
1958