Loading...
Note: File does not exist in v3.15.
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/irq.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#include "amdgpu_ih.h"
34#include "atom.h"
35#include "amdgpu_connectors.h"
36
37#include <linux/pm_runtime.h>
38
39#define AMDGPU_WAIT_IDLE_TIMEOUT 200
40
41/*
42 * Handle hotplug events outside the interrupt handler proper.
43 */
44/**
45 * amdgpu_hotplug_work_func - display hotplug work handler
46 *
47 * @work: work struct
48 *
49 * This is the hot plug event work handler (all asics).
50 * The work gets scheduled from the irq handler if there
51 * was a hot plug interrupt. It walks the connector table
52 * and calls the hotplug handler for each one, then sends
53 * a drm hotplug event to alert userspace.
54 */
55static void amdgpu_hotplug_work_func(struct work_struct *work)
56{
57 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
58 hotplug_work);
59 struct drm_device *dev = adev->ddev;
60 struct drm_mode_config *mode_config = &dev->mode_config;
61 struct drm_connector *connector;
62
63 mutex_lock(&mode_config->mutex);
64 if (mode_config->num_connector) {
65 list_for_each_entry(connector, &mode_config->connector_list, head)
66 amdgpu_connector_hotplug(connector);
67 }
68 mutex_unlock(&mode_config->mutex);
69 /* Just fire off a uevent and let userspace tell us what to do */
70 drm_helper_hpd_irq_event(dev);
71}
72
73/**
74 * amdgpu_irq_reset_work_func - execute gpu reset
75 *
76 * @work: work struct
77 *
78 * Execute scheduled gpu reset (cayman+).
79 * This function is called when the irq handler
80 * thinks we need a gpu reset.
81 */
82static void amdgpu_irq_reset_work_func(struct work_struct *work)
83{
84 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
85 reset_work);
86
87 amdgpu_gpu_reset(adev);
88}
89
90/* Disable *all* interrupts */
91static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
92{
93 unsigned long irqflags;
94 unsigned i, j;
95 int r;
96
97 spin_lock_irqsave(&adev->irq.lock, irqflags);
98 for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
99 struct amdgpu_irq_src *src = adev->irq.sources[i];
100
101 if (!src || !src->funcs->set || !src->num_types)
102 continue;
103
104 for (j = 0; j < src->num_types; ++j) {
105 atomic_set(&src->enabled_types[j], 0);
106 r = src->funcs->set(adev, src, j,
107 AMDGPU_IRQ_STATE_DISABLE);
108 if (r)
109 DRM_ERROR("error disabling interrupt (%d)\n",
110 r);
111 }
112 }
113 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
114}
115
116/**
117 * amdgpu_irq_preinstall - drm irq preinstall callback
118 *
119 * @dev: drm dev pointer
120 *
121 * Gets the hw ready to enable irqs (all asics).
122 * This function disables all interrupt sources on the GPU.
123 */
124void amdgpu_irq_preinstall(struct drm_device *dev)
125{
126 struct amdgpu_device *adev = dev->dev_private;
127
128 /* Disable *all* interrupts */
129 amdgpu_irq_disable_all(adev);
130 /* Clear bits */
131 amdgpu_ih_process(adev);
132}
133
134/**
135 * amdgpu_irq_postinstall - drm irq preinstall callback
136 *
137 * @dev: drm dev pointer
138 *
139 * Handles stuff to be done after enabling irqs (all asics).
140 * Returns 0 on success.
141 */
142int amdgpu_irq_postinstall(struct drm_device *dev)
143{
144 dev->max_vblank_count = 0x00ffffff;
145 return 0;
146}
147
148/**
149 * amdgpu_irq_uninstall - drm irq uninstall callback
150 *
151 * @dev: drm dev pointer
152 *
153 * This function disables all interrupt sources on the GPU (all asics).
154 */
155void amdgpu_irq_uninstall(struct drm_device *dev)
156{
157 struct amdgpu_device *adev = dev->dev_private;
158
159 if (adev == NULL) {
160 return;
161 }
162 amdgpu_irq_disable_all(adev);
163}
164
165/**
166 * amdgpu_irq_handler - irq handler
167 *
168 * @int irq, void *arg: args
169 *
170 * This is the irq handler for the amdgpu driver (all asics).
171 */
172irqreturn_t amdgpu_irq_handler(int irq, void *arg)
173{
174 struct drm_device *dev = (struct drm_device *) arg;
175 struct amdgpu_device *adev = dev->dev_private;
176 irqreturn_t ret;
177
178 ret = amdgpu_ih_process(adev);
179 if (ret == IRQ_HANDLED)
180 pm_runtime_mark_last_busy(dev->dev);
181 return ret;
182}
183
184/**
185 * amdgpu_msi_ok - asic specific msi checks
186 *
187 * @adev: amdgpu device pointer
188 *
189 * Handles asic specific MSI checks to determine if
190 * MSIs should be enabled on a particular chip (all asics).
191 * Returns true if MSIs should be enabled, false if MSIs
192 * should not be enabled.
193 */
194static bool amdgpu_msi_ok(struct amdgpu_device *adev)
195{
196 /* force MSI on */
197 if (amdgpu_msi == 1)
198 return true;
199 else if (amdgpu_msi == 0)
200 return false;
201
202 return true;
203}
204
205/**
206 * amdgpu_irq_init - init driver interrupt info
207 *
208 * @adev: amdgpu device pointer
209 *
210 * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
211 * Returns 0 for success, error for failure.
212 */
213int amdgpu_irq_init(struct amdgpu_device *adev)
214{
215 int r = 0;
216
217 spin_lock_init(&adev->irq.lock);
218 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
219 if (r) {
220 return r;
221 }
222 adev->ddev->vblank_disable_allowed = true;
223
224 /* enable msi */
225 adev->irq.msi_enabled = false;
226
227 if (amdgpu_msi_ok(adev)) {
228 int ret = pci_enable_msi(adev->pdev);
229 if (!ret) {
230 adev->irq.msi_enabled = true;
231 dev_info(adev->dev, "amdgpu: using MSI.\n");
232 }
233 }
234
235 INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
236 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
237
238 adev->irq.installed = true;
239 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
240 if (r) {
241 adev->irq.installed = false;
242 flush_work(&adev->hotplug_work);
243 return r;
244 }
245
246 DRM_INFO("amdgpu: irq initialized.\n");
247 return 0;
248}
249
250/**
251 * amdgpu_irq_fini - tear down driver interrupt info
252 *
253 * @adev: amdgpu device pointer
254 *
255 * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
256 */
257void amdgpu_irq_fini(struct amdgpu_device *adev)
258{
259 unsigned i;
260
261 drm_vblank_cleanup(adev->ddev);
262 if (adev->irq.installed) {
263 drm_irq_uninstall(adev->ddev);
264 adev->irq.installed = false;
265 if (adev->irq.msi_enabled)
266 pci_disable_msi(adev->pdev);
267 flush_work(&adev->hotplug_work);
268 }
269
270 for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
271 struct amdgpu_irq_src *src = adev->irq.sources[i];
272
273 if (!src)
274 continue;
275
276 kfree(src->enabled_types);
277 src->enabled_types = NULL;
278 if (src->data) {
279 kfree(src->data);
280 kfree(src);
281 adev->irq.sources[i] = NULL;
282 }
283 }
284}
285
286/**
287 * amdgpu_irq_add_id - register irq source
288 *
289 * @adev: amdgpu device pointer
290 * @src_id: source id for this source
291 * @source: irq source
292 *
293 */
294int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
295 struct amdgpu_irq_src *source)
296{
297 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
298 return -EINVAL;
299
300 if (adev->irq.sources[src_id] != NULL)
301 return -EINVAL;
302
303 if (!source->funcs)
304 return -EINVAL;
305
306 if (source->num_types && !source->enabled_types) {
307 atomic_t *types;
308
309 types = kcalloc(source->num_types, sizeof(atomic_t),
310 GFP_KERNEL);
311 if (!types)
312 return -ENOMEM;
313
314 source->enabled_types = types;
315 }
316
317 adev->irq.sources[src_id] = source;
318
319 return 0;
320}
321
322/**
323 * amdgpu_irq_dispatch - dispatch irq to IP blocks
324 *
325 * @adev: amdgpu device pointer
326 * @entry: interrupt vector
327 *
328 * Dispatches the irq to the different IP blocks
329 */
330void amdgpu_irq_dispatch(struct amdgpu_device *adev,
331 struct amdgpu_iv_entry *entry)
332{
333 unsigned src_id = entry->src_id;
334 struct amdgpu_irq_src *src;
335 int r;
336
337 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
338 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
339 return;
340 }
341
342 if (adev->irq.virq[src_id]) {
343 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
344 } else {
345 src = adev->irq.sources[src_id];
346 if (!src) {
347 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
348 return;
349 }
350
351 r = src->funcs->process(adev, src, entry);
352 if (r)
353 DRM_ERROR("error processing interrupt (%d)\n", r);
354 }
355}
356
357/**
358 * amdgpu_irq_update - update hw interrupt state
359 *
360 * @adev: amdgpu device pointer
361 * @src: interrupt src you want to enable
362 * @type: type of interrupt you want to update
363 *
364 * Updates the interrupt state for a specific src (all asics).
365 */
366int amdgpu_irq_update(struct amdgpu_device *adev,
367 struct amdgpu_irq_src *src, unsigned type)
368{
369 unsigned long irqflags;
370 enum amdgpu_interrupt_state state;
371 int r;
372
373 spin_lock_irqsave(&adev->irq.lock, irqflags);
374
375 /* we need to determine after taking the lock, otherwise
376 we might disable just enabled interrupts again */
377 if (amdgpu_irq_enabled(adev, src, type))
378 state = AMDGPU_IRQ_STATE_ENABLE;
379 else
380 state = AMDGPU_IRQ_STATE_DISABLE;
381
382 r = src->funcs->set(adev, src, type, state);
383 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
384 return r;
385}
386
387/**
388 * amdgpu_irq_get - enable interrupt
389 *
390 * @adev: amdgpu device pointer
391 * @src: interrupt src you want to enable
392 * @type: type of interrupt you want to enable
393 *
394 * Enables the interrupt type for a specific src (all asics).
395 */
396int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
397 unsigned type)
398{
399 if (!adev->ddev->irq_enabled)
400 return -ENOENT;
401
402 if (type >= src->num_types)
403 return -EINVAL;
404
405 if (!src->enabled_types || !src->funcs->set)
406 return -EINVAL;
407
408 if (atomic_inc_return(&src->enabled_types[type]) == 1)
409 return amdgpu_irq_update(adev, src, type);
410
411 return 0;
412}
413
414bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
415 struct amdgpu_irq_src *src,
416 unsigned type)
417{
418 if ((type >= src->num_types) || !src->enabled_types)
419 return false;
420 return atomic_inc_return(&src->enabled_types[type]) == 1;
421}
422
423/**
424 * amdgpu_irq_put - disable interrupt
425 *
426 * @adev: amdgpu device pointer
427 * @src: interrupt src you want to disable
428 * @type: type of interrupt you want to disable
429 *
430 * Disables the interrupt type for a specific src (all asics).
431 */
432int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
433 unsigned type)
434{
435 if (!adev->ddev->irq_enabled)
436 return -ENOENT;
437
438 if (type >= src->num_types)
439 return -EINVAL;
440
441 if (!src->enabled_types || !src->funcs->set)
442 return -EINVAL;
443
444 if (atomic_dec_and_test(&src->enabled_types[type]))
445 return amdgpu_irq_update(adev, src, type);
446
447 return 0;
448}
449
450/**
451 * amdgpu_irq_enabled - test if irq is enabled or not
452 *
453 * @adev: amdgpu device pointer
454 * @idx: interrupt src you want to test
455 *
456 * Tests if the given interrupt source is enabled or not
457 */
458bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
459 unsigned type)
460{
461 if (!adev->ddev->irq_enabled)
462 return false;
463
464 if (type >= src->num_types)
465 return false;
466
467 if (!src->enabled_types || !src->funcs->set)
468 return false;
469
470 return !!atomic_read(&src->enabled_types[type]);
471}
472
473/* gen irq */
474static void amdgpu_irq_mask(struct irq_data *irqd)
475{
476 /* XXX */
477}
478
479static void amdgpu_irq_unmask(struct irq_data *irqd)
480{
481 /* XXX */
482}
483
484static struct irq_chip amdgpu_irq_chip = {
485 .name = "amdgpu-ih",
486 .irq_mask = amdgpu_irq_mask,
487 .irq_unmask = amdgpu_irq_unmask,
488};
489
490static int amdgpu_irqdomain_map(struct irq_domain *d,
491 unsigned int irq, irq_hw_number_t hwirq)
492{
493 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
494 return -EPERM;
495
496 irq_set_chip_and_handler(irq,
497 &amdgpu_irq_chip, handle_simple_irq);
498 return 0;
499}
500
501static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
502 .map = amdgpu_irqdomain_map,
503};
504
505/**
506 * amdgpu_irq_add_domain - create a linear irq domain
507 *
508 * @adev: amdgpu device pointer
509 *
510 * Create an irq domain for GPU interrupt sources
511 * that may be driven by another driver (e.g., ACP).
512 */
513int amdgpu_irq_add_domain(struct amdgpu_device *adev)
514{
515 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
516 &amdgpu_hw_irqdomain_ops, adev);
517 if (!adev->irq.domain) {
518 DRM_ERROR("GPU irq add domain failed\n");
519 return -ENODEV;
520 }
521
522 return 0;
523}
524
525/**
526 * amdgpu_irq_remove_domain - remove the irq domain
527 *
528 * @adev: amdgpu device pointer
529 *
530 * Remove the irq domain for GPU interrupt sources
531 * that may be driven by another driver (e.g., ACP).
532 */
533void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
534{
535 if (adev->irq.domain) {
536 irq_domain_remove(adev->irq.domain);
537 adev->irq.domain = NULL;
538 }
539}
540
541/**
542 * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
543 * Linux irq
544 *
545 * @adev: amdgpu device pointer
546 * @src_id: IH source id
547 *
548 * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
549 * Use this for components that generate a GPU interrupt, but are driven
550 * by a different driver (e.g., ACP).
551 * Returns the Linux irq.
552 */
553unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
554{
555 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
556
557 return adev->irq.virq[src_id];
558}