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1/*
2 * Generic driver for memory-mapped GPIO controllers.
3 *
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
13 * ...`` ```````..
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
17 * `````````
18 ___
19_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
23 * ```````
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
31 * . ^^
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
37 * |
38 * ^^ / \
39 *
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
44 * `.......````.```
45 */
46
47#include <linux/init.h>
48#include <linux/err.h>
49#include <linux/bug.h>
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/spinlock.h>
53#include <linux/compiler.h>
54#include <linux/types.h>
55#include <linux/errno.h>
56#include <linux/log2.h>
57#include <linux/ioport.h>
58#include <linux/io.h>
59#include <linux/gpio/driver.h>
60#include <linux/slab.h>
61#include <linux/bitops.h>
62#include <linux/platform_device.h>
63#include <linux/mod_devicetable.h>
64
65static void bgpio_write8(void __iomem *reg, unsigned long data)
66{
67 writeb(data, reg);
68}
69
70static unsigned long bgpio_read8(void __iomem *reg)
71{
72 return readb(reg);
73}
74
75static void bgpio_write16(void __iomem *reg, unsigned long data)
76{
77 writew(data, reg);
78}
79
80static unsigned long bgpio_read16(void __iomem *reg)
81{
82 return readw(reg);
83}
84
85static void bgpio_write32(void __iomem *reg, unsigned long data)
86{
87 writel(data, reg);
88}
89
90static unsigned long bgpio_read32(void __iomem *reg)
91{
92 return readl(reg);
93}
94
95#if BITS_PER_LONG >= 64
96static void bgpio_write64(void __iomem *reg, unsigned long data)
97{
98 writeq(data, reg);
99}
100
101static unsigned long bgpio_read64(void __iomem *reg)
102{
103 return readq(reg);
104}
105#endif /* BITS_PER_LONG >= 64 */
106
107static void bgpio_write16be(void __iomem *reg, unsigned long data)
108{
109 iowrite16be(data, reg);
110}
111
112static unsigned long bgpio_read16be(void __iomem *reg)
113{
114 return ioread16be(reg);
115}
116
117static void bgpio_write32be(void __iomem *reg, unsigned long data)
118{
119 iowrite32be(data, reg);
120}
121
122static unsigned long bgpio_read32be(void __iomem *reg)
123{
124 return ioread32be(reg);
125}
126
127static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
128{
129 return BIT(pin);
130}
131
132static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
133 unsigned int pin)
134{
135 return BIT(gc->bgpio_bits - 1 - pin);
136}
137
138static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
139{
140 unsigned long pinmask = gc->pin2mask(gc, gpio);
141
142 if (gc->bgpio_dir & pinmask)
143 return !!(gc->read_reg(gc->reg_set) & pinmask);
144 else
145 return !!(gc->read_reg(gc->reg_dat) & pinmask);
146}
147
148static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
149{
150 return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
151}
152
153static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
154{
155}
156
157static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
158{
159 unsigned long mask = gc->pin2mask(gc, gpio);
160 unsigned long flags;
161
162 spin_lock_irqsave(&gc->bgpio_lock, flags);
163
164 if (val)
165 gc->bgpio_data |= mask;
166 else
167 gc->bgpio_data &= ~mask;
168
169 gc->write_reg(gc->reg_dat, gc->bgpio_data);
170
171 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
172}
173
174static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
175 int val)
176{
177 unsigned long mask = gc->pin2mask(gc, gpio);
178
179 if (val)
180 gc->write_reg(gc->reg_set, mask);
181 else
182 gc->write_reg(gc->reg_clr, mask);
183}
184
185static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
186{
187 unsigned long mask = gc->pin2mask(gc, gpio);
188 unsigned long flags;
189
190 spin_lock_irqsave(&gc->bgpio_lock, flags);
191
192 if (val)
193 gc->bgpio_data |= mask;
194 else
195 gc->bgpio_data &= ~mask;
196
197 gc->write_reg(gc->reg_set, gc->bgpio_data);
198
199 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
200}
201
202static void bgpio_multiple_get_masks(struct gpio_chip *gc,
203 unsigned long *mask, unsigned long *bits,
204 unsigned long *set_mask,
205 unsigned long *clear_mask)
206{
207 int i;
208
209 *set_mask = 0;
210 *clear_mask = 0;
211
212 for (i = 0; i < gc->bgpio_bits; i++) {
213 if (*mask == 0)
214 break;
215 if (__test_and_clear_bit(i, mask)) {
216 if (test_bit(i, bits))
217 *set_mask |= gc->pin2mask(gc, i);
218 else
219 *clear_mask |= gc->pin2mask(gc, i);
220 }
221 }
222}
223
224static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
225 unsigned long *mask,
226 unsigned long *bits,
227 void __iomem *reg)
228{
229 unsigned long flags;
230 unsigned long set_mask, clear_mask;
231
232 spin_lock_irqsave(&gc->bgpio_lock, flags);
233
234 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
235
236 gc->bgpio_data |= set_mask;
237 gc->bgpio_data &= ~clear_mask;
238
239 gc->write_reg(reg, gc->bgpio_data);
240
241 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
242}
243
244static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
245 unsigned long *bits)
246{
247 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
248}
249
250static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
251 unsigned long *bits)
252{
253 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
254}
255
256static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
257 unsigned long *mask,
258 unsigned long *bits)
259{
260 unsigned long set_mask, clear_mask;
261
262 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
263
264 if (set_mask)
265 gc->write_reg(gc->reg_set, set_mask);
266 if (clear_mask)
267 gc->write_reg(gc->reg_clr, clear_mask);
268}
269
270static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
271{
272 return 0;
273}
274
275static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
276 int val)
277{
278 return -EINVAL;
279}
280
281static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
282 int val)
283{
284 gc->set(gc, gpio, val);
285
286 return 0;
287}
288
289static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
290{
291 unsigned long flags;
292
293 spin_lock_irqsave(&gc->bgpio_lock, flags);
294
295 gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
296 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
297
298 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
299
300 return 0;
301}
302
303static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
304{
305 /* Return 0 if output, 1 of input */
306 return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
307}
308
309static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
310{
311 unsigned long flags;
312
313 gc->set(gc, gpio, val);
314
315 spin_lock_irqsave(&gc->bgpio_lock, flags);
316
317 gc->bgpio_dir |= gc->pin2mask(gc, gpio);
318 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
319
320 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
321
322 return 0;
323}
324
325static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
326{
327 unsigned long flags;
328
329 spin_lock_irqsave(&gc->bgpio_lock, flags);
330
331 gc->bgpio_dir |= gc->pin2mask(gc, gpio);
332 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
333
334 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
335
336 return 0;
337}
338
339static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
340{
341 unsigned long flags;
342
343 gc->set(gc, gpio, val);
344
345 spin_lock_irqsave(&gc->bgpio_lock, flags);
346
347 gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
348 gc->write_reg(gc->reg_dir, gc->bgpio_dir);
349
350 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
351
352 return 0;
353}
354
355static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
356{
357 /* Return 0 if output, 1 if input */
358 return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
359}
360
361static int bgpio_setup_accessors(struct device *dev,
362 struct gpio_chip *gc,
363 bool bit_be,
364 bool byte_be)
365{
366
367 switch (gc->bgpio_bits) {
368 case 8:
369 gc->read_reg = bgpio_read8;
370 gc->write_reg = bgpio_write8;
371 break;
372 case 16:
373 if (byte_be) {
374 gc->read_reg = bgpio_read16be;
375 gc->write_reg = bgpio_write16be;
376 } else {
377 gc->read_reg = bgpio_read16;
378 gc->write_reg = bgpio_write16;
379 }
380 break;
381 case 32:
382 if (byte_be) {
383 gc->read_reg = bgpio_read32be;
384 gc->write_reg = bgpio_write32be;
385 } else {
386 gc->read_reg = bgpio_read32;
387 gc->write_reg = bgpio_write32;
388 }
389 break;
390#if BITS_PER_LONG >= 64
391 case 64:
392 if (byte_be) {
393 dev_err(dev,
394 "64 bit big endian byte order unsupported\n");
395 return -EINVAL;
396 } else {
397 gc->read_reg = bgpio_read64;
398 gc->write_reg = bgpio_write64;
399 }
400 break;
401#endif /* BITS_PER_LONG >= 64 */
402 default:
403 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
404 return -EINVAL;
405 }
406
407 gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
408
409 return 0;
410}
411
412/*
413 * Create the device and allocate the resources. For setting GPIO's there are
414 * three supported configurations:
415 *
416 * - single input/output register resource (named "dat").
417 * - set/clear pair (named "set" and "clr").
418 * - single output register resource and single input resource ("set" and
419 * dat").
420 *
421 * For the single output register, this drives a 1 by setting a bit and a zero
422 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
423 * in the set register and clears it by setting a bit in the clear register.
424 * The configuration is detected by which resources are present.
425 *
426 * For setting the GPIO direction, there are three supported configurations:
427 *
428 * - simple bidirection GPIO that requires no configuration.
429 * - an output direction register (named "dirout") where a 1 bit
430 * indicates the GPIO is an output.
431 * - an input direction register (named "dirin") where a 1 bit indicates
432 * the GPIO is an input.
433 */
434static int bgpio_setup_io(struct gpio_chip *gc,
435 void __iomem *dat,
436 void __iomem *set,
437 void __iomem *clr,
438 unsigned long flags)
439{
440
441 gc->reg_dat = dat;
442 if (!gc->reg_dat)
443 return -EINVAL;
444
445 if (set && clr) {
446 gc->reg_set = set;
447 gc->reg_clr = clr;
448 gc->set = bgpio_set_with_clear;
449 gc->set_multiple = bgpio_set_multiple_with_clear;
450 } else if (set && !clr) {
451 gc->reg_set = set;
452 gc->set = bgpio_set_set;
453 gc->set_multiple = bgpio_set_multiple_set;
454 } else if (flags & BGPIOF_NO_OUTPUT) {
455 gc->set = bgpio_set_none;
456 gc->set_multiple = NULL;
457 } else {
458 gc->set = bgpio_set;
459 gc->set_multiple = bgpio_set_multiple;
460 }
461
462 if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
463 (flags & BGPIOF_READ_OUTPUT_REG_SET))
464 gc->get = bgpio_get_set;
465 else
466 gc->get = bgpio_get;
467
468 return 0;
469}
470
471static int bgpio_setup_direction(struct gpio_chip *gc,
472 void __iomem *dirout,
473 void __iomem *dirin,
474 unsigned long flags)
475{
476 if (dirout && dirin) {
477 return -EINVAL;
478 } else if (dirout) {
479 gc->reg_dir = dirout;
480 gc->direction_output = bgpio_dir_out;
481 gc->direction_input = bgpio_dir_in;
482 gc->get_direction = bgpio_get_dir;
483 } else if (dirin) {
484 gc->reg_dir = dirin;
485 gc->direction_output = bgpio_dir_out_inv;
486 gc->direction_input = bgpio_dir_in_inv;
487 gc->get_direction = bgpio_get_dir_inv;
488 } else {
489 if (flags & BGPIOF_NO_OUTPUT)
490 gc->direction_output = bgpio_dir_out_err;
491 else
492 gc->direction_output = bgpio_simple_dir_out;
493 gc->direction_input = bgpio_simple_dir_in;
494 }
495
496 return 0;
497}
498
499static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
500{
501 if (gpio_pin < chip->ngpio)
502 return 0;
503
504 return -EINVAL;
505}
506
507int bgpio_init(struct gpio_chip *gc, struct device *dev,
508 unsigned long sz, void __iomem *dat, void __iomem *set,
509 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
510 unsigned long flags)
511{
512 int ret;
513
514 if (!is_power_of_2(sz))
515 return -EINVAL;
516
517 gc->bgpio_bits = sz * 8;
518 if (gc->bgpio_bits > BITS_PER_LONG)
519 return -EINVAL;
520
521 spin_lock_init(&gc->bgpio_lock);
522 gc->parent = dev;
523 gc->label = dev_name(dev);
524 gc->base = -1;
525 gc->ngpio = gc->bgpio_bits;
526 gc->request = bgpio_request;
527
528 ret = bgpio_setup_io(gc, dat, set, clr, flags);
529 if (ret)
530 return ret;
531
532 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
533 flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
534 if (ret)
535 return ret;
536
537 ret = bgpio_setup_direction(gc, dirout, dirin, flags);
538 if (ret)
539 return ret;
540
541 gc->bgpio_data = gc->read_reg(gc->reg_dat);
542 if (gc->set == bgpio_set_set &&
543 !(flags & BGPIOF_UNREADABLE_REG_SET))
544 gc->bgpio_data = gc->read_reg(gc->reg_set);
545 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
546 gc->bgpio_dir = gc->read_reg(gc->reg_dir);
547
548 return ret;
549}
550EXPORT_SYMBOL_GPL(bgpio_init);
551
552#ifdef CONFIG_GPIO_GENERIC_PLATFORM
553
554static void __iomem *bgpio_map(struct platform_device *pdev,
555 const char *name,
556 resource_size_t sane_sz)
557{
558 struct resource *r;
559 resource_size_t sz;
560
561 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
562 if (!r)
563 return NULL;
564
565 sz = resource_size(r);
566 if (sz != sane_sz)
567 return IOMEM_ERR_PTR(-EINVAL);
568
569 return devm_ioremap_resource(&pdev->dev, r);
570}
571
572static int bgpio_pdev_probe(struct platform_device *pdev)
573{
574 struct device *dev = &pdev->dev;
575 struct resource *r;
576 void __iomem *dat;
577 void __iomem *set;
578 void __iomem *clr;
579 void __iomem *dirout;
580 void __iomem *dirin;
581 unsigned long sz;
582 unsigned long flags = pdev->id_entry->driver_data;
583 int err;
584 struct gpio_chip *gc;
585 struct bgpio_pdata *pdata = dev_get_platdata(dev);
586
587 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
588 if (!r)
589 return -EINVAL;
590
591 sz = resource_size(r);
592
593 dat = bgpio_map(pdev, "dat", sz);
594 if (IS_ERR(dat))
595 return PTR_ERR(dat);
596
597 set = bgpio_map(pdev, "set", sz);
598 if (IS_ERR(set))
599 return PTR_ERR(set);
600
601 clr = bgpio_map(pdev, "clr", sz);
602 if (IS_ERR(clr))
603 return PTR_ERR(clr);
604
605 dirout = bgpio_map(pdev, "dirout", sz);
606 if (IS_ERR(dirout))
607 return PTR_ERR(dirout);
608
609 dirin = bgpio_map(pdev, "dirin", sz);
610 if (IS_ERR(dirin))
611 return PTR_ERR(dirin);
612
613 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
614 if (!gc)
615 return -ENOMEM;
616
617 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
618 if (err)
619 return err;
620
621 if (pdata) {
622 if (pdata->label)
623 gc->label = pdata->label;
624 gc->base = pdata->base;
625 if (pdata->ngpio > 0)
626 gc->ngpio = pdata->ngpio;
627 }
628
629 platform_set_drvdata(pdev, gc);
630
631 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
632}
633
634static const struct platform_device_id bgpio_id_table[] = {
635 {
636 .name = "basic-mmio-gpio",
637 .driver_data = 0,
638 }, {
639 .name = "basic-mmio-gpio-be",
640 .driver_data = BGPIOF_BIG_ENDIAN,
641 },
642 { }
643};
644MODULE_DEVICE_TABLE(platform, bgpio_id_table);
645
646static struct platform_driver bgpio_driver = {
647 .driver = {
648 .name = "basic-mmio-gpio",
649 },
650 .id_table = bgpio_id_table,
651 .probe = bgpio_pdev_probe,
652};
653
654module_platform_driver(bgpio_driver);
655
656#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
657
658MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
659MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
660MODULE_LICENSE("GPL");
1/*
2 * Generic driver for memory-mapped GPIO controllers.
3 *
4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
13 * ...`` ```````..
14 * ..The simplest form of a GPIO controller that the driver supports is``
15 * `.just a single "data" register, where GPIO state can be read and/or `
16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
17 * `````````
18 ___
19_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
20__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
21o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
22 `....trivial..'~`.```.```
23 * ```````
24 * .```````~~~~`..`.``.``.
25 * . The driver supports `... ,..```.`~~~```````````````....````.``,,
26 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
27 * . register the device with -be`. .with a pair of set/clear-bit registers ,
28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
29 * ``.`.``...``` ```.. output pins are also supported.`
30 * ^^ `````.`````````.,``~``~``~~``````
31 * . ^^
32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
33 * .. The expectation is that in at least some cases . ,-~~~-,
34 * .this will be used with roll-your-own ASIC/FPGA .` \ /
35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
36 * ..````````......``````````` \o_
37 * |
38 * ^^ / \
39 *
40 * ...`````~~`.....``.`..........``````.`.``.```........``.
41 * ` 8, 16, 32 and 64 bits registers are supported, and``.
42 * . the number of GPIOs is determined by the width of ~
43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
44 * `.......````.```
45 */
46
47#include <linux/init.h>
48#include <linux/err.h>
49#include <linux/bug.h>
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/spinlock.h>
53#include <linux/compiler.h>
54#include <linux/types.h>
55#include <linux/errno.h>
56#include <linux/log2.h>
57#include <linux/ioport.h>
58#include <linux/io.h>
59#include <linux/gpio.h>
60#include <linux/slab.h>
61#include <linux/platform_device.h>
62#include <linux/mod_devicetable.h>
63#include <linux/basic_mmio_gpio.h>
64
65static void bgpio_write8(void __iomem *reg, unsigned long data)
66{
67 writeb(data, reg);
68}
69
70static unsigned long bgpio_read8(void __iomem *reg)
71{
72 return readb(reg);
73}
74
75static void bgpio_write16(void __iomem *reg, unsigned long data)
76{
77 writew(data, reg);
78}
79
80static unsigned long bgpio_read16(void __iomem *reg)
81{
82 return readw(reg);
83}
84
85static void bgpio_write32(void __iomem *reg, unsigned long data)
86{
87 writel(data, reg);
88}
89
90static unsigned long bgpio_read32(void __iomem *reg)
91{
92 return readl(reg);
93}
94
95#if BITS_PER_LONG >= 64
96static void bgpio_write64(void __iomem *reg, unsigned long data)
97{
98 writeq(data, reg);
99}
100
101static unsigned long bgpio_read64(void __iomem *reg)
102{
103 return readq(reg);
104}
105#endif /* BITS_PER_LONG >= 64 */
106
107static void bgpio_write16be(void __iomem *reg, unsigned long data)
108{
109 iowrite16be(data, reg);
110}
111
112static unsigned long bgpio_read16be(void __iomem *reg)
113{
114 return ioread16be(reg);
115}
116
117static void bgpio_write32be(void __iomem *reg, unsigned long data)
118{
119 iowrite32be(data, reg);
120}
121
122static unsigned long bgpio_read32be(void __iomem *reg)
123{
124 return ioread32be(reg);
125}
126
127static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
128{
129 return 1 << pin;
130}
131
132static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
133 unsigned int pin)
134{
135 return 1 << (bgc->bits - 1 - pin);
136}
137
138static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
139{
140 struct bgpio_chip *bgc = to_bgpio_chip(gc);
141
142 return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
143}
144
145static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
146{
147 struct bgpio_chip *bgc = to_bgpio_chip(gc);
148 unsigned long mask = bgc->pin2mask(bgc, gpio);
149 unsigned long flags;
150
151 spin_lock_irqsave(&bgc->lock, flags);
152
153 if (val)
154 bgc->data |= mask;
155 else
156 bgc->data &= ~mask;
157
158 bgc->write_reg(bgc->reg_dat, bgc->data);
159
160 spin_unlock_irqrestore(&bgc->lock, flags);
161}
162
163static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
164 int val)
165{
166 struct bgpio_chip *bgc = to_bgpio_chip(gc);
167 unsigned long mask = bgc->pin2mask(bgc, gpio);
168
169 if (val)
170 bgc->write_reg(bgc->reg_set, mask);
171 else
172 bgc->write_reg(bgc->reg_clr, mask);
173}
174
175static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
176{
177 struct bgpio_chip *bgc = to_bgpio_chip(gc);
178 unsigned long mask = bgc->pin2mask(bgc, gpio);
179 unsigned long flags;
180
181 spin_lock_irqsave(&bgc->lock, flags);
182
183 if (val)
184 bgc->data |= mask;
185 else
186 bgc->data &= ~mask;
187
188 bgc->write_reg(bgc->reg_set, bgc->data);
189
190 spin_unlock_irqrestore(&bgc->lock, flags);
191}
192
193static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
194{
195 return 0;
196}
197
198static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
199 int val)
200{
201 gc->set(gc, gpio, val);
202
203 return 0;
204}
205
206static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
207{
208 struct bgpio_chip *bgc = to_bgpio_chip(gc);
209 unsigned long flags;
210
211 spin_lock_irqsave(&bgc->lock, flags);
212
213 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
214 bgc->write_reg(bgc->reg_dir, bgc->dir);
215
216 spin_unlock_irqrestore(&bgc->lock, flags);
217
218 return 0;
219}
220
221static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
222{
223 struct bgpio_chip *bgc = to_bgpio_chip(gc);
224 unsigned long flags;
225
226 gc->set(gc, gpio, val);
227
228 spin_lock_irqsave(&bgc->lock, flags);
229
230 bgc->dir |= bgc->pin2mask(bgc, gpio);
231 bgc->write_reg(bgc->reg_dir, bgc->dir);
232
233 spin_unlock_irqrestore(&bgc->lock, flags);
234
235 return 0;
236}
237
238static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
239{
240 struct bgpio_chip *bgc = to_bgpio_chip(gc);
241 unsigned long flags;
242
243 spin_lock_irqsave(&bgc->lock, flags);
244
245 bgc->dir |= bgc->pin2mask(bgc, gpio);
246 bgc->write_reg(bgc->reg_dir, bgc->dir);
247
248 spin_unlock_irqrestore(&bgc->lock, flags);
249
250 return 0;
251}
252
253static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
254{
255 struct bgpio_chip *bgc = to_bgpio_chip(gc);
256 unsigned long flags;
257
258 gc->set(gc, gpio, val);
259
260 spin_lock_irqsave(&bgc->lock, flags);
261
262 bgc->dir &= ~bgc->pin2mask(bgc, gpio);
263 bgc->write_reg(bgc->reg_dir, bgc->dir);
264
265 spin_unlock_irqrestore(&bgc->lock, flags);
266
267 return 0;
268}
269
270static int bgpio_setup_accessors(struct device *dev,
271 struct bgpio_chip *bgc,
272 bool bit_be,
273 bool byte_be)
274{
275
276 switch (bgc->bits) {
277 case 8:
278 bgc->read_reg = bgpio_read8;
279 bgc->write_reg = bgpio_write8;
280 break;
281 case 16:
282 if (byte_be) {
283 bgc->read_reg = bgpio_read16be;
284 bgc->write_reg = bgpio_write16be;
285 } else {
286 bgc->read_reg = bgpio_read16;
287 bgc->write_reg = bgpio_write16;
288 }
289 break;
290 case 32:
291 if (byte_be) {
292 bgc->read_reg = bgpio_read32be;
293 bgc->write_reg = bgpio_write32be;
294 } else {
295 bgc->read_reg = bgpio_read32;
296 bgc->write_reg = bgpio_write32;
297 }
298 break;
299#if BITS_PER_LONG >= 64
300 case 64:
301 if (byte_be) {
302 dev_err(dev,
303 "64 bit big endian byte order unsupported\n");
304 return -EINVAL;
305 } else {
306 bgc->read_reg = bgpio_read64;
307 bgc->write_reg = bgpio_write64;
308 }
309 break;
310#endif /* BITS_PER_LONG >= 64 */
311 default:
312 dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
313 return -EINVAL;
314 }
315
316 bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
317
318 return 0;
319}
320
321/*
322 * Create the device and allocate the resources. For setting GPIO's there are
323 * three supported configurations:
324 *
325 * - single input/output register resource (named "dat").
326 * - set/clear pair (named "set" and "clr").
327 * - single output register resource and single input resource ("set" and
328 * dat").
329 *
330 * For the single output register, this drives a 1 by setting a bit and a zero
331 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
332 * in the set register and clears it by setting a bit in the clear register.
333 * The configuration is detected by which resources are present.
334 *
335 * For setting the GPIO direction, there are three supported configurations:
336 *
337 * - simple bidirection GPIO that requires no configuration.
338 * - an output direction register (named "dirout") where a 1 bit
339 * indicates the GPIO is an output.
340 * - an input direction register (named "dirin") where a 1 bit indicates
341 * the GPIO is an input.
342 */
343static int bgpio_setup_io(struct bgpio_chip *bgc,
344 void __iomem *dat,
345 void __iomem *set,
346 void __iomem *clr)
347{
348
349 bgc->reg_dat = dat;
350 if (!bgc->reg_dat)
351 return -EINVAL;
352
353 if (set && clr) {
354 bgc->reg_set = set;
355 bgc->reg_clr = clr;
356 bgc->gc.set = bgpio_set_with_clear;
357 } else if (set && !clr) {
358 bgc->reg_set = set;
359 bgc->gc.set = bgpio_set_set;
360 } else {
361 bgc->gc.set = bgpio_set;
362 }
363
364 bgc->gc.get = bgpio_get;
365
366 return 0;
367}
368
369static int bgpio_setup_direction(struct bgpio_chip *bgc,
370 void __iomem *dirout,
371 void __iomem *dirin)
372{
373 if (dirout && dirin) {
374 return -EINVAL;
375 } else if (dirout) {
376 bgc->reg_dir = dirout;
377 bgc->gc.direction_output = bgpio_dir_out;
378 bgc->gc.direction_input = bgpio_dir_in;
379 } else if (dirin) {
380 bgc->reg_dir = dirin;
381 bgc->gc.direction_output = bgpio_dir_out_inv;
382 bgc->gc.direction_input = bgpio_dir_in_inv;
383 } else {
384 bgc->gc.direction_output = bgpio_simple_dir_out;
385 bgc->gc.direction_input = bgpio_simple_dir_in;
386 }
387
388 return 0;
389}
390
391int bgpio_remove(struct bgpio_chip *bgc)
392{
393 return gpiochip_remove(&bgc->gc);
394}
395EXPORT_SYMBOL_GPL(bgpio_remove);
396
397int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
398 unsigned long sz, void __iomem *dat, void __iomem *set,
399 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
400 unsigned long flags)
401{
402 int ret;
403
404 if (!is_power_of_2(sz))
405 return -EINVAL;
406
407 bgc->bits = sz * 8;
408 if (bgc->bits > BITS_PER_LONG)
409 return -EINVAL;
410
411 spin_lock_init(&bgc->lock);
412 bgc->gc.dev = dev;
413 bgc->gc.label = dev_name(dev);
414 bgc->gc.base = -1;
415 bgc->gc.ngpio = bgc->bits;
416
417 ret = bgpio_setup_io(bgc, dat, set, clr);
418 if (ret)
419 return ret;
420
421 ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
422 flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
423 if (ret)
424 return ret;
425
426 ret = bgpio_setup_direction(bgc, dirout, dirin);
427 if (ret)
428 return ret;
429
430 bgc->data = bgc->read_reg(bgc->reg_dat);
431 if (bgc->gc.set == bgpio_set_set &&
432 !(flags & BGPIOF_UNREADABLE_REG_SET))
433 bgc->data = bgc->read_reg(bgc->reg_set);
434 if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
435 bgc->dir = bgc->read_reg(bgc->reg_dir);
436
437 return ret;
438}
439EXPORT_SYMBOL_GPL(bgpio_init);
440
441#ifdef CONFIG_GPIO_GENERIC_PLATFORM
442
443static void __iomem *bgpio_map(struct platform_device *pdev,
444 const char *name,
445 resource_size_t sane_sz,
446 int *err)
447{
448 struct device *dev = &pdev->dev;
449 struct resource *r;
450 resource_size_t start;
451 resource_size_t sz;
452 void __iomem *ret;
453
454 *err = 0;
455
456 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
457 if (!r)
458 return NULL;
459
460 sz = resource_size(r);
461 if (sz != sane_sz) {
462 *err = -EINVAL;
463 return NULL;
464 }
465
466 start = r->start;
467 if (!devm_request_mem_region(dev, start, sz, r->name)) {
468 *err = -EBUSY;
469 return NULL;
470 }
471
472 ret = devm_ioremap(dev, start, sz);
473 if (!ret) {
474 *err = -ENOMEM;
475 return NULL;
476 }
477
478 return ret;
479}
480
481static int bgpio_pdev_probe(struct platform_device *pdev)
482{
483 struct device *dev = &pdev->dev;
484 struct resource *r;
485 void __iomem *dat;
486 void __iomem *set;
487 void __iomem *clr;
488 void __iomem *dirout;
489 void __iomem *dirin;
490 unsigned long sz;
491 unsigned long flags = pdev->id_entry->driver_data;
492 int err;
493 struct bgpio_chip *bgc;
494 struct bgpio_pdata *pdata = dev_get_platdata(dev);
495
496 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
497 if (!r)
498 return -EINVAL;
499
500 sz = resource_size(r);
501
502 dat = bgpio_map(pdev, "dat", sz, &err);
503 if (!dat)
504 return err ? err : -EINVAL;
505
506 set = bgpio_map(pdev, "set", sz, &err);
507 if (err)
508 return err;
509
510 clr = bgpio_map(pdev, "clr", sz, &err);
511 if (err)
512 return err;
513
514 dirout = bgpio_map(pdev, "dirout", sz, &err);
515 if (err)
516 return err;
517
518 dirin = bgpio_map(pdev, "dirin", sz, &err);
519 if (err)
520 return err;
521
522 bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
523 if (!bgc)
524 return -ENOMEM;
525
526 err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
527 if (err)
528 return err;
529
530 if (pdata) {
531 if (pdata->label)
532 bgc->gc.label = pdata->label;
533 bgc->gc.base = pdata->base;
534 if (pdata->ngpio > 0)
535 bgc->gc.ngpio = pdata->ngpio;
536 }
537
538 platform_set_drvdata(pdev, bgc);
539
540 return gpiochip_add(&bgc->gc);
541}
542
543static int bgpio_pdev_remove(struct platform_device *pdev)
544{
545 struct bgpio_chip *bgc = platform_get_drvdata(pdev);
546
547 return bgpio_remove(bgc);
548}
549
550static const struct platform_device_id bgpio_id_table[] = {
551 {
552 .name = "basic-mmio-gpio",
553 .driver_data = 0,
554 }, {
555 .name = "basic-mmio-gpio-be",
556 .driver_data = BGPIOF_BIG_ENDIAN,
557 },
558 { }
559};
560MODULE_DEVICE_TABLE(platform, bgpio_id_table);
561
562static struct platform_driver bgpio_driver = {
563 .driver = {
564 .name = "basic-mmio-gpio",
565 },
566 .id_table = bgpio_id_table,
567 .probe = bgpio_pdev_probe,
568 .remove = bgpio_pdev_remove,
569};
570
571module_platform_driver(bgpio_driver);
572
573#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
574
575MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
576MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
577MODULE_LICENSE("GPL");