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1/*
2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
4 *
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
6 */
7
8#include <asm/asm-offsets.h>
9#include <asm/ppc_asm.h>
10#include <asm/ppc-opcode.h>
11#include <asm/ptrace.h>
12#include <asm/reg.h>
13#include <asm/bug.h>
14
15#ifdef CONFIG_VSX
16/* See fpu.S, this is borrowed from there */
17#define __SAVE_32FPRS_VSRS(n,c,base) \
18BEGIN_FTR_SECTION \
19 b 2f; \
20END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
21 SAVE_32FPRS(n,base); \
22 b 3f; \
232: SAVE_32VSRS(n,c,base); \
243:
25#define __REST_32FPRS_VSRS(n,c,base) \
26BEGIN_FTR_SECTION \
27 b 2f; \
28END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
30 b 3f; \
312: REST_32VSRS(n,c,base); \
323:
33#else
34#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
35#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
36#endif
37#define SAVE_32FPRS_VSRS(n,c,base) \
38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
39#define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
41
42/* Stack frame offsets for local variables. */
43#define TM_FRAME_L0 TM_FRAME_SIZE-16
44#define TM_FRAME_L1 TM_FRAME_SIZE-8
45
46
47/* In order to access the TM SPRs, TM must be enabled. So, do so: */
48_GLOBAL(tm_enable)
49 mfmsr r4
50 li r3, MSR_TM >> 32
51 sldi r3, r3, 32
52 and. r0, r4, r3
53 bne 1f
54 or r4, r4, r3
55 mtmsrd r4
561: blr
57
58_GLOBAL(tm_save_sprs)
59 mfspr r0, SPRN_TFHAR
60 std r0, THREAD_TM_TFHAR(r3)
61 mfspr r0, SPRN_TEXASR
62 std r0, THREAD_TM_TEXASR(r3)
63 mfspr r0, SPRN_TFIAR
64 std r0, THREAD_TM_TFIAR(r3)
65 blr
66
67_GLOBAL(tm_restore_sprs)
68 ld r0, THREAD_TM_TFHAR(r3)
69 mtspr SPRN_TFHAR, r0
70 ld r0, THREAD_TM_TEXASR(r3)
71 mtspr SPRN_TEXASR, r0
72 ld r0, THREAD_TM_TFIAR(r3)
73 mtspr SPRN_TFIAR, r0
74 blr
75
76 /* Passed an 8-bit failure cause as first argument. */
77_GLOBAL(tm_abort)
78 TABORT(R3)
79 blr
80
81/* void tm_reclaim(struct thread_struct *thread,
82 * unsigned long orig_msr,
83 * uint8_t cause)
84 *
85 * - Performs a full reclaim. This destroys outstanding
86 * transactions and updates thread->regs.tm_ckpt_* with the
87 * original checkpointed state. Note that thread->regs is
88 * unchanged.
89 * - FP regs are written back to thread->transact_fpr before
90 * reclaiming. These are the transactional (current) versions.
91 *
92 * Purpose is to both abort transactions of, and preserve the state of,
93 * a transactions at a context switch. We preserve/restore both sets of process
94 * state to restore them when the thread's scheduled again. We continue in
95 * userland as though nothing happened, but when the transaction is resumed
96 * they will abort back to the checkpointed state we save out here.
97 *
98 * Call with IRQs off, stacks get all out of sync for some periods in here!
99 */
100_GLOBAL(tm_reclaim)
101 mfcr r6
102 mflr r0
103 stw r6, 8(r1)
104 std r0, 16(r1)
105 std r2, STK_GOT(r1)
106 stdu r1, -TM_FRAME_SIZE(r1)
107
108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
109
110 std r3, STK_PARAM(R3)(r1)
111 SAVE_NVGPRS(r1)
112
113 /* We need to setup MSR for VSX register save instructions. Here we
114 * also clear the MSR RI since when we do the treclaim, we won't have a
115 * valid kernel pointer for a while. We clear RI here as it avoids
116 * adding another mtmsr closer to the treclaim. This makes the region
117 * maked as non-recoverable wider than it needs to be but it saves on
118 * inserting another mtmsrd later.
119 */
120 mfmsr r14
121 mr r15, r14
122 ori r15, r15, MSR_FP
123 li r16, MSR_RI
124 ori r16, r16, MSR_EE /* IRQs hard off */
125 andc r15, r15, r16
126 oris r15, r15, MSR_VEC@h
127#ifdef CONFIG_VSX
128 BEGIN_FTR_SECTION
129 oris r15,r15, MSR_VSX@h
130 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
131#endif
132 mtmsrd r15
133 std r14, TM_FRAME_L0(r1)
134
135 /* Stash the stack pointer away for use after reclaim */
136 std r1, PACAR1(r13)
137
138 /* ******************** FPR/VR/VSRs ************
139 * Before reclaiming, capture the current/transactional FPR/VR
140 * versions /if used/.
141 *
142 * (If VSX used, FP and VMX are implied. Or, we don't need to look
143 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
144 *
145 * We're passed the thread's MSR as parameter 2.
146 *
147 * We enabled VEC/FP/VSX in the msr above, so we can execute these
148 * instructions!
149 */
150 andis. r0, r4, MSR_VEC@h
151 beq dont_backup_vec
152
153 addi r7, r3, THREAD_TRANSACT_VRSTATE
154 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
155 mfvscr v0
156 li r6, VRSTATE_VSCR
157 stvx v0, r7, r6
158dont_backup_vec:
159 mfspr r0, SPRN_VRSAVE
160 std r0, THREAD_TRANSACT_VRSAVE(r3)
161
162 andi. r0, r4, MSR_FP
163 beq dont_backup_fp
164
165 addi r7, r3, THREAD_TRANSACT_FPSTATE
166 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
167
168 mffs fr0
169 stfd fr0,FPSTATE_FPSCR(r7)
170
171dont_backup_fp:
172 /* Do sanity check on MSR to make sure we are suspended */
173 li r7, (MSR_TS_S)@higher
174 srdi r6, r14, 32
175 and r6, r6, r7
1761: tdeqi r6, 0
177 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
178
179 /* The moment we treclaim, ALL of our GPRs will switch
180 * to user register state. (FPRs, CCR etc. also!)
181 * Use an sprg and a tm_scratch in the PACA to shuffle.
182 */
183 TRECLAIM(R5) /* Cause in r5 */
184
185 /* ******************** GPRs ******************** */
186 /* Stash the checkpointed r13 away in the scratch SPR and get the real
187 * paca
188 */
189 SET_SCRATCH0(r13)
190 GET_PACA(r13)
191
192 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
193 * stack pointer back
194 */
195 std r1, PACATMSCRATCH(r13)
196 ld r1, PACAR1(r13)
197
198 /* Store the PPR in r11 and reset to decent value */
199 std r11, GPR11(r1) /* Temporary stash */
200 mfspr r11, SPRN_PPR
201 HMT_MEDIUM
202
203 /* Now get some more GPRS free */
204 std r7, GPR7(r1) /* Temporary stash */
205 std r12, GPR12(r1) /* '' '' '' */
206 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
207
208 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
209
210 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
211
212 /* Make r7 look like an exception frame so that we
213 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
214 */
215 subi r7, r7, STACK_FRAME_OVERHEAD
216
217 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
218 SAVE_GPR(0, r7) /* user r0 */
219 SAVE_GPR(2, r7) /* user r2 */
220 SAVE_4GPRS(3, r7) /* user r3-r6 */
221 SAVE_GPR(8, r7) /* user r8 */
222 SAVE_GPR(9, r7) /* user r9 */
223 SAVE_GPR(10, r7) /* user r10 */
224 ld r3, PACATMSCRATCH(r13) /* user r1 */
225 ld r4, GPR7(r1) /* user r7 */
226 ld r5, GPR11(r1) /* user r11 */
227 ld r6, GPR12(r1) /* user r12 */
228 GET_SCRATCH0(8) /* user r13 */
229 std r3, GPR1(r7)
230 std r4, GPR7(r7)
231 std r5, GPR11(r7)
232 std r6, GPR12(r7)
233 std r8, GPR13(r7)
234
235 SAVE_NVGPRS(r7) /* user r14-r31 */
236
237 /* ******************** NIP ******************** */
238 mfspr r3, SPRN_TFHAR
239 std r3, _NIP(r7) /* Returns to failhandler */
240 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
241 * but is used in signal return to 'wind back' to the abort handler.
242 */
243
244 /* ******************** CR,LR,CCR,MSR ********** */
245 mfctr r3
246 mflr r4
247 mfcr r5
248 mfxer r6
249
250 std r3, _CTR(r7)
251 std r4, _LINK(r7)
252 std r5, _CCR(r7)
253 std r6, _XER(r7)
254
255
256 /* ******************** TAR, DSCR ********** */
257 mfspr r3, SPRN_TAR
258 mfspr r4, SPRN_DSCR
259
260 std r3, THREAD_TM_TAR(r12)
261 std r4, THREAD_TM_DSCR(r12)
262
263 /* MSR and flags: We don't change CRs, and we don't need to alter
264 * MSR.
265 */
266
267 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
268 * been updated by the treclaim, to explain to userland the failure
269 * cause (aborted).
270 */
271 mfspr r0, SPRN_TEXASR
272 mfspr r3, SPRN_TFHAR
273 mfspr r4, SPRN_TFIAR
274 std r0, THREAD_TM_TEXASR(r12)
275 std r3, THREAD_TM_TFHAR(r12)
276 std r4, THREAD_TM_TFIAR(r12)
277
278 /* AMR is checkpointed too, but is unsupported by Linux. */
279
280 /* Restore original MSR/IRQ state & clear TM mode */
281 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
282 li r15, 0
283 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
284 mtmsrd r14
285
286 REST_NVGPRS(r1)
287
288 addi r1, r1, TM_FRAME_SIZE
289 lwz r4, 8(r1)
290 ld r0, 16(r1)
291 mtcr r4
292 mtlr r0
293 ld r2, STK_GOT(r1)
294
295 /* Load CPU's default DSCR */
296 ld r0, PACA_DSCR_DEFAULT(r13)
297 mtspr SPRN_DSCR, r0
298
299 blr
300
301
302 /* void tm_recheckpoint(struct thread_struct *thread,
303 * unsigned long orig_msr)
304 * - Restore the checkpointed register state saved by tm_reclaim
305 * when we switch_to a process.
306 *
307 * Call with IRQs off, stacks get all out of sync for
308 * some periods in here!
309 */
310_GLOBAL(__tm_recheckpoint)
311 mfcr r5
312 mflr r0
313 stw r5, 8(r1)
314 std r0, 16(r1)
315 std r2, STK_GOT(r1)
316 stdu r1, -TM_FRAME_SIZE(r1)
317
318 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
319 * This is used for backing up the NVGPRs:
320 */
321 SAVE_NVGPRS(r1)
322
323 /* Load complete register state from ts_ckpt* registers */
324
325 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
326
327 /* Make r7 look like an exception frame so that we
328 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
329 */
330 subi r7, r7, STACK_FRAME_OVERHEAD
331
332 SET_SCRATCH0(r1)
333
334 mfmsr r6
335 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
336
337 /* Enable FP/vec in MSR if necessary! */
338 lis r5, MSR_VEC@h
339 ori r5, r5, MSR_FP
340 and. r5, r4, r5
341 beq restore_gprs /* if neither, skip both */
342
343#ifdef CONFIG_VSX
344 BEGIN_FTR_SECTION
345 oris r5, r5, MSR_VSX@h
346 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
347#endif
348 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
349 mtmsr r5
350
351#ifdef CONFIG_ALTIVEC
352 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
353 * and thread.vr[] respectively. The thread.transact_fpr[] version
354 * is more modern, and will be loaded subsequently by any FPUnavailable
355 * trap.
356 */
357 andis. r0, r4, MSR_VEC@h
358 beq dont_restore_vec
359
360 addi r8, r3, THREAD_VRSTATE
361 li r5, VRSTATE_VSCR
362 lvx v0, r8, r5
363 mtvscr v0
364 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
365dont_restore_vec:
366 ld r5, THREAD_VRSAVE(r3)
367 mtspr SPRN_VRSAVE, r5
368#endif
369
370 andi. r0, r4, MSR_FP
371 beq dont_restore_fp
372
373 addi r8, r3, THREAD_FPSTATE
374 lfd fr0, FPSTATE_FPSCR(r8)
375 MTFSF_L(fr0)
376 REST_32FPRS_VSRS(0, R4, R8)
377
378dont_restore_fp:
379 mtmsr r6 /* FP/Vec off again! */
380
381restore_gprs:
382
383 /* ******************** CR,LR,CCR,MSR ********** */
384 ld r4, _CTR(r7)
385 ld r5, _LINK(r7)
386 ld r8, _XER(r7)
387
388 mtctr r4
389 mtlr r5
390 mtxer r8
391
392 /* ******************** TAR ******************** */
393 ld r4, THREAD_TM_TAR(r3)
394 mtspr SPRN_TAR, r4
395
396 /* Load up the PPR and DSCR in GPRs only at this stage */
397 ld r5, THREAD_TM_DSCR(r3)
398 ld r6, THREAD_TM_PPR(r3)
399
400 /* Clear the MSR RI since we are about to change R1. EE is already off
401 */
402 li r4, 0
403 mtmsrd r4, 1
404
405 REST_GPR(0, r7) /* GPR0 */
406 REST_2GPRS(2, r7) /* GPR2-3 */
407 REST_GPR(4, r7) /* GPR4 */
408 REST_4GPRS(8, r7) /* GPR8-11 */
409 REST_2GPRS(12, r7) /* GPR12-13 */
410
411 REST_NVGPRS(r7) /* GPR14-31 */
412
413 /* Load up PPR and DSCR here so we don't run with user values for long
414 */
415 mtspr SPRN_DSCR, r5
416 mtspr SPRN_PPR, r6
417
418 /* Do final sanity check on TEXASR to make sure FS is set. Do this
419 * here before we load up the userspace r1 so any bugs we hit will get
420 * a call chain */
421 mfspr r5, SPRN_TEXASR
422 srdi r5, r5, 16
423 li r6, (TEXASR_FS)@h
424 and r6, r6, r5
4251: tdeqi r6, 0
426 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
427
428 /* Do final sanity check on MSR to make sure we are not transactional
429 * or suspended
430 */
431 mfmsr r6
432 li r5, (MSR_TS_MASK)@higher
433 srdi r6, r6, 32
434 and r6, r6, r5
4351: tdnei r6, 0
436 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
437
438 /* Restore CR */
439 ld r6, _CCR(r7)
440 mtcr r6
441
442 REST_GPR(1, r7) /* GPR1 */
443 REST_GPR(5, r7) /* GPR5-7 */
444 REST_GPR(6, r7)
445 ld r7, GPR7(r7)
446
447 /* Commit register state as checkpointed state: */
448 TRECHKPT
449
450 HMT_MEDIUM
451
452 /* Our transactional state has now changed.
453 *
454 * Now just get out of here. Transactional (current) state will be
455 * updated once restore is called on the return path in the _switch-ed
456 * -to process.
457 */
458
459 GET_PACA(r13)
460 GET_SCRATCH0(r1)
461
462 /* R1 is restored, so we are recoverable again. EE is still off */
463 li r4, MSR_RI
464 mtmsrd r4, 1
465
466 REST_NVGPRS(r1)
467
468 addi r1, r1, TM_FRAME_SIZE
469 lwz r4, 8(r1)
470 ld r0, 16(r1)
471 mtcr r4
472 mtlr r0
473 ld r2, STK_GOT(r1)
474
475 /* Load CPU's default DSCR */
476 ld r0, PACA_DSCR_DEFAULT(r13)
477 mtspr SPRN_DSCR, r0
478
479 blr
480
481 /* ****************************************************************** */
1/*
2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
4 *
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
6 */
7
8#include <asm/asm-offsets.h>
9#include <asm/ppc_asm.h>
10#include <asm/ppc-opcode.h>
11#include <asm/ptrace.h>
12#include <asm/reg.h>
13
14#ifdef CONFIG_VSX
15/* See fpu.S, this is borrowed from there */
16#define __SAVE_32FPRS_VSRS(n,c,base) \
17BEGIN_FTR_SECTION \
18 b 2f; \
19END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
20 SAVE_32FPRS(n,base); \
21 b 3f; \
222: SAVE_32VSRS(n,c,base); \
233:
24#define __REST_32FPRS_VSRS(n,c,base) \
25BEGIN_FTR_SECTION \
26 b 2f; \
27END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
28 REST_32FPRS(n,base); \
29 b 3f; \
302: REST_32VSRS(n,c,base); \
313:
32#else
33#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
34#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
35#endif
36#define SAVE_32FPRS_VSRS(n,c,base) \
37 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
38#define REST_32FPRS_VSRS(n,c,base) \
39 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
40
41/* Stack frame offsets for local variables. */
42#define TM_FRAME_L0 TM_FRAME_SIZE-16
43#define TM_FRAME_L1 TM_FRAME_SIZE-8
44#define STACK_PARAM(x) (48+((x)*8))
45
46
47/* In order to access the TM SPRs, TM must be enabled. So, do so: */
48_GLOBAL(tm_enable)
49 mfmsr r4
50 li r3, MSR_TM >> 32
51 sldi r3, r3, 32
52 and. r0, r4, r3
53 bne 1f
54 or r4, r4, r3
55 mtmsrd r4
561: blr
57
58_GLOBAL(tm_save_sprs)
59 mfspr r0, SPRN_TFHAR
60 std r0, THREAD_TM_TFHAR(r3)
61 mfspr r0, SPRN_TEXASR
62 std r0, THREAD_TM_TEXASR(r3)
63 mfspr r0, SPRN_TFIAR
64 std r0, THREAD_TM_TFIAR(r3)
65 blr
66
67_GLOBAL(tm_restore_sprs)
68 ld r0, THREAD_TM_TFHAR(r3)
69 mtspr SPRN_TFHAR, r0
70 ld r0, THREAD_TM_TEXASR(r3)
71 mtspr SPRN_TEXASR, r0
72 ld r0, THREAD_TM_TFIAR(r3)
73 mtspr SPRN_TFIAR, r0
74 blr
75
76 /* Passed an 8-bit failure cause as first argument. */
77_GLOBAL(tm_abort)
78 TABORT(R3)
79 blr
80
81 .section ".toc","aw"
82DSCR_DEFAULT:
83 .tc dscr_default[TC],dscr_default
84
85 .section ".text"
86
87/* void tm_reclaim(struct thread_struct *thread,
88 * unsigned long orig_msr,
89 * uint8_t cause)
90 *
91 * - Performs a full reclaim. This destroys outstanding
92 * transactions and updates thread->regs.tm_ckpt_* with the
93 * original checkpointed state. Note that thread->regs is
94 * unchanged.
95 * - FP regs are written back to thread->transact_fpr before
96 * reclaiming. These are the transactional (current) versions.
97 *
98 * Purpose is to both abort transactions of, and preserve the state of,
99 * a transactions at a context switch. We preserve/restore both sets of process
100 * state to restore them when the thread's scheduled again. We continue in
101 * userland as though nothing happened, but when the transaction is resumed
102 * they will abort back to the checkpointed state we save out here.
103 *
104 * Call with IRQs off, stacks get all out of sync for some periods in here!
105 */
106_GLOBAL(tm_reclaim)
107 mfcr r6
108 mflr r0
109 stw r6, 8(r1)
110 std r0, 16(r1)
111 std r2, 40(r1)
112 stdu r1, -TM_FRAME_SIZE(r1)
113
114 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
115
116 std r3, STACK_PARAM(0)(r1)
117 SAVE_NVGPRS(r1)
118
119 /* We need to setup MSR for VSX register save instructions. Here we
120 * also clear the MSR RI since when we do the treclaim, we won't have a
121 * valid kernel pointer for a while. We clear RI here as it avoids
122 * adding another mtmsr closer to the treclaim. This makes the region
123 * maked as non-recoverable wider than it needs to be but it saves on
124 * inserting another mtmsrd later.
125 */
126 mfmsr r14
127 mr r15, r14
128 ori r15, r15, MSR_FP
129 li r16, MSR_RI
130 ori r16, r16, MSR_EE /* IRQs hard off */
131 andc r15, r15, r16
132 oris r15, r15, MSR_VEC@h
133#ifdef CONFIG_VSX
134 BEGIN_FTR_SECTION
135 oris r15,r15, MSR_VSX@h
136 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
137#endif
138 mtmsrd r15
139 std r14, TM_FRAME_L0(r1)
140
141 /* Stash the stack pointer away for use after reclaim */
142 std r1, PACAR1(r13)
143
144 /* ******************** FPR/VR/VSRs ************
145 * Before reclaiming, capture the current/transactional FPR/VR
146 * versions /if used/.
147 *
148 * (If VSX used, FP and VMX are implied. Or, we don't need to look
149 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
150 *
151 * We're passed the thread's MSR as parameter 2.
152 *
153 * We enabled VEC/FP/VSX in the msr above, so we can execute these
154 * instructions!
155 */
156 andis. r0, r4, MSR_VEC@h
157 beq dont_backup_vec
158
159 addi r7, r3, THREAD_TRANSACT_VRSTATE
160 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
161 mfvscr vr0
162 li r6, VRSTATE_VSCR
163 stvx vr0, r7, r6
164dont_backup_vec:
165 mfspr r0, SPRN_VRSAVE
166 std r0, THREAD_TRANSACT_VRSAVE(r3)
167
168 andi. r0, r4, MSR_FP
169 beq dont_backup_fp
170
171 addi r7, r3, THREAD_TRANSACT_FPSTATE
172 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
173
174 mffs fr0
175 stfd fr0,FPSTATE_FPSCR(r7)
176
177dont_backup_fp:
178 /* The moment we treclaim, ALL of our GPRs will switch
179 * to user register state. (FPRs, CCR etc. also!)
180 * Use an sprg and a tm_scratch in the PACA to shuffle.
181 */
182 TRECLAIM(R5) /* Cause in r5 */
183
184 /* ******************** GPRs ******************** */
185 /* Stash the checkpointed r13 away in the scratch SPR and get the real
186 * paca
187 */
188 SET_SCRATCH0(r13)
189 GET_PACA(r13)
190
191 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
192 * stack pointer back
193 */
194 std r1, PACATMSCRATCH(r13)
195 ld r1, PACAR1(r13)
196
197 /* Store the PPR in r11 and reset to decent value */
198 std r11, GPR11(r1) /* Temporary stash */
199 mfspr r11, SPRN_PPR
200 HMT_MEDIUM
201
202 /* Now get some more GPRS free */
203 std r7, GPR7(r1) /* Temporary stash */
204 std r12, GPR12(r1) /* '' '' '' */
205 ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */
206
207 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
208
209 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
210
211 /* Make r7 look like an exception frame so that we
212 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
213 */
214 subi r7, r7, STACK_FRAME_OVERHEAD
215
216 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
217 SAVE_GPR(0, r7) /* user r0 */
218 SAVE_GPR(2, r7) /* user r2 */
219 SAVE_4GPRS(3, r7) /* user r3-r6 */
220 SAVE_GPR(8, r7) /* user r8 */
221 SAVE_GPR(9, r7) /* user r9 */
222 SAVE_GPR(10, r7) /* user r10 */
223 ld r3, PACATMSCRATCH(r13) /* user r1 */
224 ld r4, GPR7(r1) /* user r7 */
225 ld r5, GPR11(r1) /* user r11 */
226 ld r6, GPR12(r1) /* user r12 */
227 GET_SCRATCH0(8) /* user r13 */
228 std r3, GPR1(r7)
229 std r4, GPR7(r7)
230 std r5, GPR11(r7)
231 std r6, GPR12(r7)
232 std r8, GPR13(r7)
233
234 SAVE_NVGPRS(r7) /* user r14-r31 */
235
236 /* ******************** NIP ******************** */
237 mfspr r3, SPRN_TFHAR
238 std r3, _NIP(r7) /* Returns to failhandler */
239 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
240 * but is used in signal return to 'wind back' to the abort handler.
241 */
242
243 /* ******************** CR,LR,CCR,MSR ********** */
244 mfctr r3
245 mflr r4
246 mfcr r5
247 mfxer r6
248
249 std r3, _CTR(r7)
250 std r4, _LINK(r7)
251 std r5, _CCR(r7)
252 std r6, _XER(r7)
253
254
255 /* ******************** TAR, DSCR ********** */
256 mfspr r3, SPRN_TAR
257 mfspr r4, SPRN_DSCR
258
259 std r3, THREAD_TM_TAR(r12)
260 std r4, THREAD_TM_DSCR(r12)
261
262 /* MSR and flags: We don't change CRs, and we don't need to alter
263 * MSR.
264 */
265
266 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
267 * been updated by the treclaim, to explain to userland the failure
268 * cause (aborted).
269 */
270 mfspr r0, SPRN_TEXASR
271 mfspr r3, SPRN_TFHAR
272 mfspr r4, SPRN_TFIAR
273 std r0, THREAD_TM_TEXASR(r12)
274 std r3, THREAD_TM_TFHAR(r12)
275 std r4, THREAD_TM_TFIAR(r12)
276
277 /* AMR is checkpointed too, but is unsupported by Linux. */
278
279 /* Restore original MSR/IRQ state & clear TM mode */
280 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
281 li r15, 0
282 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
283 mtmsrd r14
284
285 REST_NVGPRS(r1)
286
287 addi r1, r1, TM_FRAME_SIZE
288 lwz r4, 8(r1)
289 ld r0, 16(r1)
290 mtcr r4
291 mtlr r0
292 ld r2, 40(r1)
293
294 /* Load system default DSCR */
295 ld r4, DSCR_DEFAULT@toc(r2)
296 ld r0, 0(r4)
297 mtspr SPRN_DSCR, r0
298
299 blr
300
301
302 /* void tm_recheckpoint(struct thread_struct *thread,
303 * unsigned long orig_msr)
304 * - Restore the checkpointed register state saved by tm_reclaim
305 * when we switch_to a process.
306 *
307 * Call with IRQs off, stacks get all out of sync for
308 * some periods in here!
309 */
310_GLOBAL(__tm_recheckpoint)
311 mfcr r5
312 mflr r0
313 stw r5, 8(r1)
314 std r0, 16(r1)
315 std r2, 40(r1)
316 stdu r1, -TM_FRAME_SIZE(r1)
317
318 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
319 * This is used for backing up the NVGPRs:
320 */
321 SAVE_NVGPRS(r1)
322
323 std r1, PACAR1(r13)
324
325 /* Load complete register state from ts_ckpt* registers */
326
327 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
328
329 /* Make r7 look like an exception frame so that we
330 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
331 */
332 subi r7, r7, STACK_FRAME_OVERHEAD
333
334 SET_SCRATCH0(r1)
335
336 mfmsr r6
337 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
338
339 /* Enable FP/vec in MSR if necessary! */
340 lis r5, MSR_VEC@h
341 ori r5, r5, MSR_FP
342 and. r5, r4, r5
343 beq restore_gprs /* if neither, skip both */
344
345#ifdef CONFIG_VSX
346 BEGIN_FTR_SECTION
347 oris r5, r5, MSR_VSX@h
348 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
349#endif
350 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
351 mtmsr r5
352
353#ifdef CONFIG_ALTIVEC
354 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
355 * and thread.vr[] respectively. The thread.transact_fpr[] version
356 * is more modern, and will be loaded subsequently by any FPUnavailable
357 * trap.
358 */
359 andis. r0, r4, MSR_VEC@h
360 beq dont_restore_vec
361
362 addi r8, r3, THREAD_VRSTATE
363 li r5, VRSTATE_VSCR
364 lvx vr0, r8, r5
365 mtvscr vr0
366 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
367dont_restore_vec:
368 ld r5, THREAD_VRSAVE(r3)
369 mtspr SPRN_VRSAVE, r5
370#endif
371
372 andi. r0, r4, MSR_FP
373 beq dont_restore_fp
374
375 addi r8, r3, THREAD_FPSTATE
376 lfd fr0, FPSTATE_FPSCR(r8)
377 MTFSF_L(fr0)
378 REST_32FPRS_VSRS(0, R4, R8)
379
380dont_restore_fp:
381 mtmsr r6 /* FP/Vec off again! */
382
383restore_gprs:
384
385 /* ******************** CR,LR,CCR,MSR ********** */
386 ld r4, _CTR(r7)
387 ld r5, _LINK(r7)
388 ld r6, _CCR(r7)
389 ld r8, _XER(r7)
390
391 mtctr r4
392 mtlr r5
393 mtcr r6
394 mtxer r8
395
396 /* ******************** TAR ******************** */
397 ld r4, THREAD_TM_TAR(r3)
398 mtspr SPRN_TAR, r4
399
400 /* Load up the PPR and DSCR in GPRs only at this stage */
401 ld r5, THREAD_TM_DSCR(r3)
402 ld r6, THREAD_TM_PPR(r3)
403
404 /* Clear the MSR RI since we are about to change R1. EE is already off
405 */
406 li r4, 0
407 mtmsrd r4, 1
408
409 REST_4GPRS(0, r7) /* GPR0-3 */
410 REST_GPR(4, r7) /* GPR4 */
411 REST_4GPRS(8, r7) /* GPR8-11 */
412 REST_2GPRS(12, r7) /* GPR12-13 */
413
414 REST_NVGPRS(r7) /* GPR14-31 */
415
416 /* Load up PPR and DSCR here so we don't run with user values for long
417 */
418 mtspr SPRN_DSCR, r5
419 mtspr SPRN_PPR, r6
420
421 REST_GPR(5, r7) /* GPR5-7 */
422 REST_GPR(6, r7)
423 ld r7, GPR7(r7)
424
425 /* Commit register state as checkpointed state: */
426 TRECHKPT
427
428 HMT_MEDIUM
429
430 /* Our transactional state has now changed.
431 *
432 * Now just get out of here. Transactional (current) state will be
433 * updated once restore is called on the return path in the _switch-ed
434 * -to process.
435 */
436
437 GET_PACA(r13)
438 GET_SCRATCH0(r1)
439
440 /* R1 is restored, so we are recoverable again. EE is still off */
441 li r4, MSR_RI
442 mtmsrd r4, 1
443
444 REST_NVGPRS(r1)
445
446 addi r1, r1, TM_FRAME_SIZE
447 lwz r4, 8(r1)
448 ld r0, 16(r1)
449 mtcr r4
450 mtlr r0
451 ld r2, 40(r1)
452
453 /* Load system default DSCR */
454 ld r4, DSCR_DEFAULT@toc(r2)
455 ld r0, 0(r4)
456 mtspr SPRN_DSCR, r0
457
458 blr
459
460 /* ****************************************************************** */