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1/*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_POWERPC_OPAL_H
13#define _ASM_POWERPC_OPAL_H
14
15#include <asm/opal-api.h>
16
17#ifndef __ASSEMBLY__
18
19#include <linux/notifier.h>
20
21/* We calculate number of sg entries based on PAGE_SIZE */
22#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
23
24/* /sys/firmware/opal */
25extern struct kobject *opal_kobj;
26
27/* /ibm,opal */
28extern struct device_node *opal_node;
29
30/* API functions */
31int64_t opal_invalid_call(void);
32int64_t opal_console_write(int64_t term_number, __be64 *length,
33 const uint8_t *buffer);
34int64_t opal_console_read(int64_t term_number, __be64 *length,
35 uint8_t *buffer);
36int64_t opal_console_write_buffer_space(int64_t term_number,
37 __be64 *length);
38int64_t opal_console_flush(int64_t term_number);
39int64_t opal_rtc_read(__be32 *year_month_day,
40 __be64 *hour_minute_second_millisecond);
41int64_t opal_rtc_write(uint32_t year_month_day,
42 uint64_t hour_minute_second_millisecond);
43int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
44int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
45 uint32_t hour_min);
46int64_t opal_cec_power_down(uint64_t request);
47int64_t opal_cec_reboot(void);
48int64_t opal_cec_reboot2(uint32_t reboot_type, char *diag);
49int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
50int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
51int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
52int64_t opal_poll_events(__be64 *outstanding_event_mask);
53int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
54 uint64_t tce_mem_size);
55int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
56 uint64_t tce_mem_size);
57int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
58 uint64_t offset, uint8_t *data);
59int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
60 uint64_t offset, __be16 *data);
61int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
62 uint64_t offset, __be32 *data);
63int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
64 uint64_t offset, uint8_t data);
65int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
66 uint64_t offset, uint16_t data);
67int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
68 uint64_t offset, uint32_t data);
69int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
70int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
71int64_t opal_register_exception_handler(uint64_t opal_exception,
72 uint64_t handler_address,
73 uint64_t glue_cache_line);
74int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
75 uint8_t *freeze_state,
76 __be16 *pci_error_type,
77 __be64 *phb_status);
78int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
79 uint64_t eeh_action_token);
80int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
81 uint64_t eeh_action_token);
82int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
83 uint32_t func, uint64_t addr, uint64_t mask);
84int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
85
86
87
88int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
89 uint16_t window_num, uint16_t enable);
90int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
91 uint16_t window_num,
92 uint64_t starting_real_address,
93 uint64_t starting_pci_address,
94 uint64_t size);
95int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
96 uint16_t window_type, uint16_t window_num,
97 uint16_t segment_num);
98int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
99 uint64_t ivt_addr, uint64_t ivt_len,
100 uint64_t reject_array_addr,
101 uint64_t peltv_addr);
102int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
103 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
104 uint8_t pe_action);
105int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
106 uint8_t state);
107int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
108int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
109 uint32_t state);
110int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
111 uint8_t *p_bit, uint8_t *q_bit);
112int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
113 uint8_t p_bit, uint8_t q_bit);
114int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
115int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
116 uint32_t xive_num);
117int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
118 __be32 *interrupt_source_number);
119int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
120 uint8_t msi_range, __be32 *msi_address,
121 __be32 *message_data);
122int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
123 uint32_t xive_num, uint8_t msi_range,
124 __be64 *msi_address, __be32 *message_data);
125int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
126int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
127int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
128int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
129 uint16_t tce_levels, uint64_t tce_table_addr,
130 uint64_t tce_table_size, uint64_t tce_page_size);
131int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
132 uint16_t dma_window_number, uint64_t pci_start_addr,
133 uint64_t pci_mem_size);
134int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
135
136int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
137 uint64_t diag_buffer_len);
138int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
139 uint64_t diag_buffer_len);
140int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
141 uint64_t diag_buffer_len);
142int64_t opal_pci_fence_phb(uint64_t phb_id);
143int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
144int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
145int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
146int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
147int64_t opal_get_dpo_status(__be64 *dpo_timeout);
148int64_t opal_set_system_attention_led(uint8_t led_action);
149int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
150 __be16 *pci_error_type, __be16 *severity);
151int64_t opal_pci_poll(uint64_t phb_id);
152int64_t opal_return_cpu(void);
153int64_t opal_check_token(uint64_t token);
154int64_t opal_reinit_cpus(uint64_t flags);
155
156int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
157int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
158
159int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
160 uint32_t addr, uint32_t data, uint32_t sz);
161int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
162 uint32_t addr, __be32 *data, uint32_t sz);
163
164int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
165int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
166int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
167int64_t opal_send_ack_elog(uint64_t log_id);
168void opal_resend_pending_logs(void);
169
170int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
171int64_t opal_manage_flash(uint8_t op);
172int64_t opal_update_flash(uint64_t blk_list);
173int64_t opal_dump_init(uint8_t dump_type);
174int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
175int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
176int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
177int64_t opal_dump_ack(uint32_t dump_id);
178int64_t opal_dump_resend_notification(void);
179
180int64_t opal_get_msg(uint64_t buffer, uint64_t size);
181int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
182int64_t opal_sync_host_reboot(void);
183int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
184 uint64_t length);
185int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
186 uint64_t length);
187int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
188int64_t opal_handle_hmi(void);
189int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
190int64_t opal_unregister_dump_region(uint32_t id);
191int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
192int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
193int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
194int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
195 uint64_t msg_len);
196int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
197 uint64_t *msg_len);
198int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
199 struct opal_i2c_request *oreq);
200int64_t opal_prd_msg(struct opal_prd_msg *msg);
201int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
202 __be64 *led_value, __be64 *max_led_type);
203int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
204 const u64 led_value, __be64 *max_led_type);
205
206int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
207 uint64_t size, uint64_t token);
208int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
209 uint64_t size, uint64_t token);
210int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
211 uint64_t token);
212
213/* Internal functions */
214extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
215 int depth, void *data);
216extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
217 const char *uname, int depth, void *data);
218
219extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
220extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
221
222extern void hvc_opal_init_early(void);
223
224extern int opal_notifier_register(struct notifier_block *nb);
225extern int opal_notifier_unregister(struct notifier_block *nb);
226
227extern int opal_message_notifier_register(enum opal_msg_type msg_type,
228 struct notifier_block *nb);
229extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
230 struct notifier_block *nb);
231extern void opal_notifier_enable(void);
232extern void opal_notifier_disable(void);
233extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
234
235extern int __opal_async_get_token(void);
236extern int opal_async_get_token_interruptible(void);
237extern int __opal_async_release_token(int token);
238extern int opal_async_release_token(int token);
239extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
240extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
241
242struct rtc_time;
243extern unsigned long opal_get_boot_time(void);
244extern void opal_nvram_init(void);
245extern void opal_flash_update_init(void);
246extern void opal_flash_term_callback(void);
247extern int opal_elog_init(void);
248extern void opal_platform_dump_init(void);
249extern void opal_sys_param_init(void);
250extern void opal_msglog_init(void);
251extern void opal_msglog_sysfs_init(void);
252extern int opal_async_comp_init(void);
253extern int opal_sensor_init(void);
254extern int opal_hmi_handler_init(void);
255extern int opal_event_init(void);
256
257extern int opal_machine_check(struct pt_regs *regs);
258extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
259extern int opal_hmi_exception_early(struct pt_regs *regs);
260extern int opal_handle_hmi_exception(struct pt_regs *regs);
261
262extern void opal_shutdown(void);
263extern int opal_resync_timebase(void);
264
265extern void opal_lpc_init(void);
266
267extern void opal_kmsg_init(void);
268
269extern int opal_event_request(unsigned int opal_event_nr);
270
271struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
272 unsigned long vmalloc_size);
273void opal_free_sg_list(struct opal_sg_list *sg);
274
275extern int opal_error_code(int rc);
276
277ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
278
279#endif /* __ASSEMBLY__ */
280
281#endif /* _ASM_POWERPC_OPAL_H */
1/*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __OPAL_H
13#define __OPAL_H
14
15/****** Takeover interface ********/
16
17/* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23#ifndef __ASSEMBLY__
24
25struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34};
35
36/*
37 * SG entry
38 *
39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well.
42 */
43struct opal_sg_entry {
44 __be64 data;
45 __be64 length;
46};
47
48/* SG list */
49struct opal_sg_list {
50 __be64 length;
51 __be64 next;
52 struct opal_sg_entry entry[];
53};
54
55/* We calculate number of sg entries based on PAGE_SIZE */
56#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
57
58extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
59
60extern long opal_do_takeover(struct opal_takeover_args *args);
61
62struct rtas_args;
63extern int opal_enter_rtas(struct rtas_args *args,
64 unsigned long data,
65 unsigned long entry);
66
67#endif /* __ASSEMBLY__ */
68
69/****** OPAL APIs ******/
70
71/* Return codes */
72#define OPAL_SUCCESS 0
73#define OPAL_PARAMETER -1
74#define OPAL_BUSY -2
75#define OPAL_PARTIAL -3
76#define OPAL_CONSTRAINED -4
77#define OPAL_CLOSED -5
78#define OPAL_HARDWARE -6
79#define OPAL_UNSUPPORTED -7
80#define OPAL_PERMISSION -8
81#define OPAL_NO_MEM -9
82#define OPAL_RESOURCE -10
83#define OPAL_INTERNAL_ERROR -11
84#define OPAL_BUSY_EVENT -12
85#define OPAL_HARDWARE_FROZEN -13
86#define OPAL_WRONG_STATE -14
87#define OPAL_ASYNC_COMPLETION -15
88
89/* API Tokens (in r0) */
90#define OPAL_INVALID_CALL -1
91#define OPAL_CONSOLE_WRITE 1
92#define OPAL_CONSOLE_READ 2
93#define OPAL_RTC_READ 3
94#define OPAL_RTC_WRITE 4
95#define OPAL_CEC_POWER_DOWN 5
96#define OPAL_CEC_REBOOT 6
97#define OPAL_READ_NVRAM 7
98#define OPAL_WRITE_NVRAM 8
99#define OPAL_HANDLE_INTERRUPT 9
100#define OPAL_POLL_EVENTS 10
101#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
102#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
103#define OPAL_PCI_CONFIG_READ_BYTE 13
104#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
105#define OPAL_PCI_CONFIG_READ_WORD 15
106#define OPAL_PCI_CONFIG_WRITE_BYTE 16
107#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
108#define OPAL_PCI_CONFIG_WRITE_WORD 18
109#define OPAL_SET_XIVE 19
110#define OPAL_GET_XIVE 20
111#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
112#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
113#define OPAL_PCI_EEH_FREEZE_STATUS 23
114#define OPAL_PCI_SHPC 24
115#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
116#define OPAL_PCI_EEH_FREEZE_CLEAR 26
117#define OPAL_PCI_PHB_MMIO_ENABLE 27
118#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
119#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
120#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
121#define OPAL_PCI_SET_PE 31
122#define OPAL_PCI_SET_PELTV 32
123#define OPAL_PCI_SET_MVE 33
124#define OPAL_PCI_SET_MVE_ENABLE 34
125#define OPAL_PCI_GET_XIVE_REISSUE 35
126#define OPAL_PCI_SET_XIVE_REISSUE 36
127#define OPAL_PCI_SET_XIVE_PE 37
128#define OPAL_GET_XIVE_SOURCE 38
129#define OPAL_GET_MSI_32 39
130#define OPAL_GET_MSI_64 40
131#define OPAL_START_CPU 41
132#define OPAL_QUERY_CPU_STATUS 42
133#define OPAL_WRITE_OPPANEL 43
134#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
135#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
136#define OPAL_PCI_RESET 49
137#define OPAL_PCI_GET_HUB_DIAG_DATA 50
138#define OPAL_PCI_GET_PHB_DIAG_DATA 51
139#define OPAL_PCI_FENCE_PHB 52
140#define OPAL_PCI_REINIT 53
141#define OPAL_PCI_MASK_PE_ERROR 54
142#define OPAL_SET_SLOT_LED_STATUS 55
143#define OPAL_GET_EPOW_STATUS 56
144#define OPAL_SET_SYSTEM_ATTENTION_LED 57
145#define OPAL_RESERVED1 58
146#define OPAL_RESERVED2 59
147#define OPAL_PCI_NEXT_ERROR 60
148#define OPAL_PCI_EEH_FREEZE_STATUS2 61
149#define OPAL_PCI_POLL 62
150#define OPAL_PCI_MSI_EOI 63
151#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
152#define OPAL_XSCOM_READ 65
153#define OPAL_XSCOM_WRITE 66
154#define OPAL_LPC_READ 67
155#define OPAL_LPC_WRITE 68
156#define OPAL_RETURN_CPU 69
157#define OPAL_ELOG_READ 71
158#define OPAL_ELOG_WRITE 72
159#define OPAL_ELOG_ACK 73
160#define OPAL_ELOG_RESEND 74
161#define OPAL_ELOG_SIZE 75
162#define OPAL_FLASH_VALIDATE 76
163#define OPAL_FLASH_MANAGE 77
164#define OPAL_FLASH_UPDATE 78
165#define OPAL_RESYNC_TIMEBASE 79
166#define OPAL_DUMP_INIT 81
167#define OPAL_DUMP_INFO 82
168#define OPAL_DUMP_READ 83
169#define OPAL_DUMP_ACK 84
170#define OPAL_GET_MSG 85
171#define OPAL_CHECK_ASYNC_COMPLETION 86
172#define OPAL_SYNC_HOST_REBOOT 87
173#define OPAL_SENSOR_READ 88
174#define OPAL_GET_PARAM 89
175#define OPAL_SET_PARAM 90
176#define OPAL_DUMP_RESEND 91
177#define OPAL_DUMP_INFO2 94
178
179#ifndef __ASSEMBLY__
180
181#include <linux/notifier.h>
182
183/* Other enums */
184enum OpalVendorApiTokens {
185 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
186};
187
188enum OpalFreezeState {
189 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
190 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
191 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
192 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
193 OPAL_EEH_STOPPED_RESET = 4,
194 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
195 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
196};
197
198enum OpalEehFreezeActionToken {
199 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
200 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
201 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
202};
203
204enum OpalPciStatusToken {
205 OPAL_EEH_NO_ERROR = 0,
206 OPAL_EEH_IOC_ERROR = 1,
207 OPAL_EEH_PHB_ERROR = 2,
208 OPAL_EEH_PE_ERROR = 3,
209 OPAL_EEH_PE_MMIO_ERROR = 4,
210 OPAL_EEH_PE_DMA_ERROR = 5
211};
212
213enum OpalPciErrorSeverity {
214 OPAL_EEH_SEV_NO_ERROR = 0,
215 OPAL_EEH_SEV_IOC_DEAD = 1,
216 OPAL_EEH_SEV_PHB_DEAD = 2,
217 OPAL_EEH_SEV_PHB_FENCED = 3,
218 OPAL_EEH_SEV_PE_ER = 4,
219 OPAL_EEH_SEV_INF = 5
220};
221
222enum OpalShpcAction {
223 OPAL_SHPC_GET_LINK_STATE = 0,
224 OPAL_SHPC_GET_SLOT_STATE = 1
225};
226
227enum OpalShpcLinkState {
228 OPAL_SHPC_LINK_DOWN = 0,
229 OPAL_SHPC_LINK_UP = 1
230};
231
232enum OpalMmioWindowType {
233 OPAL_M32_WINDOW_TYPE = 1,
234 OPAL_M64_WINDOW_TYPE = 2,
235 OPAL_IO_WINDOW_TYPE = 3
236};
237
238enum OpalShpcSlotState {
239 OPAL_SHPC_DEV_NOT_PRESENT = 0,
240 OPAL_SHPC_DEV_PRESENT = 1
241};
242
243enum OpalExceptionHandler {
244 OPAL_MACHINE_CHECK_HANDLER = 1,
245 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
246 OPAL_SOFTPATCH_HANDLER = 3
247};
248
249enum OpalPendingState {
250 OPAL_EVENT_OPAL_INTERNAL = 0x1,
251 OPAL_EVENT_NVRAM = 0x2,
252 OPAL_EVENT_RTC = 0x4,
253 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
254 OPAL_EVENT_CONSOLE_INPUT = 0x10,
255 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
256 OPAL_EVENT_ERROR_LOG = 0x40,
257 OPAL_EVENT_EPOW = 0x80,
258 OPAL_EVENT_LED_STATUS = 0x100,
259 OPAL_EVENT_PCI_ERROR = 0x200,
260 OPAL_EVENT_DUMP_AVAIL = 0x400,
261 OPAL_EVENT_MSG_PENDING = 0x800,
262};
263
264enum OpalMessageType {
265 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
266 * additional params function-specific
267 */
268 OPAL_MSG_MEM_ERR,
269 OPAL_MSG_EPOW,
270 OPAL_MSG_SHUTDOWN,
271 OPAL_MSG_TYPE_MAX,
272};
273
274/* Machine check related definitions */
275enum OpalMCE_Version {
276 OpalMCE_V1 = 1,
277};
278
279enum OpalMCE_Severity {
280 OpalMCE_SEV_NO_ERROR = 0,
281 OpalMCE_SEV_WARNING = 1,
282 OpalMCE_SEV_ERROR_SYNC = 2,
283 OpalMCE_SEV_FATAL = 3,
284};
285
286enum OpalMCE_Disposition {
287 OpalMCE_DISPOSITION_RECOVERED = 0,
288 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
289};
290
291enum OpalMCE_Initiator {
292 OpalMCE_INITIATOR_UNKNOWN = 0,
293 OpalMCE_INITIATOR_CPU = 1,
294};
295
296enum OpalMCE_ErrorType {
297 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
298 OpalMCE_ERROR_TYPE_UE = 1,
299 OpalMCE_ERROR_TYPE_SLB = 2,
300 OpalMCE_ERROR_TYPE_ERAT = 3,
301 OpalMCE_ERROR_TYPE_TLB = 4,
302};
303
304enum OpalMCE_UeErrorType {
305 OpalMCE_UE_ERROR_INDETERMINATE = 0,
306 OpalMCE_UE_ERROR_IFETCH = 1,
307 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
308 OpalMCE_UE_ERROR_LOAD_STORE = 3,
309 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
310};
311
312enum OpalMCE_SlbErrorType {
313 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
314 OpalMCE_SLB_ERROR_PARITY = 1,
315 OpalMCE_SLB_ERROR_MULTIHIT = 2,
316};
317
318enum OpalMCE_EratErrorType {
319 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
320 OpalMCE_ERAT_ERROR_PARITY = 1,
321 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
322};
323
324enum OpalMCE_TlbErrorType {
325 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
326 OpalMCE_TLB_ERROR_PARITY = 1,
327 OpalMCE_TLB_ERROR_MULTIHIT = 2,
328};
329
330enum OpalThreadStatus {
331 OPAL_THREAD_INACTIVE = 0x0,
332 OPAL_THREAD_STARTED = 0x1,
333 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
334};
335
336enum OpalPciBusCompare {
337 OpalPciBusAny = 0, /* Any bus number match */
338 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
339 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
340 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
341 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
342 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
343 OpalPciBusAll = 7, /* Match bus number exactly */
344};
345
346enum OpalDeviceCompare {
347 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
348 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
349};
350
351enum OpalFuncCompare {
352 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
353 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
354};
355
356enum OpalPeAction {
357 OPAL_UNMAP_PE = 0,
358 OPAL_MAP_PE = 1
359};
360
361enum OpalPeltvAction {
362 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
363 OPAL_ADD_PE_TO_DOMAIN = 1
364};
365
366enum OpalMveEnableAction {
367 OPAL_DISABLE_MVE = 0,
368 OPAL_ENABLE_MVE = 1
369};
370
371enum OpalPciResetScope {
372 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
373 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
374 OPAL_PCI_IODA_TABLE_RESET = 6,
375};
376
377enum OpalPciReinitScope {
378 OPAL_REINIT_PCI_DEV = 1000
379};
380
381enum OpalPciResetState {
382 OPAL_DEASSERT_RESET = 0,
383 OPAL_ASSERT_RESET = 1
384};
385
386enum OpalPciMaskAction {
387 OPAL_UNMASK_ERROR_TYPE = 0,
388 OPAL_MASK_ERROR_TYPE = 1
389};
390
391enum OpalSlotLedType {
392 OPAL_SLOT_LED_ID_TYPE = 0,
393 OPAL_SLOT_LED_FAULT_TYPE = 1
394};
395
396enum OpalLedAction {
397 OPAL_TURN_OFF_LED = 0,
398 OPAL_TURN_ON_LED = 1,
399 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
400};
401
402enum OpalEpowStatus {
403 OPAL_EPOW_NONE = 0,
404 OPAL_EPOW_UPS = 1,
405 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
406 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
407};
408
409/*
410 * Address cycle types for LPC accesses. These also correspond
411 * to the content of the first cell of the "reg" property for
412 * device nodes on the LPC bus
413 */
414enum OpalLPCAddressType {
415 OPAL_LPC_MEM = 0,
416 OPAL_LPC_IO = 1,
417 OPAL_LPC_FW = 2,
418};
419
420/* System parameter permission */
421enum OpalSysparamPerm {
422 OPAL_SYSPARAM_READ = 0x1,
423 OPAL_SYSPARAM_WRITE = 0x2,
424 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
425};
426
427struct opal_msg {
428 __be32 msg_type;
429 __be32 reserved;
430 __be64 params[8];
431};
432
433struct opal_machine_check_event {
434 enum OpalMCE_Version version:8; /* 0x00 */
435 uint8_t in_use; /* 0x01 */
436 enum OpalMCE_Severity severity:8; /* 0x02 */
437 enum OpalMCE_Initiator initiator:8; /* 0x03 */
438 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
439 enum OpalMCE_Disposition disposition:8; /* 0x05 */
440 uint8_t reserved_1[2]; /* 0x06 */
441 uint64_t gpr3; /* 0x08 */
442 uint64_t srr0; /* 0x10 */
443 uint64_t srr1; /* 0x18 */
444 union { /* 0x20 */
445 struct {
446 enum OpalMCE_UeErrorType ue_error_type:8;
447 uint8_t effective_address_provided;
448 uint8_t physical_address_provided;
449 uint8_t reserved_1[5];
450 uint64_t effective_address;
451 uint64_t physical_address;
452 uint8_t reserved_2[8];
453 } ue_error;
454
455 struct {
456 enum OpalMCE_SlbErrorType slb_error_type:8;
457 uint8_t effective_address_provided;
458 uint8_t reserved_1[6];
459 uint64_t effective_address;
460 uint8_t reserved_2[16];
461 } slb_error;
462
463 struct {
464 enum OpalMCE_EratErrorType erat_error_type:8;
465 uint8_t effective_address_provided;
466 uint8_t reserved_1[6];
467 uint64_t effective_address;
468 uint8_t reserved_2[16];
469 } erat_error;
470
471 struct {
472 enum OpalMCE_TlbErrorType tlb_error_type:8;
473 uint8_t effective_address_provided;
474 uint8_t reserved_1[6];
475 uint64_t effective_address;
476 uint8_t reserved_2[16];
477 } tlb_error;
478 } u;
479};
480
481/* FSP memory errors handling */
482enum OpalMemErr_Version {
483 OpalMemErr_V1 = 1,
484};
485
486enum OpalMemErrType {
487 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
488 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
489 OPAL_MEM_ERR_TYPE_SCRUB,
490};
491
492/* Memory Reilience error type */
493enum OpalMemErr_ResilErrType {
494 OPAL_MEM_RESILIENCE_CE = 0,
495 OPAL_MEM_RESILIENCE_UE,
496 OPAL_MEM_RESILIENCE_UE_SCRUB,
497};
498
499/* Dynamic Memory Deallocation type */
500enum OpalMemErr_DynErrType {
501 OPAL_MEM_DYNAMIC_DEALLOC = 0,
502};
503
504/* OpalMemoryErrorData->flags */
505#define OPAL_MEM_CORRECTED_ERROR 0x0001
506#define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
507#define OPAL_MEM_ACK_REQUIRED 0x8000
508
509struct OpalMemoryErrorData {
510 enum OpalMemErr_Version version:8; /* 0x00 */
511 enum OpalMemErrType type:8; /* 0x01 */
512 uint16_t flags; /* 0x02 */
513 uint8_t reserved_1[4]; /* 0x04 */
514
515 union {
516 /* Memory Resilience corrected/uncorrected error info */
517 struct {
518 enum OpalMemErr_ResilErrType resil_err_type:8;
519 uint8_t reserved_1[7];
520 uint64_t physical_address_start;
521 uint64_t physical_address_end;
522 } resilience;
523 /* Dynamic memory deallocation error info */
524 struct {
525 enum OpalMemErr_DynErrType dyn_err_type:8;
526 uint8_t reserved_1[7];
527 uint64_t physical_address_start;
528 uint64_t physical_address_end;
529 } dyn_dealloc;
530 } u;
531};
532
533enum {
534 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
535 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
536 OPAL_P7IOC_DIAG_TYPE_BI = 2,
537 OPAL_P7IOC_DIAG_TYPE_CI = 3,
538 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
539 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
540 OPAL_P7IOC_DIAG_TYPE_LAST = 6
541};
542
543struct OpalIoP7IOCErrorData {
544 uint16_t type;
545
546 /* GEM */
547 uint64_t gemXfir;
548 uint64_t gemRfir;
549 uint64_t gemRirqfir;
550 uint64_t gemMask;
551 uint64_t gemRwof;
552
553 /* LEM */
554 uint64_t lemFir;
555 uint64_t lemErrMask;
556 uint64_t lemAction0;
557 uint64_t lemAction1;
558 uint64_t lemWof;
559
560 union {
561 struct OpalIoP7IOCRgcErrorData {
562 uint64_t rgcStatus; /* 3E1C10 */
563 uint64_t rgcLdcp; /* 3E1C18 */
564 }rgc;
565 struct OpalIoP7IOCBiErrorData {
566 uint64_t biLdcp0; /* 3C0100, 3C0118 */
567 uint64_t biLdcp1; /* 3C0108, 3C0120 */
568 uint64_t biLdcp2; /* 3C0110, 3C0128 */
569 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
570
571 uint8_t biDownbound; /* BI Downbound or Upbound */
572 }bi;
573 struct OpalIoP7IOCCiErrorData {
574 uint64_t ciPortStatus; /* 3Dn008 */
575 uint64_t ciPortLdcp; /* 3Dn010 */
576
577 uint8_t ciPort; /* Index of CI port: 0/1 */
578 }ci;
579 };
580};
581
582/**
583 * This structure defines the overlay which will be used to store PHB error
584 * data upon request.
585 */
586enum {
587 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
588};
589
590enum {
591 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
592 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
593};
594
595enum {
596 OPAL_P7IOC_NUM_PEST_REGS = 128,
597 OPAL_PHB3_NUM_PEST_REGS = 256
598};
599
600struct OpalIoPhbErrorCommon {
601 uint32_t version;
602 uint32_t ioType;
603 uint32_t len;
604};
605
606struct OpalIoP7IOCPhbErrorData {
607 struct OpalIoPhbErrorCommon common;
608
609 uint32_t brdgCtl;
610
611 // P7IOC utl regs
612 uint32_t portStatusReg;
613 uint32_t rootCmplxStatus;
614 uint32_t busAgentStatus;
615
616 // P7IOC cfg regs
617 uint32_t deviceStatus;
618 uint32_t slotStatus;
619 uint32_t linkStatus;
620 uint32_t devCmdStatus;
621 uint32_t devSecStatus;
622
623 // cfg AER regs
624 uint32_t rootErrorStatus;
625 uint32_t uncorrErrorStatus;
626 uint32_t corrErrorStatus;
627 uint32_t tlpHdr1;
628 uint32_t tlpHdr2;
629 uint32_t tlpHdr3;
630 uint32_t tlpHdr4;
631 uint32_t sourceId;
632
633 uint32_t rsv3;
634
635 // Record data about the call to allocate a buffer.
636 uint64_t errorClass;
637 uint64_t correlator;
638
639 //P7IOC MMIO Error Regs
640 uint64_t p7iocPlssr; // n120
641 uint64_t p7iocCsr; // n110
642 uint64_t lemFir; // nC00
643 uint64_t lemErrorMask; // nC18
644 uint64_t lemWOF; // nC40
645 uint64_t phbErrorStatus; // nC80
646 uint64_t phbFirstErrorStatus; // nC88
647 uint64_t phbErrorLog0; // nCC0
648 uint64_t phbErrorLog1; // nCC8
649 uint64_t mmioErrorStatus; // nD00
650 uint64_t mmioFirstErrorStatus; // nD08
651 uint64_t mmioErrorLog0; // nD40
652 uint64_t mmioErrorLog1; // nD48
653 uint64_t dma0ErrorStatus; // nD80
654 uint64_t dma0FirstErrorStatus; // nD88
655 uint64_t dma0ErrorLog0; // nDC0
656 uint64_t dma0ErrorLog1; // nDC8
657 uint64_t dma1ErrorStatus; // nE00
658 uint64_t dma1FirstErrorStatus; // nE08
659 uint64_t dma1ErrorLog0; // nE40
660 uint64_t dma1ErrorLog1; // nE48
661 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
662 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
663};
664
665struct OpalIoPhb3ErrorData {
666 struct OpalIoPhbErrorCommon common;
667
668 uint32_t brdgCtl;
669
670 /* PHB3 UTL regs */
671 uint32_t portStatusReg;
672 uint32_t rootCmplxStatus;
673 uint32_t busAgentStatus;
674
675 /* PHB3 cfg regs */
676 uint32_t deviceStatus;
677 uint32_t slotStatus;
678 uint32_t linkStatus;
679 uint32_t devCmdStatus;
680 uint32_t devSecStatus;
681
682 /* cfg AER regs */
683 uint32_t rootErrorStatus;
684 uint32_t uncorrErrorStatus;
685 uint32_t corrErrorStatus;
686 uint32_t tlpHdr1;
687 uint32_t tlpHdr2;
688 uint32_t tlpHdr3;
689 uint32_t tlpHdr4;
690 uint32_t sourceId;
691
692 uint32_t rsv3;
693
694 /* Record data about the call to allocate a buffer */
695 uint64_t errorClass;
696 uint64_t correlator;
697
698 uint64_t nFir; /* 000 */
699 uint64_t nFirMask; /* 003 */
700 uint64_t nFirWOF; /* 008 */
701
702 /* PHB3 MMIO Error Regs */
703 uint64_t phbPlssr; /* 120 */
704 uint64_t phbCsr; /* 110 */
705 uint64_t lemFir; /* C00 */
706 uint64_t lemErrorMask; /* C18 */
707 uint64_t lemWOF; /* C40 */
708 uint64_t phbErrorStatus; /* C80 */
709 uint64_t phbFirstErrorStatus; /* C88 */
710 uint64_t phbErrorLog0; /* CC0 */
711 uint64_t phbErrorLog1; /* CC8 */
712 uint64_t mmioErrorStatus; /* D00 */
713 uint64_t mmioFirstErrorStatus; /* D08 */
714 uint64_t mmioErrorLog0; /* D40 */
715 uint64_t mmioErrorLog1; /* D48 */
716 uint64_t dma0ErrorStatus; /* D80 */
717 uint64_t dma0FirstErrorStatus; /* D88 */
718 uint64_t dma0ErrorLog0; /* DC0 */
719 uint64_t dma0ErrorLog1; /* DC8 */
720 uint64_t dma1ErrorStatus; /* E00 */
721 uint64_t dma1FirstErrorStatus; /* E08 */
722 uint64_t dma1ErrorLog0; /* E40 */
723 uint64_t dma1ErrorLog1; /* E48 */
724 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
725 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
726};
727
728typedef struct oppanel_line {
729 const char * line;
730 uint64_t line_len;
731} oppanel_line_t;
732
733/* /sys/firmware/opal */
734extern struct kobject *opal_kobj;
735
736/* /ibm,opal */
737extern struct device_node *opal_node;
738
739/* API functions */
740int64_t opal_invalid_call(void);
741int64_t opal_console_write(int64_t term_number, __be64 *length,
742 const uint8_t *buffer);
743int64_t opal_console_read(int64_t term_number, __be64 *length,
744 uint8_t *buffer);
745int64_t opal_console_write_buffer_space(int64_t term_number,
746 __be64 *length);
747int64_t opal_rtc_read(__be32 *year_month_day,
748 __be64 *hour_minute_second_millisecond);
749int64_t opal_rtc_write(uint32_t year_month_day,
750 uint64_t hour_minute_second_millisecond);
751int64_t opal_cec_power_down(uint64_t request);
752int64_t opal_cec_reboot(void);
753int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
754int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
755int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
756int64_t opal_poll_events(__be64 *outstanding_event_mask);
757int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
758 uint64_t tce_mem_size);
759int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
760 uint64_t tce_mem_size);
761int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
762 uint64_t offset, uint8_t *data);
763int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
764 uint64_t offset, __be16 *data);
765int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
766 uint64_t offset, __be32 *data);
767int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
768 uint64_t offset, uint8_t data);
769int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
770 uint64_t offset, uint16_t data);
771int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
772 uint64_t offset, uint32_t data);
773int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
774int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
775int64_t opal_register_exception_handler(uint64_t opal_exception,
776 uint64_t handler_address,
777 uint64_t glue_cache_line);
778int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
779 uint8_t *freeze_state,
780 __be16 *pci_error_type,
781 __be64 *phb_status);
782int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
783 uint64_t eeh_action_token);
784int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
785
786
787
788int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
789 uint16_t window_num, uint16_t enable);
790int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
791 uint16_t window_num,
792 uint64_t starting_real_address,
793 uint64_t starting_pci_address,
794 uint16_t segment_size);
795int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
796 uint16_t window_type, uint16_t window_num,
797 uint16_t segment_num);
798int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
799 uint64_t ivt_addr, uint64_t ivt_len,
800 uint64_t reject_array_addr,
801 uint64_t peltv_addr);
802int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
803 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
804 uint8_t pe_action);
805int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
806 uint8_t state);
807int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
808int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
809 uint32_t state);
810int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
811 uint8_t *p_bit, uint8_t *q_bit);
812int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
813 uint8_t p_bit, uint8_t q_bit);
814int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
815int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
816 uint32_t xive_num);
817int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
818 __be32 *interrupt_source_number);
819int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
820 uint8_t msi_range, __be32 *msi_address,
821 __be32 *message_data);
822int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
823 uint32_t xive_num, uint8_t msi_range,
824 __be64 *msi_address, __be32 *message_data);
825int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
826int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
827int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
828int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
829 uint16_t tce_levels, uint64_t tce_table_addr,
830 uint64_t tce_table_size, uint64_t tce_page_size);
831int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
832 uint16_t dma_window_number, uint64_t pci_start_addr,
833 uint64_t pci_mem_size);
834int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
835
836int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
837 uint64_t diag_buffer_len);
838int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
839 uint64_t diag_buffer_len);
840int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
841 uint64_t diag_buffer_len);
842int64_t opal_pci_fence_phb(uint64_t phb_id);
843int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
844int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
845int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
846int64_t opal_get_epow_status(__be64 *status);
847int64_t opal_set_system_attention_led(uint8_t led_action);
848int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
849 uint16_t *pci_error_type, uint16_t *severity);
850int64_t opal_pci_poll(uint64_t phb_id);
851int64_t opal_return_cpu(void);
852
853int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
854int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
855
856int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
857 uint32_t addr, uint32_t data, uint32_t sz);
858int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
859 uint32_t addr, __be32 *data, uint32_t sz);
860
861int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
862int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
863int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
864int64_t opal_send_ack_elog(uint64_t log_id);
865void opal_resend_pending_logs(void);
866
867int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
868int64_t opal_manage_flash(uint8_t op);
869int64_t opal_update_flash(uint64_t blk_list);
870int64_t opal_dump_init(uint8_t dump_type);
871int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
872int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
873int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
874int64_t opal_dump_ack(uint32_t dump_id);
875int64_t opal_dump_resend_notification(void);
876
877int64_t opal_get_msg(uint64_t buffer, uint64_t size);
878int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
879int64_t opal_sync_host_reboot(void);
880int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
881 uint64_t length);
882int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
883 uint64_t length);
884int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
885
886/* Internal functions */
887extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
888 int depth, void *data);
889extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
890 const char *uname, int depth, void *data);
891
892extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
893extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
894
895extern void hvc_opal_init_early(void);
896
897extern int opal_notifier_register(struct notifier_block *nb);
898extern int opal_notifier_unregister(struct notifier_block *nb);
899
900extern int opal_message_notifier_register(enum OpalMessageType msg_type,
901 struct notifier_block *nb);
902extern void opal_notifier_enable(void);
903extern void opal_notifier_disable(void);
904extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
905
906extern int __opal_async_get_token(void);
907extern int opal_async_get_token_interruptible(void);
908extern int __opal_async_release_token(int token);
909extern int opal_async_release_token(int token);
910extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
911extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
912
913struct rtc_time;
914extern int opal_set_rtc_time(struct rtc_time *tm);
915extern void opal_get_rtc_time(struct rtc_time *tm);
916extern unsigned long opal_get_boot_time(void);
917extern void opal_nvram_init(void);
918extern void opal_flash_init(void);
919extern int opal_elog_init(void);
920extern void opal_platform_dump_init(void);
921extern void opal_sys_param_init(void);
922extern void opal_msglog_init(void);
923
924extern int opal_machine_check(struct pt_regs *regs);
925extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
926
927extern void opal_shutdown(void);
928extern int opal_resync_timebase(void);
929
930extern void opal_lpc_init(void);
931
932struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
933 unsigned long vmalloc_size);
934void opal_free_sg_list(struct opal_sg_list *sg);
935
936#endif /* __ASSEMBLY__ */
937
938#endif /* __OPAL_H */