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1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/prefetch.h>
22#include <linux/usb.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25#include <linux/device.h>
26#include <linux/platform_device.h>
27#include <linux/dma-mapping.h>
28#include <linux/usb/usb_phy_generic.h>
29
30#include "musb_core.h"
31
32struct tusb6010_glue {
33 struct device *dev;
34 struct platform_device *musb;
35 struct platform_device *phy;
36};
37
38static void tusb_musb_set_vbus(struct musb *musb, int is_on);
39
40#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
41#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
42
43/*
44 * Checks the revision. We need to use the DMA register as 3.0 does not
45 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
46 */
47static u8 tusb_get_revision(struct musb *musb)
48{
49 void __iomem *tbase = musb->ctrl_base;
50 u32 die_id;
51 u8 rev;
52
53 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
54 if (TUSB_REV_MAJOR(rev) == 3) {
55 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
56 TUSB_DIDR1_HI));
57 if (die_id >= TUSB_DIDR1_HI_REV_31)
58 rev |= 1;
59 }
60
61 return rev;
62}
63
64static void tusb_print_revision(struct musb *musb)
65{
66 void __iomem *tbase = musb->ctrl_base;
67 u8 rev;
68
69 rev = musb->tusb_revision;
70
71 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
72 "prcm",
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
75 "int",
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
78 "gpio",
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
81 "dma",
82 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
83 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
84 "dieid",
85 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
86 "rev",
87 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
88}
89
90#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
91 | TUSB_PHY_OTG_CTRL_TESTM0)
92
93/*
94 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
95 * Disables power detection in PHY for the duration of idle.
96 */
97static void tusb_wbus_quirk(struct musb *musb, int enabled)
98{
99 void __iomem *tbase = musb->ctrl_base;
100 static u32 phy_otg_ctrl, phy_otg_ena;
101 u32 tmp;
102
103 if (enabled) {
104 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
105 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
106 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
107 | phy_otg_ena | WBUS_QUIRK_MASK;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
109 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
110 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
111 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
112 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
113 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
114 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
115 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
116 & TUSB_PHY_OTG_CTRL_TESTM2) {
117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
118 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
119 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
120 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
121 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
122 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
123 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
124 phy_otg_ctrl = 0;
125 phy_otg_ena = 0;
126 }
127}
128
129static u32 tusb_fifo_offset(u8 epnum)
130{
131 return 0x200 + (epnum * 0x20);
132}
133
134static u32 tusb_ep_offset(u8 epnum, u16 offset)
135{
136 return 0x10 + offset;
137}
138
139/* TUSB mapping: "flat" plus ep0 special cases */
140static void tusb_ep_select(void __iomem *mbase, u8 epnum)
141{
142 musb_writeb(mbase, MUSB_INDEX, epnum);
143}
144
145/*
146 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
147 */
148static u8 tusb_readb(const void __iomem *addr, unsigned offset)
149{
150 u16 tmp;
151 u8 val;
152
153 tmp = __raw_readw(addr + (offset & ~1));
154 if (offset & 1)
155 val = (tmp >> 8);
156 else
157 val = tmp & 0xff;
158
159 return val;
160}
161
162static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data)
163{
164 u16 tmp;
165
166 tmp = __raw_readw(addr + (offset & ~1));
167 if (offset & 1)
168 tmp = (data << 8) | (tmp & 0xff);
169 else
170 tmp = (tmp & 0xff00) | data;
171
172 __raw_writew(tmp, addr + (offset & ~1));
173}
174
175/*
176 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
177 * so both loading and unloading FIFOs need explicit byte counts.
178 */
179
180static inline void
181tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
182{
183 u32 val;
184 int i;
185
186 if (len > 4) {
187 for (i = 0; i < (len >> 2); i++) {
188 memcpy(&val, buf, 4);
189 musb_writel(fifo, 0, val);
190 buf += 4;
191 }
192 len %= 4;
193 }
194 if (len > 0) {
195 /* Write the rest 1 - 3 bytes to FIFO */
196 memcpy(&val, buf, len);
197 musb_writel(fifo, 0, val);
198 }
199}
200
201static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
202 void *buf, u16 len)
203{
204 u32 val;
205 int i;
206
207 if (len > 4) {
208 for (i = 0; i < (len >> 2); i++) {
209 val = musb_readl(fifo, 0);
210 memcpy(buf, &val, 4);
211 buf += 4;
212 }
213 len %= 4;
214 }
215 if (len > 0) {
216 /* Read the rest 1 - 3 bytes from FIFO */
217 val = musb_readl(fifo, 0);
218 memcpy(buf, &val, len);
219 }
220}
221
222static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
223{
224 struct musb *musb = hw_ep->musb;
225 void __iomem *ep_conf = hw_ep->conf;
226 void __iomem *fifo = hw_ep->fifo;
227 u8 epnum = hw_ep->epnum;
228
229 prefetch(buf);
230
231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
232 'T', epnum, fifo, len, buf);
233
234 if (epnum)
235 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
236 TUSB_EP_CONFIG_XFR_SIZE(len));
237 else
238 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
239 TUSB_EP0_CONFIG_XFR_SIZE(len));
240
241 if (likely((0x01 & (unsigned long) buf) == 0)) {
242
243 /* Best case is 32bit-aligned destination address */
244 if ((0x02 & (unsigned long) buf) == 0) {
245 if (len >= 4) {
246 iowrite32_rep(fifo, buf, len >> 2);
247 buf += (len & ~0x03);
248 len &= 0x03;
249 }
250 } else {
251 if (len >= 2) {
252 u32 val;
253 int i;
254
255 /* Cannot use writesw, fifo is 32-bit */
256 for (i = 0; i < (len >> 2); i++) {
257 val = (u32)(*(u16 *)buf);
258 buf += 2;
259 val |= (*(u16 *)buf) << 16;
260 buf += 2;
261 musb_writel(fifo, 0, val);
262 }
263 len &= 0x03;
264 }
265 }
266 }
267
268 if (len > 0)
269 tusb_fifo_write_unaligned(fifo, buf, len);
270}
271
272static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
273{
274 struct musb *musb = hw_ep->musb;
275 void __iomem *ep_conf = hw_ep->conf;
276 void __iomem *fifo = hw_ep->fifo;
277 u8 epnum = hw_ep->epnum;
278
279 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
280 'R', epnum, fifo, len, buf);
281
282 if (epnum)
283 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
284 TUSB_EP_CONFIG_XFR_SIZE(len));
285 else
286 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
287
288 if (likely((0x01 & (unsigned long) buf) == 0)) {
289
290 /* Best case is 32bit-aligned destination address */
291 if ((0x02 & (unsigned long) buf) == 0) {
292 if (len >= 4) {
293 ioread32_rep(fifo, buf, len >> 2);
294 buf += (len & ~0x03);
295 len &= 0x03;
296 }
297 } else {
298 if (len >= 2) {
299 u32 val;
300 int i;
301
302 /* Cannot use readsw, fifo is 32-bit */
303 for (i = 0; i < (len >> 2); i++) {
304 val = musb_readl(fifo, 0);
305 *(u16 *)buf = (u16)(val & 0xffff);
306 buf += 2;
307 *(u16 *)buf = (u16)(val >> 16);
308 buf += 2;
309 }
310 len &= 0x03;
311 }
312 }
313 }
314
315 if (len > 0)
316 tusb_fifo_read_unaligned(fifo, buf, len);
317}
318
319static struct musb *the_musb;
320
321/* This is used by gadget drivers, and OTG transceiver logic, allowing
322 * at most mA current to be drawn from VBUS during a Default-B session
323 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
324 * mode), or low power Default-B sessions, something else supplies power.
325 * Caller must take care of locking.
326 */
327static int tusb_draw_power(struct usb_phy *x, unsigned mA)
328{
329 struct musb *musb = the_musb;
330 void __iomem *tbase = musb->ctrl_base;
331 u32 reg;
332
333 /* tps65030 seems to consume max 100mA, with maybe 60mA available
334 * (measured on one board) for things other than tps and tusb.
335 *
336 * Boards sharing the CPU clock with CLKIN will need to prevent
337 * certain idle sleep states while the USB link is active.
338 *
339 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
340 * The actual current usage would be very board-specific. For now,
341 * it's simpler to just use an aggregate (also board-specific).
342 */
343 if (x->otg->default_a || mA < (musb->min_power << 1))
344 mA = 0;
345
346 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
347 if (mA) {
348 musb->is_bus_powered = 1;
349 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
350 } else {
351 musb->is_bus_powered = 0;
352 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
353 }
354 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
355
356 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
357 return 0;
358}
359
360/* workaround for issue 13: change clock during chip idle
361 * (to be fixed in rev3 silicon) ... symptoms include disconnect
362 * or looping suspend/resume cycles
363 */
364static void tusb_set_clock_source(struct musb *musb, unsigned mode)
365{
366 void __iomem *tbase = musb->ctrl_base;
367 u32 reg;
368
369 reg = musb_readl(tbase, TUSB_PRCM_CONF);
370 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
371
372 /* 0 = refclk (clkin, XI)
373 * 1 = PHY 60 MHz (internal PLL)
374 * 2 = not supported
375 * 3 = what?
376 */
377 if (mode > 0)
378 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
379
380 musb_writel(tbase, TUSB_PRCM_CONF, reg);
381
382 /* FIXME tusb6010_platform_retime(mode == 0); */
383}
384
385/*
386 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
387 * Other code ensures that we idle unless we're connected _and_ the
388 * USB link is not suspended ... and tells us the relevant wakeup
389 * events. SW_EN for voltage is handled separately.
390 */
391static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
392{
393 void __iomem *tbase = musb->ctrl_base;
394 u32 reg;
395
396 if ((wakeup_enables & TUSB_PRCM_WBUS)
397 && (musb->tusb_revision == TUSB_REV_30))
398 tusb_wbus_quirk(musb, 1);
399
400 tusb_set_clock_source(musb, 0);
401
402 wakeup_enables |= TUSB_PRCM_WNORCS;
403 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
404
405 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
406 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
407 * Presumably that's mostly to save power, hence WID is immaterial ...
408 */
409
410 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
411 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
412 if (is_host_active(musb)) {
413 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
414 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
415 } else {
416 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
417 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
418 }
419 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
420 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
421
422 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
423}
424
425/*
426 * Updates cable VBUS status. Caller must take care of locking.
427 */
428static int tusb_musb_vbus_status(struct musb *musb)
429{
430 void __iomem *tbase = musb->ctrl_base;
431 u32 otg_stat, prcm_mngmt;
432 int ret = 0;
433
434 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
435 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
436
437 /* Temporarily enable VBUS detection if it was disabled for
438 * suspend mode. Unless it's enabled otg_stat and devctl will
439 * not show correct VBUS state.
440 */
441 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
442 u32 tmp = prcm_mngmt;
443 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
444 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
445 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
446 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
447 }
448
449 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
450 ret = 1;
451
452 return ret;
453}
454
455static struct timer_list musb_idle_timer;
456
457static void musb_do_idle(unsigned long _musb)
458{
459 struct musb *musb = (void *)_musb;
460 unsigned long flags;
461
462 spin_lock_irqsave(&musb->lock, flags);
463
464 switch (musb->xceiv->otg->state) {
465 case OTG_STATE_A_WAIT_BCON:
466 if ((musb->a_wait_bcon != 0)
467 && (musb->idle_timeout == 0
468 || time_after(jiffies, musb->idle_timeout))) {
469 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
470 usb_otg_state_string(musb->xceiv->otg->state));
471 }
472 /* FALLTHROUGH */
473 case OTG_STATE_A_IDLE:
474 tusb_musb_set_vbus(musb, 0);
475 default:
476 break;
477 }
478
479 if (!musb->is_active) {
480 u32 wakeups;
481
482 /* wait until hub_wq handles port change status */
483 if (is_host_active(musb) && (musb->port1_status >> 16))
484 goto done;
485
486 if (!musb->gadget_driver) {
487 wakeups = 0;
488 } else {
489 wakeups = TUSB_PRCM_WHOSTDISCON
490 | TUSB_PRCM_WBUS
491 | TUSB_PRCM_WVBUS;
492 wakeups |= TUSB_PRCM_WID;
493 }
494 tusb_allow_idle(musb, wakeups);
495 }
496done:
497 spin_unlock_irqrestore(&musb->lock, flags);
498}
499
500/*
501 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
502 * like "disconnected" or "suspended". We'll be woken out of it by
503 * connect, resume, or disconnect.
504 *
505 * Needs to be called as the last function everywhere where there is
506 * register access to TUSB6010 because of NOR flash wake-up.
507 * Caller should own controller spinlock.
508 *
509 * Delay because peripheral enables D+ pullup 3msec after SE0, and
510 * we don't want to treat that full speed J as a wakeup event.
511 * ... peripherals must draw only suspend current after 10 msec.
512 */
513static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
514{
515 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
516 static unsigned long last_timer;
517
518 if (timeout == 0)
519 timeout = default_timeout;
520
521 /* Never idle if active, or when VBUS timeout is not set as host */
522 if (musb->is_active || ((musb->a_wait_bcon == 0)
523 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
524 dev_dbg(musb->controller, "%s active, deleting timer\n",
525 usb_otg_state_string(musb->xceiv->otg->state));
526 del_timer(&musb_idle_timer);
527 last_timer = jiffies;
528 return;
529 }
530
531 if (time_after(last_timer, timeout)) {
532 if (!timer_pending(&musb_idle_timer))
533 last_timer = timeout;
534 else {
535 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
536 return;
537 }
538 }
539 last_timer = timeout;
540
541 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
542 usb_otg_state_string(musb->xceiv->otg->state),
543 (unsigned long)jiffies_to_msecs(timeout - jiffies));
544 mod_timer(&musb_idle_timer, timeout);
545}
546
547/* ticks of 60 MHz clock */
548#define DEVCLOCK 60000000
549#define OTG_TIMER_MS(msecs) ((msecs) \
550 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
551 | TUSB_DEV_OTG_TIMER_ENABLE) \
552 : 0)
553
554static void tusb_musb_set_vbus(struct musb *musb, int is_on)
555{
556 void __iomem *tbase = musb->ctrl_base;
557 u32 conf, prcm, timer;
558 u8 devctl;
559 struct usb_otg *otg = musb->xceiv->otg;
560
561 /* HDRC controls CPEN, but beware current surges during device
562 * connect. They can trigger transient overcurrent conditions
563 * that must be ignored.
564 */
565
566 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
567 conf = musb_readl(tbase, TUSB_DEV_CONF);
568 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
569
570 if (is_on) {
571 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
572 otg->default_a = 1;
573 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
574 devctl |= MUSB_DEVCTL_SESSION;
575
576 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
577 MUSB_HST_MODE(musb);
578 } else {
579 u32 otg_stat;
580
581 timer = 0;
582
583 /* If ID pin is grounded, we want to be a_idle */
584 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
585 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
586 switch (musb->xceiv->otg->state) {
587 case OTG_STATE_A_WAIT_VRISE:
588 case OTG_STATE_A_WAIT_BCON:
589 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
590 break;
591 case OTG_STATE_A_WAIT_VFALL:
592 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
593 break;
594 default:
595 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
596 }
597 musb->is_active = 0;
598 otg->default_a = 1;
599 MUSB_HST_MODE(musb);
600 } else {
601 musb->is_active = 0;
602 otg->default_a = 0;
603 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
604 MUSB_DEV_MODE(musb);
605 }
606
607 devctl &= ~MUSB_DEVCTL_SESSION;
608 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
609 }
610 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
611
612 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
613 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
614 musb_writel(tbase, TUSB_DEV_CONF, conf);
615 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
616
617 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
618 usb_otg_state_string(musb->xceiv->otg->state),
619 musb_readb(musb->mregs, MUSB_DEVCTL),
620 musb_readl(tbase, TUSB_DEV_OTG_STAT),
621 conf, prcm);
622}
623
624/*
625 * Sets the mode to OTG, peripheral or host by changing the ID detection.
626 * Caller must take care of locking.
627 *
628 * Note that if a mini-A cable is plugged in the ID line will stay down as
629 * the weak ID pull-up is not able to pull the ID up.
630 */
631static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
632{
633 void __iomem *tbase = musb->ctrl_base;
634 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
635
636 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
637 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
638 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
639 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
640
641 switch (musb_mode) {
642
643 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
644 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
645 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
646 dev_conf |= TUSB_DEV_CONF_ID_SEL;
647 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
648 break;
649 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
650 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
651 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
652 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
653 break;
654 case MUSB_OTG: /* Use PHY ID detection */
655 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
656 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
657 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
658 break;
659
660 default:
661 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
662 return -EINVAL;
663 }
664
665 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
666 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
667 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
668 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
669 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
670
671 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
672 if ((musb_mode == MUSB_PERIPHERAL) &&
673 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
674 INFO("Cannot be peripheral with mini-A cable "
675 "otg_stat: %08x\n", otg_stat);
676
677 return 0;
678}
679
680static inline unsigned long
681tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
682{
683 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
684 unsigned long idle_timeout = 0;
685 struct usb_otg *otg = musb->xceiv->otg;
686
687 /* ID pin */
688 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
689 int default_a;
690
691 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
692 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
693 otg->default_a = default_a;
694 tusb_musb_set_vbus(musb, default_a);
695
696 /* Don't allow idling immediately */
697 if (default_a)
698 idle_timeout = jiffies + (HZ * 3);
699 }
700
701 /* VBUS state change */
702 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
703
704 /* B-dev state machine: no vbus ~= disconnect */
705 if (!otg->default_a) {
706 /* ? musb_root_disconnect(musb); */
707 musb->port1_status &=
708 ~(USB_PORT_STAT_CONNECTION
709 | USB_PORT_STAT_ENABLE
710 | USB_PORT_STAT_LOW_SPEED
711 | USB_PORT_STAT_HIGH_SPEED
712 | USB_PORT_STAT_TEST
713 );
714
715 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
716 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
717 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
718 /* INTR_DISCONNECT can hide... */
719 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
720 musb->int_usb |= MUSB_INTR_DISCONNECT;
721 }
722 musb->is_active = 0;
723 }
724 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
725 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
726 idle_timeout = jiffies + (1 * HZ);
727 schedule_work(&musb->irq_work);
728
729 } else /* A-dev state machine */ {
730 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
731 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
732
733 switch (musb->xceiv->otg->state) {
734 case OTG_STATE_A_IDLE:
735 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
736 musb_platform_set_vbus(musb, 1);
737
738 /* CONNECT can wake if a_wait_bcon is set */
739 if (musb->a_wait_bcon != 0)
740 musb->is_active = 0;
741 else
742 musb->is_active = 1;
743
744 /*
745 * OPT FS A TD.4.6 needs few seconds for
746 * A_WAIT_VRISE
747 */
748 idle_timeout = jiffies + (2 * HZ);
749
750 break;
751 case OTG_STATE_A_WAIT_VRISE:
752 /* ignore; A-session-valid < VBUS_VALID/2,
753 * we monitor this with the timer
754 */
755 break;
756 case OTG_STATE_A_WAIT_VFALL:
757 /* REVISIT this irq triggers during short
758 * spikes caused by enumeration ...
759 */
760 if (musb->vbuserr_retry) {
761 musb->vbuserr_retry--;
762 tusb_musb_set_vbus(musb, 1);
763 } else {
764 musb->vbuserr_retry
765 = VBUSERR_RETRY_COUNT;
766 tusb_musb_set_vbus(musb, 0);
767 }
768 break;
769 default:
770 break;
771 }
772 }
773 }
774
775 /* OTG timer expiration */
776 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
777 u8 devctl;
778
779 dev_dbg(musb->controller, "%s timer, %03x\n",
780 usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
781
782 switch (musb->xceiv->otg->state) {
783 case OTG_STATE_A_WAIT_VRISE:
784 /* VBUS has probably been valid for a while now,
785 * but may well have bounced out of range a bit
786 */
787 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
788 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
789 if ((devctl & MUSB_DEVCTL_VBUS)
790 != MUSB_DEVCTL_VBUS) {
791 dev_dbg(musb->controller, "devctl %02x\n", devctl);
792 break;
793 }
794 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
795 musb->is_active = 0;
796 idle_timeout = jiffies
797 + msecs_to_jiffies(musb->a_wait_bcon);
798 } else {
799 /* REVISIT report overcurrent to hub? */
800 ERR("vbus too slow, devctl %02x\n", devctl);
801 tusb_musb_set_vbus(musb, 0);
802 }
803 break;
804 case OTG_STATE_A_WAIT_BCON:
805 if (musb->a_wait_bcon != 0)
806 idle_timeout = jiffies
807 + msecs_to_jiffies(musb->a_wait_bcon);
808 break;
809 case OTG_STATE_A_SUSPEND:
810 break;
811 case OTG_STATE_B_WAIT_ACON:
812 break;
813 default:
814 break;
815 }
816 }
817 schedule_work(&musb->irq_work);
818
819 return idle_timeout;
820}
821
822static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
823{
824 struct musb *musb = __hci;
825 void __iomem *tbase = musb->ctrl_base;
826 unsigned long flags, idle_timeout = 0;
827 u32 int_mask, int_src;
828
829 spin_lock_irqsave(&musb->lock, flags);
830
831 /* Mask all interrupts to allow using both edge and level GPIO irq */
832 int_mask = musb_readl(tbase, TUSB_INT_MASK);
833 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
834
835 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
836 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
837
838 musb->int_usb = (u8) int_src;
839
840 /* Acknowledge wake-up source interrupts */
841 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
842 u32 reg;
843 u32 i;
844
845 if (musb->tusb_revision == TUSB_REV_30)
846 tusb_wbus_quirk(musb, 0);
847
848 /* there are issues re-locking the PLL on wakeup ... */
849
850 /* work around issue 8 */
851 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
852 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
853 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
854 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
855 if (reg == i)
856 break;
857 dev_dbg(musb->controller, "TUSB NOR not ready\n");
858 }
859
860 /* work around issue 13 (2nd half) */
861 tusb_set_clock_source(musb, 1);
862
863 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
864 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
865 if (reg & ~TUSB_PRCM_WNORCS) {
866 musb->is_active = 1;
867 schedule_work(&musb->irq_work);
868 }
869 dev_dbg(musb->controller, "wake %sactive %02x\n",
870 musb->is_active ? "" : "in", reg);
871
872 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
873 }
874
875 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
876 del_timer(&musb_idle_timer);
877
878 /* OTG state change reports (annoyingly) not issued by Mentor core */
879 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
880 | TUSB_INT_SRC_OTG_TIMEOUT
881 | TUSB_INT_SRC_ID_STATUS_CHNG))
882 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
883
884 /* TX dma callback must be handled here, RX dma callback is
885 * handled in tusb_omap_dma_cb.
886 */
887 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
888 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
889 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
890
891 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
892 real_dma_src = ~real_dma_src & dma_src;
893 if (tusb_dma_omap(musb) && real_dma_src) {
894 int tx_source = (real_dma_src & 0xffff);
895 int i;
896
897 for (i = 1; i <= 15; i++) {
898 if (tx_source & (1 << i)) {
899 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
900 musb_dma_completion(musb, i, 1);
901 }
902 }
903 }
904 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
905 }
906
907 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
908 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
909 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
910
911 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
912 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
913 musb->int_tx = (musb_src & 0xffff);
914 } else {
915 musb->int_rx = 0;
916 musb->int_tx = 0;
917 }
918
919 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
920 musb_interrupt(musb);
921
922 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
923 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
924 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
925
926 tusb_musb_try_idle(musb, idle_timeout);
927
928 musb_writel(tbase, TUSB_INT_MASK, int_mask);
929 spin_unlock_irqrestore(&musb->lock, flags);
930
931 return IRQ_HANDLED;
932}
933
934static int dma_off;
935
936/*
937 * Enables TUSB6010. Caller must take care of locking.
938 * REVISIT:
939 * - Check what is unnecessary in MGC_HdrcStart()
940 */
941static void tusb_musb_enable(struct musb *musb)
942{
943 void __iomem *tbase = musb->ctrl_base;
944
945 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
946 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
947 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
948
949 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
950 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
951 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
952 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
953
954 /* Clear all subsystem interrups */
955 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
956 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
957 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
958
959 /* Acknowledge pending interrupt(s) */
960 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
961
962 /* Only 0 clock cycles for minimum interrupt de-assertion time and
963 * interrupt polarity active low seems to work reliably here */
964 musb_writel(tbase, TUSB_INT_CTRL_CONF,
965 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
966
967 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
968
969 /* maybe force into the Default-A OTG state machine */
970 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
971 & TUSB_DEV_OTG_STAT_ID_STATUS))
972 musb_writel(tbase, TUSB_INT_SRC_SET,
973 TUSB_INT_SRC_ID_STATUS_CHNG);
974
975 if (is_dma_capable() && dma_off)
976 printk(KERN_WARNING "%s %s: dma not reactivated\n",
977 __FILE__, __func__);
978 else
979 dma_off = 1;
980}
981
982/*
983 * Disables TUSB6010. Caller must take care of locking.
984 */
985static void tusb_musb_disable(struct musb *musb)
986{
987 void __iomem *tbase = musb->ctrl_base;
988
989 /* FIXME stop DMA, IRQs, timers, ... */
990
991 /* disable all IRQs */
992 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
993 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
994 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
995 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
996
997 del_timer(&musb_idle_timer);
998
999 if (is_dma_capable() && !dma_off) {
1000 printk(KERN_WARNING "%s %s: dma still active\n",
1001 __FILE__, __func__);
1002 dma_off = 1;
1003 }
1004}
1005
1006/*
1007 * Sets up TUSB6010 CPU interface specific signals and registers
1008 * Note: Settings optimized for OMAP24xx
1009 */
1010static void tusb_setup_cpu_interface(struct musb *musb)
1011{
1012 void __iomem *tbase = musb->ctrl_base;
1013
1014 /*
1015 * Disable GPIO[5:0] pullups (used as output DMA requests)
1016 * Don't disable GPIO[7:6] as they are needed for wake-up.
1017 */
1018 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1019
1020 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1021 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1022
1023 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1024 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1025
1026 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1027 * de-assertion time 2 system clocks p 62 */
1028 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1029 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1030 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1031 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1032
1033 /* Set 0 wait count for synchronous burst access */
1034 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1035}
1036
1037static int tusb_musb_start(struct musb *musb)
1038{
1039 void __iomem *tbase = musb->ctrl_base;
1040 int ret = 0;
1041 unsigned long flags;
1042 u32 reg;
1043
1044 if (musb->board_set_power)
1045 ret = musb->board_set_power(1);
1046 if (ret != 0) {
1047 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1048 return ret;
1049 }
1050
1051 spin_lock_irqsave(&musb->lock, flags);
1052
1053 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1054 TUSB_PROD_TEST_RESET_VAL) {
1055 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1056 goto err;
1057 }
1058
1059 musb->tusb_revision = tusb_get_revision(musb);
1060 tusb_print_revision(musb);
1061 if (musb->tusb_revision < 2) {
1062 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1063 musb->tusb_revision);
1064 goto err;
1065 }
1066
1067 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1068 * NOR FLASH interface is used */
1069 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1070
1071 /* Select PHY free running 60MHz as a system clock */
1072 tusb_set_clock_source(musb, 1);
1073
1074 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1075 * power saving, enable VBus detect and session end comparators,
1076 * enable IDpullup, enable VBus charging */
1077 musb_writel(tbase, TUSB_PRCM_MNGMT,
1078 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1079 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1080 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1081 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1082 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1083 tusb_setup_cpu_interface(musb);
1084
1085 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1086 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1087 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1088 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1089
1090 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1091 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1092 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1093
1094 spin_unlock_irqrestore(&musb->lock, flags);
1095
1096 return 0;
1097
1098err:
1099 spin_unlock_irqrestore(&musb->lock, flags);
1100
1101 if (musb->board_set_power)
1102 musb->board_set_power(0);
1103
1104 return -ENODEV;
1105}
1106
1107static int tusb_musb_init(struct musb *musb)
1108{
1109 struct platform_device *pdev;
1110 struct resource *mem;
1111 void __iomem *sync = NULL;
1112 int ret;
1113
1114 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1115 if (IS_ERR_OR_NULL(musb->xceiv))
1116 return -EPROBE_DEFER;
1117
1118 pdev = to_platform_device(musb->controller);
1119
1120 /* dma address for async dma */
1121 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 musb->async = mem->start;
1123
1124 /* dma address for sync dma */
1125 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1126 if (!mem) {
1127 pr_debug("no sync dma resource?\n");
1128 ret = -ENODEV;
1129 goto done;
1130 }
1131 musb->sync = mem->start;
1132
1133 sync = ioremap(mem->start, resource_size(mem));
1134 if (!sync) {
1135 pr_debug("ioremap for sync failed\n");
1136 ret = -ENOMEM;
1137 goto done;
1138 }
1139 musb->sync_va = sync;
1140
1141 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1142 * FIFOs at 0x600, TUSB at 0x800
1143 */
1144 musb->mregs += TUSB_BASE_OFFSET;
1145
1146 ret = tusb_musb_start(musb);
1147 if (ret) {
1148 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1149 ret);
1150 goto done;
1151 }
1152 musb->isr = tusb_musb_interrupt;
1153
1154 musb->xceiv->set_power = tusb_draw_power;
1155 the_musb = musb;
1156
1157 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1158
1159done:
1160 if (ret < 0) {
1161 if (sync)
1162 iounmap(sync);
1163
1164 usb_put_phy(musb->xceiv);
1165 }
1166 return ret;
1167}
1168
1169static int tusb_musb_exit(struct musb *musb)
1170{
1171 del_timer_sync(&musb_idle_timer);
1172 the_musb = NULL;
1173
1174 if (musb->board_set_power)
1175 musb->board_set_power(0);
1176
1177 iounmap(musb->sync_va);
1178
1179 usb_put_phy(musb->xceiv);
1180 return 0;
1181}
1182
1183static const struct musb_platform_ops tusb_ops = {
1184 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB,
1185 .init = tusb_musb_init,
1186 .exit = tusb_musb_exit,
1187
1188 .ep_offset = tusb_ep_offset,
1189 .ep_select = tusb_ep_select,
1190 .fifo_offset = tusb_fifo_offset,
1191 .readb = tusb_readb,
1192 .writeb = tusb_writeb,
1193 .read_fifo = tusb_read_fifo,
1194 .write_fifo = tusb_write_fifo,
1195#ifdef CONFIG_USB_TUSB_OMAP_DMA
1196 .dma_init = tusb_dma_controller_create,
1197 .dma_exit = tusb_dma_controller_destroy,
1198#endif
1199 .enable = tusb_musb_enable,
1200 .disable = tusb_musb_disable,
1201
1202 .set_mode = tusb_musb_set_mode,
1203 .try_idle = tusb_musb_try_idle,
1204
1205 .vbus_status = tusb_musb_vbus_status,
1206 .set_vbus = tusb_musb_set_vbus,
1207};
1208
1209static const struct platform_device_info tusb_dev_info = {
1210 .name = "musb-hdrc",
1211 .id = PLATFORM_DEVID_AUTO,
1212 .dma_mask = DMA_BIT_MASK(32),
1213};
1214
1215static int tusb_probe(struct platform_device *pdev)
1216{
1217 struct resource musb_resources[3];
1218 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1219 struct platform_device *musb;
1220 struct tusb6010_glue *glue;
1221 struct platform_device_info pinfo;
1222 int ret;
1223
1224 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
1225 if (!glue)
1226 return -ENOMEM;
1227
1228 glue->dev = &pdev->dev;
1229
1230 pdata->platform_ops = &tusb_ops;
1231
1232 usb_phy_generic_register();
1233 platform_set_drvdata(pdev, glue);
1234
1235 memset(musb_resources, 0x00, sizeof(*musb_resources) *
1236 ARRAY_SIZE(musb_resources));
1237
1238 musb_resources[0].name = pdev->resource[0].name;
1239 musb_resources[0].start = pdev->resource[0].start;
1240 musb_resources[0].end = pdev->resource[0].end;
1241 musb_resources[0].flags = pdev->resource[0].flags;
1242
1243 musb_resources[1].name = pdev->resource[1].name;
1244 musb_resources[1].start = pdev->resource[1].start;
1245 musb_resources[1].end = pdev->resource[1].end;
1246 musb_resources[1].flags = pdev->resource[1].flags;
1247
1248 musb_resources[2].name = pdev->resource[2].name;
1249 musb_resources[2].start = pdev->resource[2].start;
1250 musb_resources[2].end = pdev->resource[2].end;
1251 musb_resources[2].flags = pdev->resource[2].flags;
1252
1253 pinfo = tusb_dev_info;
1254 pinfo.parent = &pdev->dev;
1255 pinfo.res = musb_resources;
1256 pinfo.num_res = ARRAY_SIZE(musb_resources);
1257 pinfo.data = pdata;
1258 pinfo.size_data = sizeof(*pdata);
1259
1260 glue->musb = musb = platform_device_register_full(&pinfo);
1261 if (IS_ERR(musb)) {
1262 ret = PTR_ERR(musb);
1263 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
1264 return ret;
1265 }
1266
1267 return 0;
1268}
1269
1270static int tusb_remove(struct platform_device *pdev)
1271{
1272 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1273
1274 platform_device_unregister(glue->musb);
1275 usb_phy_generic_unregister(glue->phy);
1276
1277 return 0;
1278}
1279
1280static struct platform_driver tusb_driver = {
1281 .probe = tusb_probe,
1282 .remove = tusb_remove,
1283 .driver = {
1284 .name = "musb-tusb",
1285 },
1286};
1287
1288MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1289MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1290MODULE_LICENSE("GPL v2");
1291module_platform_driver(tusb_driver);
1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/prefetch.h>
22#include <linux/usb.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26
27#include "musb_core.h"
28
29struct tusb6010_glue {
30 struct device *dev;
31 struct platform_device *musb;
32};
33
34static void tusb_musb_set_vbus(struct musb *musb, int is_on);
35
36#define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
37#define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
38
39/*
40 * Checks the revision. We need to use the DMA register as 3.0 does not
41 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
42 */
43u8 tusb_get_revision(struct musb *musb)
44{
45 void __iomem *tbase = musb->ctrl_base;
46 u32 die_id;
47 u8 rev;
48
49 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
50 if (TUSB_REV_MAJOR(rev) == 3) {
51 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
52 TUSB_DIDR1_HI));
53 if (die_id >= TUSB_DIDR1_HI_REV_31)
54 rev |= 1;
55 }
56
57 return rev;
58}
59
60static int tusb_print_revision(struct musb *musb)
61{
62 void __iomem *tbase = musb->ctrl_base;
63 u8 rev;
64
65 rev = tusb_get_revision(musb);
66
67 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
68 "prcm",
69 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
70 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 "int",
72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 "gpio",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 "dma",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 "dieid",
81 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
82 "rev",
83 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
84
85 return tusb_get_revision(musb);
86}
87
88#define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
89 | TUSB_PHY_OTG_CTRL_TESTM0)
90
91/*
92 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
93 * Disables power detection in PHY for the duration of idle.
94 */
95static void tusb_wbus_quirk(struct musb *musb, int enabled)
96{
97 void __iomem *tbase = musb->ctrl_base;
98 static u32 phy_otg_ctrl, phy_otg_ena;
99 u32 tmp;
100
101 if (enabled) {
102 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
103 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
104 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
105 | phy_otg_ena | WBUS_QUIRK_MASK;
106 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
107 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
108 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
109 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
110 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
112 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
113 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
114 & TUSB_PHY_OTG_CTRL_TESTM2) {
115 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
116 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
118 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
119 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
121 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
122 phy_otg_ctrl = 0;
123 phy_otg_ena = 0;
124 }
125}
126
127/*
128 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
129 * so both loading and unloading FIFOs need explicit byte counts.
130 */
131
132static inline void
133tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
134{
135 u32 val;
136 int i;
137
138 if (len > 4) {
139 for (i = 0; i < (len >> 2); i++) {
140 memcpy(&val, buf, 4);
141 musb_writel(fifo, 0, val);
142 buf += 4;
143 }
144 len %= 4;
145 }
146 if (len > 0) {
147 /* Write the rest 1 - 3 bytes to FIFO */
148 memcpy(&val, buf, len);
149 musb_writel(fifo, 0, val);
150 }
151}
152
153static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
154 void __iomem *buf, u16 len)
155{
156 u32 val;
157 int i;
158
159 if (len > 4) {
160 for (i = 0; i < (len >> 2); i++) {
161 val = musb_readl(fifo, 0);
162 memcpy(buf, &val, 4);
163 buf += 4;
164 }
165 len %= 4;
166 }
167 if (len > 0) {
168 /* Read the rest 1 - 3 bytes from FIFO */
169 val = musb_readl(fifo, 0);
170 memcpy(buf, &val, len);
171 }
172}
173
174void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
175{
176 struct musb *musb = hw_ep->musb;
177 void __iomem *ep_conf = hw_ep->conf;
178 void __iomem *fifo = hw_ep->fifo;
179 u8 epnum = hw_ep->epnum;
180
181 prefetch(buf);
182
183 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
184 'T', epnum, fifo, len, buf);
185
186 if (epnum)
187 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
188 TUSB_EP_CONFIG_XFR_SIZE(len));
189 else
190 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
191 TUSB_EP0_CONFIG_XFR_SIZE(len));
192
193 if (likely((0x01 & (unsigned long) buf) == 0)) {
194
195 /* Best case is 32bit-aligned destination address */
196 if ((0x02 & (unsigned long) buf) == 0) {
197 if (len >= 4) {
198 writesl(fifo, buf, len >> 2);
199 buf += (len & ~0x03);
200 len &= 0x03;
201 }
202 } else {
203 if (len >= 2) {
204 u32 val;
205 int i;
206
207 /* Cannot use writesw, fifo is 32-bit */
208 for (i = 0; i < (len >> 2); i++) {
209 val = (u32)(*(u16 *)buf);
210 buf += 2;
211 val |= (*(u16 *)buf) << 16;
212 buf += 2;
213 musb_writel(fifo, 0, val);
214 }
215 len &= 0x03;
216 }
217 }
218 }
219
220 if (len > 0)
221 tusb_fifo_write_unaligned(fifo, buf, len);
222}
223
224void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
225{
226 struct musb *musb = hw_ep->musb;
227 void __iomem *ep_conf = hw_ep->conf;
228 void __iomem *fifo = hw_ep->fifo;
229 u8 epnum = hw_ep->epnum;
230
231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
232 'R', epnum, fifo, len, buf);
233
234 if (epnum)
235 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
236 TUSB_EP_CONFIG_XFR_SIZE(len));
237 else
238 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
239
240 if (likely((0x01 & (unsigned long) buf) == 0)) {
241
242 /* Best case is 32bit-aligned destination address */
243 if ((0x02 & (unsigned long) buf) == 0) {
244 if (len >= 4) {
245 readsl(fifo, buf, len >> 2);
246 buf += (len & ~0x03);
247 len &= 0x03;
248 }
249 } else {
250 if (len >= 2) {
251 u32 val;
252 int i;
253
254 /* Cannot use readsw, fifo is 32-bit */
255 for (i = 0; i < (len >> 2); i++) {
256 val = musb_readl(fifo, 0);
257 *(u16 *)buf = (u16)(val & 0xffff);
258 buf += 2;
259 *(u16 *)buf = (u16)(val >> 16);
260 buf += 2;
261 }
262 len &= 0x03;
263 }
264 }
265 }
266
267 if (len > 0)
268 tusb_fifo_read_unaligned(fifo, buf, len);
269}
270
271static struct musb *the_musb;
272
273/* This is used by gadget drivers, and OTG transceiver logic, allowing
274 * at most mA current to be drawn from VBUS during a Default-B session
275 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
276 * mode), or low power Default-B sessions, something else supplies power.
277 * Caller must take care of locking.
278 */
279static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
280{
281 struct musb *musb = the_musb;
282 void __iomem *tbase = musb->ctrl_base;
283 u32 reg;
284
285 /* tps65030 seems to consume max 100mA, with maybe 60mA available
286 * (measured on one board) for things other than tps and tusb.
287 *
288 * Boards sharing the CPU clock with CLKIN will need to prevent
289 * certain idle sleep states while the USB link is active.
290 *
291 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
292 * The actual current usage would be very board-specific. For now,
293 * it's simpler to just use an aggregate (also board-specific).
294 */
295 if (x->default_a || mA < (musb->min_power << 1))
296 mA = 0;
297
298 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
299 if (mA) {
300 musb->is_bus_powered = 1;
301 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
302 } else {
303 musb->is_bus_powered = 0;
304 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
305 }
306 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
307
308 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
309 return 0;
310}
311
312/* workaround for issue 13: change clock during chip idle
313 * (to be fixed in rev3 silicon) ... symptoms include disconnect
314 * or looping suspend/resume cycles
315 */
316static void tusb_set_clock_source(struct musb *musb, unsigned mode)
317{
318 void __iomem *tbase = musb->ctrl_base;
319 u32 reg;
320
321 reg = musb_readl(tbase, TUSB_PRCM_CONF);
322 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
323
324 /* 0 = refclk (clkin, XI)
325 * 1 = PHY 60 MHz (internal PLL)
326 * 2 = not supported
327 * 3 = what?
328 */
329 if (mode > 0)
330 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
331
332 musb_writel(tbase, TUSB_PRCM_CONF, reg);
333
334 /* FIXME tusb6010_platform_retime(mode == 0); */
335}
336
337/*
338 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
339 * Other code ensures that we idle unless we're connected _and_ the
340 * USB link is not suspended ... and tells us the relevant wakeup
341 * events. SW_EN for voltage is handled separately.
342 */
343static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
344{
345 void __iomem *tbase = musb->ctrl_base;
346 u32 reg;
347
348 if ((wakeup_enables & TUSB_PRCM_WBUS)
349 && (tusb_get_revision(musb) == TUSB_REV_30))
350 tusb_wbus_quirk(musb, 1);
351
352 tusb_set_clock_source(musb, 0);
353
354 wakeup_enables |= TUSB_PRCM_WNORCS;
355 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
356
357 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
358 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
359 * Presumably that's mostly to save power, hence WID is immaterial ...
360 */
361
362 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
363 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
364 if (is_host_active(musb)) {
365 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
366 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
367 } else {
368 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
369 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
370 }
371 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
372 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
373
374 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
375}
376
377/*
378 * Updates cable VBUS status. Caller must take care of locking.
379 */
380static int tusb_musb_vbus_status(struct musb *musb)
381{
382 void __iomem *tbase = musb->ctrl_base;
383 u32 otg_stat, prcm_mngmt;
384 int ret = 0;
385
386 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
387 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
388
389 /* Temporarily enable VBUS detection if it was disabled for
390 * suspend mode. Unless it's enabled otg_stat and devctl will
391 * not show correct VBUS state.
392 */
393 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
394 u32 tmp = prcm_mngmt;
395 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
396 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
397 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
398 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
399 }
400
401 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
402 ret = 1;
403
404 return ret;
405}
406
407static struct timer_list musb_idle_timer;
408
409static void musb_do_idle(unsigned long _musb)
410{
411 struct musb *musb = (void *)_musb;
412 unsigned long flags;
413
414 spin_lock_irqsave(&musb->lock, flags);
415
416 switch (musb->xceiv->state) {
417 case OTG_STATE_A_WAIT_BCON:
418 if ((musb->a_wait_bcon != 0)
419 && (musb->idle_timeout == 0
420 || time_after(jiffies, musb->idle_timeout))) {
421 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
422 otg_state_string(musb->xceiv->state));
423 }
424 /* FALLTHROUGH */
425 case OTG_STATE_A_IDLE:
426 tusb_musb_set_vbus(musb, 0);
427 default:
428 break;
429 }
430
431 if (!musb->is_active) {
432 u32 wakeups;
433
434 /* wait until khubd handles port change status */
435 if (is_host_active(musb) && (musb->port1_status >> 16))
436 goto done;
437
438 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
439 wakeups = 0;
440 } else {
441 wakeups = TUSB_PRCM_WHOSTDISCON
442 | TUSB_PRCM_WBUS
443 | TUSB_PRCM_WVBUS;
444 if (is_otg_enabled(musb))
445 wakeups |= TUSB_PRCM_WID;
446 }
447 tusb_allow_idle(musb, wakeups);
448 }
449done:
450 spin_unlock_irqrestore(&musb->lock, flags);
451}
452
453/*
454 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
455 * like "disconnected" or "suspended". We'll be woken out of it by
456 * connect, resume, or disconnect.
457 *
458 * Needs to be called as the last function everywhere where there is
459 * register access to TUSB6010 because of NOR flash wake-up.
460 * Caller should own controller spinlock.
461 *
462 * Delay because peripheral enables D+ pullup 3msec after SE0, and
463 * we don't want to treat that full speed J as a wakeup event.
464 * ... peripherals must draw only suspend current after 10 msec.
465 */
466static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
467{
468 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
469 static unsigned long last_timer;
470
471 if (timeout == 0)
472 timeout = default_timeout;
473
474 /* Never idle if active, or when VBUS timeout is not set as host */
475 if (musb->is_active || ((musb->a_wait_bcon == 0)
476 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
477 dev_dbg(musb->controller, "%s active, deleting timer\n",
478 otg_state_string(musb->xceiv->state));
479 del_timer(&musb_idle_timer);
480 last_timer = jiffies;
481 return;
482 }
483
484 if (time_after(last_timer, timeout)) {
485 if (!timer_pending(&musb_idle_timer))
486 last_timer = timeout;
487 else {
488 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
489 return;
490 }
491 }
492 last_timer = timeout;
493
494 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
495 otg_state_string(musb->xceiv->state),
496 (unsigned long)jiffies_to_msecs(timeout - jiffies));
497 mod_timer(&musb_idle_timer, timeout);
498}
499
500/* ticks of 60 MHz clock */
501#define DEVCLOCK 60000000
502#define OTG_TIMER_MS(msecs) ((msecs) \
503 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
504 | TUSB_DEV_OTG_TIMER_ENABLE) \
505 : 0)
506
507static void tusb_musb_set_vbus(struct musb *musb, int is_on)
508{
509 void __iomem *tbase = musb->ctrl_base;
510 u32 conf, prcm, timer;
511 u8 devctl;
512
513 /* HDRC controls CPEN, but beware current surges during device
514 * connect. They can trigger transient overcurrent conditions
515 * that must be ignored.
516 */
517
518 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
519 conf = musb_readl(tbase, TUSB_DEV_CONF);
520 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
521
522 if (is_on) {
523 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
524 musb->xceiv->default_a = 1;
525 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
526 devctl |= MUSB_DEVCTL_SESSION;
527
528 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
529 MUSB_HST_MODE(musb);
530 } else {
531 u32 otg_stat;
532
533 timer = 0;
534
535 /* If ID pin is grounded, we want to be a_idle */
536 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
537 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
538 switch (musb->xceiv->state) {
539 case OTG_STATE_A_WAIT_VRISE:
540 case OTG_STATE_A_WAIT_BCON:
541 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
542 break;
543 case OTG_STATE_A_WAIT_VFALL:
544 musb->xceiv->state = OTG_STATE_A_IDLE;
545 break;
546 default:
547 musb->xceiv->state = OTG_STATE_A_IDLE;
548 }
549 musb->is_active = 0;
550 musb->xceiv->default_a = 1;
551 MUSB_HST_MODE(musb);
552 } else {
553 musb->is_active = 0;
554 musb->xceiv->default_a = 0;
555 musb->xceiv->state = OTG_STATE_B_IDLE;
556 MUSB_DEV_MODE(musb);
557 }
558
559 devctl &= ~MUSB_DEVCTL_SESSION;
560 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
561 }
562 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
563
564 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
565 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
566 musb_writel(tbase, TUSB_DEV_CONF, conf);
567 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
568
569 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
570 otg_state_string(musb->xceiv->state),
571 musb_readb(musb->mregs, MUSB_DEVCTL),
572 musb_readl(tbase, TUSB_DEV_OTG_STAT),
573 conf, prcm);
574}
575
576/*
577 * Sets the mode to OTG, peripheral or host by changing the ID detection.
578 * Caller must take care of locking.
579 *
580 * Note that if a mini-A cable is plugged in the ID line will stay down as
581 * the weak ID pull-up is not able to pull the ID up.
582 *
583 * REVISIT: It would be possible to add support for changing between host
584 * and peripheral modes in non-OTG configurations by reconfiguring hardware
585 * and then setting musb->board_mode. For now, only support OTG mode.
586 */
587static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
588{
589 void __iomem *tbase = musb->ctrl_base;
590 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
591
592 if (musb->board_mode != MUSB_OTG) {
593 ERR("Changing mode currently only supported in OTG mode\n");
594 return -EINVAL;
595 }
596
597 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
598 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
599 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
600 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
601
602 switch (musb_mode) {
603
604 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
605 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
606 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
607 dev_conf |= TUSB_DEV_CONF_ID_SEL;
608 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
609 break;
610 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
611 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
612 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
613 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
614 break;
615 case MUSB_OTG: /* Use PHY ID detection */
616 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
617 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
618 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
619 break;
620
621 default:
622 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
623 return -EINVAL;
624 }
625
626 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
627 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
628 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
629 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
630 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
631
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 if ((musb_mode == MUSB_PERIPHERAL) &&
634 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
635 INFO("Cannot be peripheral with mini-A cable "
636 "otg_stat: %08x\n", otg_stat);
637
638 return 0;
639}
640
641static inline unsigned long
642tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
643{
644 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
645 unsigned long idle_timeout = 0;
646
647 /* ID pin */
648 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
649 int default_a;
650
651 if (is_otg_enabled(musb))
652 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
653 else
654 default_a = is_host_enabled(musb);
655 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
656 musb->xceiv->default_a = default_a;
657 tusb_musb_set_vbus(musb, default_a);
658
659 /* Don't allow idling immediately */
660 if (default_a)
661 idle_timeout = jiffies + (HZ * 3);
662 }
663
664 /* VBUS state change */
665 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
666
667 /* B-dev state machine: no vbus ~= disconnect */
668 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
669 || !is_host_enabled(musb)) {
670 /* ? musb_root_disconnect(musb); */
671 musb->port1_status &=
672 ~(USB_PORT_STAT_CONNECTION
673 | USB_PORT_STAT_ENABLE
674 | USB_PORT_STAT_LOW_SPEED
675 | USB_PORT_STAT_HIGH_SPEED
676 | USB_PORT_STAT_TEST
677 );
678
679 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
680 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
681 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
682 /* INTR_DISCONNECT can hide... */
683 musb->xceiv->state = OTG_STATE_B_IDLE;
684 musb->int_usb |= MUSB_INTR_DISCONNECT;
685 }
686 musb->is_active = 0;
687 }
688 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
689 otg_state_string(musb->xceiv->state), otg_stat);
690 idle_timeout = jiffies + (1 * HZ);
691 schedule_work(&musb->irq_work);
692
693 } else /* A-dev state machine */ {
694 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
695 otg_state_string(musb->xceiv->state), otg_stat);
696
697 switch (musb->xceiv->state) {
698 case OTG_STATE_A_IDLE:
699 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
700 musb_platform_set_vbus(musb, 1);
701
702 /* CONNECT can wake if a_wait_bcon is set */
703 if (musb->a_wait_bcon != 0)
704 musb->is_active = 0;
705 else
706 musb->is_active = 1;
707
708 /*
709 * OPT FS A TD.4.6 needs few seconds for
710 * A_WAIT_VRISE
711 */
712 idle_timeout = jiffies + (2 * HZ);
713
714 break;
715 case OTG_STATE_A_WAIT_VRISE:
716 /* ignore; A-session-valid < VBUS_VALID/2,
717 * we monitor this with the timer
718 */
719 break;
720 case OTG_STATE_A_WAIT_VFALL:
721 /* REVISIT this irq triggers during short
722 * spikes caused by enumeration ...
723 */
724 if (musb->vbuserr_retry) {
725 musb->vbuserr_retry--;
726 tusb_musb_set_vbus(musb, 1);
727 } else {
728 musb->vbuserr_retry
729 = VBUSERR_RETRY_COUNT;
730 tusb_musb_set_vbus(musb, 0);
731 }
732 break;
733 default:
734 break;
735 }
736 }
737 }
738
739 /* OTG timer expiration */
740 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
741 u8 devctl;
742
743 dev_dbg(musb->controller, "%s timer, %03x\n",
744 otg_state_string(musb->xceiv->state), otg_stat);
745
746 switch (musb->xceiv->state) {
747 case OTG_STATE_A_WAIT_VRISE:
748 /* VBUS has probably been valid for a while now,
749 * but may well have bounced out of range a bit
750 */
751 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
752 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
753 if ((devctl & MUSB_DEVCTL_VBUS)
754 != MUSB_DEVCTL_VBUS) {
755 dev_dbg(musb->controller, "devctl %02x\n", devctl);
756 break;
757 }
758 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
759 musb->is_active = 0;
760 idle_timeout = jiffies
761 + msecs_to_jiffies(musb->a_wait_bcon);
762 } else {
763 /* REVISIT report overcurrent to hub? */
764 ERR("vbus too slow, devctl %02x\n", devctl);
765 tusb_musb_set_vbus(musb, 0);
766 }
767 break;
768 case OTG_STATE_A_WAIT_BCON:
769 if (musb->a_wait_bcon != 0)
770 idle_timeout = jiffies
771 + msecs_to_jiffies(musb->a_wait_bcon);
772 break;
773 case OTG_STATE_A_SUSPEND:
774 break;
775 case OTG_STATE_B_WAIT_ACON:
776 break;
777 default:
778 break;
779 }
780 }
781 schedule_work(&musb->irq_work);
782
783 return idle_timeout;
784}
785
786static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
787{
788 struct musb *musb = __hci;
789 void __iomem *tbase = musb->ctrl_base;
790 unsigned long flags, idle_timeout = 0;
791 u32 int_mask, int_src;
792
793 spin_lock_irqsave(&musb->lock, flags);
794
795 /* Mask all interrupts to allow using both edge and level GPIO irq */
796 int_mask = musb_readl(tbase, TUSB_INT_MASK);
797 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
798
799 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
800 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
801
802 musb->int_usb = (u8) int_src;
803
804 /* Acknowledge wake-up source interrupts */
805 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
806 u32 reg;
807 u32 i;
808
809 if (tusb_get_revision(musb) == TUSB_REV_30)
810 tusb_wbus_quirk(musb, 0);
811
812 /* there are issues re-locking the PLL on wakeup ... */
813
814 /* work around issue 8 */
815 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
816 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
817 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
818 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
819 if (reg == i)
820 break;
821 dev_dbg(musb->controller, "TUSB NOR not ready\n");
822 }
823
824 /* work around issue 13 (2nd half) */
825 tusb_set_clock_source(musb, 1);
826
827 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
828 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
829 if (reg & ~TUSB_PRCM_WNORCS) {
830 musb->is_active = 1;
831 schedule_work(&musb->irq_work);
832 }
833 dev_dbg(musb->controller, "wake %sactive %02x\n",
834 musb->is_active ? "" : "in", reg);
835
836 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
837 }
838
839 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
840 del_timer(&musb_idle_timer);
841
842 /* OTG state change reports (annoyingly) not issued by Mentor core */
843 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
844 | TUSB_INT_SRC_OTG_TIMEOUT
845 | TUSB_INT_SRC_ID_STATUS_CHNG))
846 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
847
848 /* TX dma callback must be handled here, RX dma callback is
849 * handled in tusb_omap_dma_cb.
850 */
851 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
852 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
853 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
854
855 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
856 real_dma_src = ~real_dma_src & dma_src;
857 if (tusb_dma_omap() && real_dma_src) {
858 int tx_source = (real_dma_src & 0xffff);
859 int i;
860
861 for (i = 1; i <= 15; i++) {
862 if (tx_source & (1 << i)) {
863 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
864 musb_dma_completion(musb, i, 1);
865 }
866 }
867 }
868 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
869 }
870
871 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
872 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
873 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
874
875 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
876 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
877 musb->int_tx = (musb_src & 0xffff);
878 } else {
879 musb->int_rx = 0;
880 musb->int_tx = 0;
881 }
882
883 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
884 musb_interrupt(musb);
885
886 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
887 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
888 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
889
890 tusb_musb_try_idle(musb, idle_timeout);
891
892 musb_writel(tbase, TUSB_INT_MASK, int_mask);
893 spin_unlock_irqrestore(&musb->lock, flags);
894
895 return IRQ_HANDLED;
896}
897
898static int dma_off;
899
900/*
901 * Enables TUSB6010. Caller must take care of locking.
902 * REVISIT:
903 * - Check what is unnecessary in MGC_HdrcStart()
904 */
905static void tusb_musb_enable(struct musb *musb)
906{
907 void __iomem *tbase = musb->ctrl_base;
908
909 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
910 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
911 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
912
913 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
914 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
915 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
916 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
917
918 /* Clear all subsystem interrups */
919 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
920 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
921 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
922
923 /* Acknowledge pending interrupt(s) */
924 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
925
926 /* Only 0 clock cycles for minimum interrupt de-assertion time and
927 * interrupt polarity active low seems to work reliably here */
928 musb_writel(tbase, TUSB_INT_CTRL_CONF,
929 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
930
931 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
932
933 /* maybe force into the Default-A OTG state machine */
934 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
935 & TUSB_DEV_OTG_STAT_ID_STATUS))
936 musb_writel(tbase, TUSB_INT_SRC_SET,
937 TUSB_INT_SRC_ID_STATUS_CHNG);
938
939 if (is_dma_capable() && dma_off)
940 printk(KERN_WARNING "%s %s: dma not reactivated\n",
941 __FILE__, __func__);
942 else
943 dma_off = 1;
944}
945
946/*
947 * Disables TUSB6010. Caller must take care of locking.
948 */
949static void tusb_musb_disable(struct musb *musb)
950{
951 void __iomem *tbase = musb->ctrl_base;
952
953 /* FIXME stop DMA, IRQs, timers, ... */
954
955 /* disable all IRQs */
956 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
957 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
958 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
959 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
960
961 del_timer(&musb_idle_timer);
962
963 if (is_dma_capable() && !dma_off) {
964 printk(KERN_WARNING "%s %s: dma still active\n",
965 __FILE__, __func__);
966 dma_off = 1;
967 }
968}
969
970/*
971 * Sets up TUSB6010 CPU interface specific signals and registers
972 * Note: Settings optimized for OMAP24xx
973 */
974static void tusb_setup_cpu_interface(struct musb *musb)
975{
976 void __iomem *tbase = musb->ctrl_base;
977
978 /*
979 * Disable GPIO[5:0] pullups (used as output DMA requests)
980 * Don't disable GPIO[7:6] as they are needed for wake-up.
981 */
982 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
983
984 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
985 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
986
987 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
988 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
989
990 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
991 * de-assertion time 2 system clocks p 62 */
992 musb_writel(tbase, TUSB_DMA_REQ_CONF,
993 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
994 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
995 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
996
997 /* Set 0 wait count for synchronous burst access */
998 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
999}
1000
1001static int tusb_musb_start(struct musb *musb)
1002{
1003 void __iomem *tbase = musb->ctrl_base;
1004 int ret = 0;
1005 unsigned long flags;
1006 u32 reg;
1007
1008 if (musb->board_set_power)
1009 ret = musb->board_set_power(1);
1010 if (ret != 0) {
1011 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1012 return ret;
1013 }
1014
1015 spin_lock_irqsave(&musb->lock, flags);
1016
1017 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1018 TUSB_PROD_TEST_RESET_VAL) {
1019 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1020 goto err;
1021 }
1022
1023 ret = tusb_print_revision(musb);
1024 if (ret < 2) {
1025 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1026 ret);
1027 goto err;
1028 }
1029
1030 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1031 * NOR FLASH interface is used */
1032 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1033
1034 /* Select PHY free running 60MHz as a system clock */
1035 tusb_set_clock_source(musb, 1);
1036
1037 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1038 * power saving, enable VBus detect and session end comparators,
1039 * enable IDpullup, enable VBus charging */
1040 musb_writel(tbase, TUSB_PRCM_MNGMT,
1041 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1042 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1043 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1044 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1045 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1046 tusb_setup_cpu_interface(musb);
1047
1048 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1049 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1050 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1051 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1052
1053 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1054 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1055 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1056
1057 spin_unlock_irqrestore(&musb->lock, flags);
1058
1059 return 0;
1060
1061err:
1062 spin_unlock_irqrestore(&musb->lock, flags);
1063
1064 if (musb->board_set_power)
1065 musb->board_set_power(0);
1066
1067 return -ENODEV;
1068}
1069
1070static int tusb_musb_init(struct musb *musb)
1071{
1072 struct platform_device *pdev;
1073 struct resource *mem;
1074 void __iomem *sync = NULL;
1075 int ret;
1076
1077 usb_nop_xceiv_register();
1078 musb->xceiv = otg_get_transceiver();
1079 if (!musb->xceiv)
1080 return -ENODEV;
1081
1082 pdev = to_platform_device(musb->controller);
1083
1084 /* dma address for async dma */
1085 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 musb->async = mem->start;
1087
1088 /* dma address for sync dma */
1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1090 if (!mem) {
1091 pr_debug("no sync dma resource?\n");
1092 ret = -ENODEV;
1093 goto done;
1094 }
1095 musb->sync = mem->start;
1096
1097 sync = ioremap(mem->start, resource_size(mem));
1098 if (!sync) {
1099 pr_debug("ioremap for sync failed\n");
1100 ret = -ENOMEM;
1101 goto done;
1102 }
1103 musb->sync_va = sync;
1104
1105 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1106 * FIFOs at 0x600, TUSB at 0x800
1107 */
1108 musb->mregs += TUSB_BASE_OFFSET;
1109
1110 ret = tusb_musb_start(musb);
1111 if (ret) {
1112 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1113 ret);
1114 goto done;
1115 }
1116 musb->isr = tusb_musb_interrupt;
1117
1118 if (is_peripheral_enabled(musb)) {
1119 musb->xceiv->set_power = tusb_draw_power;
1120 the_musb = musb;
1121 }
1122
1123 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1124
1125done:
1126 if (ret < 0) {
1127 if (sync)
1128 iounmap(sync);
1129
1130 otg_put_transceiver(musb->xceiv);
1131 usb_nop_xceiv_unregister();
1132 }
1133 return ret;
1134}
1135
1136static int tusb_musb_exit(struct musb *musb)
1137{
1138 del_timer_sync(&musb_idle_timer);
1139 the_musb = NULL;
1140
1141 if (musb->board_set_power)
1142 musb->board_set_power(0);
1143
1144 iounmap(musb->sync_va);
1145
1146 otg_put_transceiver(musb->xceiv);
1147 usb_nop_xceiv_unregister();
1148 return 0;
1149}
1150
1151static const struct musb_platform_ops tusb_ops = {
1152 .init = tusb_musb_init,
1153 .exit = tusb_musb_exit,
1154
1155 .enable = tusb_musb_enable,
1156 .disable = tusb_musb_disable,
1157
1158 .set_mode = tusb_musb_set_mode,
1159 .try_idle = tusb_musb_try_idle,
1160
1161 .vbus_status = tusb_musb_vbus_status,
1162 .set_vbus = tusb_musb_set_vbus,
1163};
1164
1165static u64 tusb_dmamask = DMA_BIT_MASK(32);
1166
1167static int __init tusb_probe(struct platform_device *pdev)
1168{
1169 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1170 struct platform_device *musb;
1171 struct tusb6010_glue *glue;
1172
1173 int ret = -ENOMEM;
1174
1175 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1176 if (!glue) {
1177 dev_err(&pdev->dev, "failed to allocate glue context\n");
1178 goto err0;
1179 }
1180
1181 musb = platform_device_alloc("musb-hdrc", -1);
1182 if (!musb) {
1183 dev_err(&pdev->dev, "failed to allocate musb device\n");
1184 goto err1;
1185 }
1186
1187 musb->dev.parent = &pdev->dev;
1188 musb->dev.dma_mask = &tusb_dmamask;
1189 musb->dev.coherent_dma_mask = tusb_dmamask;
1190
1191 glue->dev = &pdev->dev;
1192 glue->musb = musb;
1193
1194 pdata->platform_ops = &tusb_ops;
1195
1196 platform_set_drvdata(pdev, glue);
1197
1198 ret = platform_device_add_resources(musb, pdev->resource,
1199 pdev->num_resources);
1200 if (ret) {
1201 dev_err(&pdev->dev, "failed to add resources\n");
1202 goto err2;
1203 }
1204
1205 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1206 if (ret) {
1207 dev_err(&pdev->dev, "failed to add platform_data\n");
1208 goto err2;
1209 }
1210
1211 ret = platform_device_add(musb);
1212 if (ret) {
1213 dev_err(&pdev->dev, "failed to register musb device\n");
1214 goto err1;
1215 }
1216
1217 return 0;
1218
1219err2:
1220 platform_device_put(musb);
1221
1222err1:
1223 kfree(glue);
1224
1225err0:
1226 return ret;
1227}
1228
1229static int __exit tusb_remove(struct platform_device *pdev)
1230{
1231 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1232
1233 platform_device_del(glue->musb);
1234 platform_device_put(glue->musb);
1235 kfree(glue);
1236
1237 return 0;
1238}
1239
1240static struct platform_driver tusb_driver = {
1241 .remove = __exit_p(tusb_remove),
1242 .driver = {
1243 .name = "musb-tusb",
1244 },
1245};
1246
1247MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1248MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1249MODULE_LICENSE("GPL v2");
1250
1251static int __init tusb_init(void)
1252{
1253 return platform_driver_probe(&tusb_driver, tusb_probe);
1254}
1255subsys_initcall(tusb_init);
1256
1257static void __exit tusb_exit(void)
1258{
1259 platform_driver_unregister(&tusb_driver);
1260}
1261module_exit(tusb_exit);