1/*******************************************************************************
  2 *
  3 * Intel Ethernet Controller XL710 Family Linux Driver
  4 * Copyright(c) 2013 - 2014 Intel Corporation.
  5 *
  6 * This program is free software; you can redistribute it and/or modify it
  7 * under the terms and conditions of the GNU General Public License,
  8 * version 2, as published by the Free Software Foundation.
  9 *
 10 * This program is distributed in the hope it will be useful, but WITHOUT
 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13 * more details.
 14 *
 15 * You should have received a copy of the GNU General Public License along
 16 * with this program.  If not, see <http://www.gnu.org/licenses/>.
 17 *
 18 * The full GNU General Public License is included in this distribution in
 19 * the file called "COPYING".
 20 *
 21 * Contact Information:
 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 24 *
 25 ******************************************************************************/
 26
 27#include "i40e_diag.h"
 28#include "i40e_prototype.h"
 29
 30/**
 31 * i40e_diag_reg_pattern_test
 32 * @hw: pointer to the hw struct
 33 * @reg: reg to be tested
 34 * @mask: bits to be touched
 35 **/
 36static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
 37							u32 reg, u32 mask)
 38{
 39	const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 40	u32 pat, val, orig_val;
 41	int i;
 42
 43	orig_val = rd32(hw, reg);
 44	for (i = 0; i < ARRAY_SIZE(patterns); i++) {
 45		pat = patterns[i];
 46		wr32(hw, reg, (pat & mask));
 47		val = rd32(hw, reg);
 48		if ((val & mask) != (pat & mask)) {
 49			i40e_debug(hw, I40E_DEBUG_DIAG,
 50				   "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
 51				   __func__, reg, pat, val);
 52			return I40E_ERR_DIAG_TEST_FAILED;
 53		}
 54	}
 55
 56	wr32(hw, reg, orig_val);
 57	val = rd32(hw, reg);
 58	if (val != orig_val) {
 59		i40e_debug(hw, I40E_DEBUG_DIAG,
 60			   "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
 61			   __func__, reg, orig_val, val);
 62		return I40E_ERR_DIAG_TEST_FAILED;
 63	}
 64
 65	return 0;
 66}
 67
 68struct i40e_diag_reg_test_info i40e_reg_list[] = {
 69	/* offset               mask         elements   stride */
 70	{I40E_QTX_CTL(0),       0x0000FFBF, 1,
 71		I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
 72	{I40E_PFINT_ITR0(0),    0x00000FFF, 3,
 73		I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
 74	{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
 75		I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
 76	{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1,
 77		I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
 78	{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1,
 79		I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
 80	{I40E_PFINT_STAT_CTL0,  0x0000000C, 1, 0},
 81	{I40E_PFINT_LNKLST0,    0x00001FFF, 1, 0},
 82	{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1,
 83		I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
 84	{I40E_QINT_TQCTL(0),    0x000000FF, 1,
 85		I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
 86	{I40E_QINT_RQCTL(0),    0x000000FF, 1,
 87		I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
 88	{I40E_PFINT_ICR0_ENA,   0xF7F20000, 1, 0},
 89	{ 0 }
 90};
 91
 92/**
 93 * i40e_diag_reg_test
 94 * @hw: pointer to the hw struct
 95 *
 96 * Perform registers diagnostic test
 97 **/
 98i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
 99{
100	i40e_status ret_code = 0;
101	u32 reg, mask;
102	u32 i, j;
103
104	for (i = 0; i40e_reg_list[i].offset != 0 &&
105					     !ret_code; i++) {
106
107		/* set actual reg range for dynamically allocated resources */
108		if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
109		    hw->func_caps.num_tx_qp != 0)
110			i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
111		if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
112		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
113		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
114		     i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
115		     i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
116		    hw->func_caps.num_msix_vectors != 0)
117			i40e_reg_list[i].elements =
118				hw->func_caps.num_msix_vectors - 1;
119
120		/* test register access */
121		mask = i40e_reg_list[i].mask;
122		for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
123			reg = i40e_reg_list[i].offset +
124			      (j * i40e_reg_list[i].stride);
125			ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
126		}
127	}
128
129	return ret_code;
130}
131
132/**
133 * i40e_diag_eeprom_test
134 * @hw: pointer to the hw struct
135 *
136 * Perform EEPROM diagnostic test
137 **/
138i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
139{
140	i40e_status ret_code;
141	u16 reg_val;
142
143	/* read NVM control word and if NVM valid, validate EEPROM checksum*/
144	ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
145	if (!ret_code &&
146	    ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
147	     BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))
148		return i40e_validate_nvm_checksum(hw, NULL);
149	else
150		return I40E_ERR_DIAG_TEST_FAILED;
151}