1/*******************************************************************************
   2 *
   3 * Intel Ethernet Controller XL710 Family Linux Driver
   4 * Copyright(c) 2013 - 2016 Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * The full GNU General Public License is included in this distribution in
  19 * the file called "COPYING".
  20 *
  21 * Contact Information:
  22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24 *
  25 ******************************************************************************/
  26
  27#ifndef _I40E_ADMINQ_CMD_H_
  28#define _I40E_ADMINQ_CMD_H_
  29
  30/* This header file defines the i40e Admin Queue commands and is shared between
  31 * i40e Firmware and Software.
  32 *
  33 * This file needs to comply with the Linux Kernel coding style.
  34 */
  35
  36#define I40E_FW_API_VERSION_MAJOR	0x0001
  37#define I40E_FW_API_VERSION_MINOR	0x0005
  38
  39struct i40e_aq_desc {
  40	__le16 flags;
  41	__le16 opcode;
  42	__le16 datalen;
  43	__le16 retval;
  44	__le32 cookie_high;
  45	__le32 cookie_low;
  46	union {
  47		struct {
  48			__le32 param0;
  49			__le32 param1;
  50			__le32 param2;
  51			__le32 param3;
  52		} internal;
  53		struct {
  54			__le32 param0;
  55			__le32 param1;
  56			__le32 addr_high;
  57			__le32 addr_low;
  58		} external;
  59		u8 raw[16];
  60	} params;
  61};
  62
  63/* Flags sub-structure
  64 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  65 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  66 */
  67
  68/* command flags and offsets*/
  69#define I40E_AQ_FLAG_DD_SHIFT	0
  70#define I40E_AQ_FLAG_CMP_SHIFT	1
  71#define I40E_AQ_FLAG_ERR_SHIFT	2
  72#define I40E_AQ_FLAG_VFE_SHIFT	3
  73#define I40E_AQ_FLAG_LB_SHIFT	9
  74#define I40E_AQ_FLAG_RD_SHIFT	10
  75#define I40E_AQ_FLAG_VFC_SHIFT	11
  76#define I40E_AQ_FLAG_BUF_SHIFT	12
  77#define I40E_AQ_FLAG_SI_SHIFT	13
  78#define I40E_AQ_FLAG_EI_SHIFT	14
  79#define I40E_AQ_FLAG_FE_SHIFT	15
  80
  81#define I40E_AQ_FLAG_DD		(1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  82#define I40E_AQ_FLAG_CMP	(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  83#define I40E_AQ_FLAG_ERR	(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  84#define I40E_AQ_FLAG_VFE	(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  85#define I40E_AQ_FLAG_LB		(1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  86#define I40E_AQ_FLAG_RD		(1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  87#define I40E_AQ_FLAG_VFC	(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  88#define I40E_AQ_FLAG_BUF	(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  89#define I40E_AQ_FLAG_SI		(1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  90#define I40E_AQ_FLAG_EI		(1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  91#define I40E_AQ_FLAG_FE		(1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  92
  93/* error codes */
  94enum i40e_admin_queue_err {
  95	I40E_AQ_RC_OK		= 0,  /* success */
  96	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */
  97	I40E_AQ_RC_ENOENT	= 2,  /* No such element */
  98	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */
  99	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */
 100	I40E_AQ_RC_EIO		= 5,  /* I/O error */
 101	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */
 102	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */
 103	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */
 104	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */
 105	I40E_AQ_RC_EACCES	= 10, /* Permission denied */
 106	I40E_AQ_RC_EFAULT	= 11, /* Bad address */
 107	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */
 108	I40E_AQ_RC_EEXIST	= 13, /* object already exists */
 109	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */
 110	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
 111	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */
 112	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */
 113	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */
 114	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
 115	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
 116	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */
 117	I40E_AQ_RC_EFBIG	= 22, /* File too large */
 118};
 119
 120/* Admin Queue command opcodes */
 121enum i40e_admin_queue_opc {
 122	/* aq commands */
 123	i40e_aqc_opc_get_version	= 0x0001,
 124	i40e_aqc_opc_driver_version	= 0x0002,
 125	i40e_aqc_opc_queue_shutdown	= 0x0003,
 126	i40e_aqc_opc_set_pf_context	= 0x0004,
 127
 128	/* resource ownership */
 129	i40e_aqc_opc_request_resource	= 0x0008,
 130	i40e_aqc_opc_release_resource	= 0x0009,
 131
 132	i40e_aqc_opc_list_func_capabilities	= 0x000A,
 133	i40e_aqc_opc_list_dev_capabilities	= 0x000B,
 134
 135	/* LAA */
 136	i40e_aqc_opc_mac_address_read	= 0x0107,
 137	i40e_aqc_opc_mac_address_write	= 0x0108,
 138
 139	/* PXE */
 140	i40e_aqc_opc_clear_pxe_mode	= 0x0110,
 141
 142	/* internal switch commands */
 143	i40e_aqc_opc_get_switch_config		= 0x0200,
 144	i40e_aqc_opc_add_statistics		= 0x0201,
 145	i40e_aqc_opc_remove_statistics		= 0x0202,
 146	i40e_aqc_opc_set_port_parameters	= 0x0203,
 147	i40e_aqc_opc_get_switch_resource_alloc	= 0x0204,
 148	i40e_aqc_opc_set_switch_config		= 0x0205,
 149	i40e_aqc_opc_rx_ctl_reg_read		= 0x0206,
 150	i40e_aqc_opc_rx_ctl_reg_write		= 0x0207,
 151
 152	i40e_aqc_opc_add_vsi			= 0x0210,
 153	i40e_aqc_opc_update_vsi_parameters	= 0x0211,
 154	i40e_aqc_opc_get_vsi_parameters		= 0x0212,
 155
 156	i40e_aqc_opc_add_pv			= 0x0220,
 157	i40e_aqc_opc_update_pv_parameters	= 0x0221,
 158	i40e_aqc_opc_get_pv_parameters		= 0x0222,
 159
 160	i40e_aqc_opc_add_veb			= 0x0230,
 161	i40e_aqc_opc_update_veb_parameters	= 0x0231,
 162	i40e_aqc_opc_get_veb_parameters		= 0x0232,
 163
 164	i40e_aqc_opc_delete_element		= 0x0243,
 165
 166	i40e_aqc_opc_add_macvlan		= 0x0250,
 167	i40e_aqc_opc_remove_macvlan		= 0x0251,
 168	i40e_aqc_opc_add_vlan			= 0x0252,
 169	i40e_aqc_opc_remove_vlan		= 0x0253,
 170	i40e_aqc_opc_set_vsi_promiscuous_modes	= 0x0254,
 171	i40e_aqc_opc_add_tag			= 0x0255,
 172	i40e_aqc_opc_remove_tag			= 0x0256,
 173	i40e_aqc_opc_add_multicast_etag		= 0x0257,
 174	i40e_aqc_opc_remove_multicast_etag	= 0x0258,
 175	i40e_aqc_opc_update_tag			= 0x0259,
 176	i40e_aqc_opc_add_control_packet_filter	= 0x025A,
 177	i40e_aqc_opc_remove_control_packet_filter	= 0x025B,
 178	i40e_aqc_opc_add_cloud_filters		= 0x025C,
 179	i40e_aqc_opc_remove_cloud_filters	= 0x025D,
 180
 181	i40e_aqc_opc_add_mirror_rule	= 0x0260,
 182	i40e_aqc_opc_delete_mirror_rule	= 0x0261,
 183
 184	/* DCB commands */
 185	i40e_aqc_opc_dcb_ignore_pfc	= 0x0301,
 186	i40e_aqc_opc_dcb_updated	= 0x0302,
 187
 188	/* TX scheduler */
 189	i40e_aqc_opc_configure_vsi_bw_limit		= 0x0400,
 190	i40e_aqc_opc_configure_vsi_ets_sla_bw_limit	= 0x0406,
 191	i40e_aqc_opc_configure_vsi_tc_bw		= 0x0407,
 192	i40e_aqc_opc_query_vsi_bw_config		= 0x0408,
 193	i40e_aqc_opc_query_vsi_ets_sla_config		= 0x040A,
 194	i40e_aqc_opc_configure_switching_comp_bw_limit	= 0x0410,
 195
 196	i40e_aqc_opc_enable_switching_comp_ets			= 0x0413,
 197	i40e_aqc_opc_modify_switching_comp_ets			= 0x0414,
 198	i40e_aqc_opc_disable_switching_comp_ets			= 0x0415,
 199	i40e_aqc_opc_configure_switching_comp_ets_bw_limit	= 0x0416,
 200	i40e_aqc_opc_configure_switching_comp_bw_config		= 0x0417,
 201	i40e_aqc_opc_query_switching_comp_ets_config		= 0x0418,
 202	i40e_aqc_opc_query_port_ets_config			= 0x0419,
 203	i40e_aqc_opc_query_switching_comp_bw_config		= 0x041A,
 204	i40e_aqc_opc_suspend_port_tx				= 0x041B,
 205	i40e_aqc_opc_resume_port_tx				= 0x041C,
 206	i40e_aqc_opc_configure_partition_bw			= 0x041D,
 207
 208	/* hmc */
 209	i40e_aqc_opc_query_hmc_resource_profile	= 0x0500,
 210	i40e_aqc_opc_set_hmc_resource_profile	= 0x0501,
 211
 212	/* phy commands*/
 213	i40e_aqc_opc_get_phy_abilities		= 0x0600,
 214	i40e_aqc_opc_set_phy_config		= 0x0601,
 215	i40e_aqc_opc_set_mac_config		= 0x0603,
 216	i40e_aqc_opc_set_link_restart_an	= 0x0605,
 217	i40e_aqc_opc_get_link_status		= 0x0607,
 218	i40e_aqc_opc_set_phy_int_mask		= 0x0613,
 219	i40e_aqc_opc_get_local_advt_reg		= 0x0614,
 220	i40e_aqc_opc_set_local_advt_reg		= 0x0615,
 221	i40e_aqc_opc_get_partner_advt		= 0x0616,
 222	i40e_aqc_opc_set_lb_modes		= 0x0618,
 223	i40e_aqc_opc_get_phy_wol_caps		= 0x0621,
 224	i40e_aqc_opc_set_phy_debug		= 0x0622,
 225	i40e_aqc_opc_upload_ext_phy_fm		= 0x0625,
 226	i40e_aqc_opc_run_phy_activity		= 0x0626,
 227
 228	/* NVM commands */
 229	i40e_aqc_opc_nvm_read			= 0x0701,
 230	i40e_aqc_opc_nvm_erase			= 0x0702,
 231	i40e_aqc_opc_nvm_update			= 0x0703,
 232	i40e_aqc_opc_nvm_config_read		= 0x0704,
 233	i40e_aqc_opc_nvm_config_write		= 0x0705,
 234	i40e_aqc_opc_oem_post_update		= 0x0720,
 235	i40e_aqc_opc_thermal_sensor		= 0x0721,
 236
 237	/* virtualization commands */
 238	i40e_aqc_opc_send_msg_to_pf		= 0x0801,
 239	i40e_aqc_opc_send_msg_to_vf		= 0x0802,
 240	i40e_aqc_opc_send_msg_to_peer		= 0x0803,
 241
 242	/* alternate structure */
 243	i40e_aqc_opc_alternate_write		= 0x0900,
 244	i40e_aqc_opc_alternate_write_indirect	= 0x0901,
 245	i40e_aqc_opc_alternate_read		= 0x0902,
 246	i40e_aqc_opc_alternate_read_indirect	= 0x0903,
 247	i40e_aqc_opc_alternate_write_done	= 0x0904,
 248	i40e_aqc_opc_alternate_set_mode		= 0x0905,
 249	i40e_aqc_opc_alternate_clear_port	= 0x0906,
 250
 251	/* LLDP commands */
 252	i40e_aqc_opc_lldp_get_mib	= 0x0A00,
 253	i40e_aqc_opc_lldp_update_mib	= 0x0A01,
 254	i40e_aqc_opc_lldp_add_tlv	= 0x0A02,
 255	i40e_aqc_opc_lldp_update_tlv	= 0x0A03,
 256	i40e_aqc_opc_lldp_delete_tlv	= 0x0A04,
 257	i40e_aqc_opc_lldp_stop		= 0x0A05,
 258	i40e_aqc_opc_lldp_start		= 0x0A06,
 259	i40e_aqc_opc_get_cee_dcb_cfg	= 0x0A07,
 260	i40e_aqc_opc_lldp_set_local_mib	= 0x0A08,
 261	i40e_aqc_opc_lldp_stop_start_spec_agent	= 0x0A09,
 262
 263	/* Tunnel commands */
 264	i40e_aqc_opc_add_udp_tunnel	= 0x0B00,
 265	i40e_aqc_opc_del_udp_tunnel	= 0x0B01,
 266	i40e_aqc_opc_set_rss_key	= 0x0B02,
 267	i40e_aqc_opc_set_rss_lut	= 0x0B03,
 268	i40e_aqc_opc_get_rss_key	= 0x0B04,
 269	i40e_aqc_opc_get_rss_lut	= 0x0B05,
 270
 271	/* Async Events */
 272	i40e_aqc_opc_event_lan_overflow		= 0x1001,
 273
 274	/* OEM commands */
 275	i40e_aqc_opc_oem_parameter_change	= 0xFE00,
 276	i40e_aqc_opc_oem_device_status_change	= 0xFE01,
 277	i40e_aqc_opc_oem_ocsd_initialize	= 0xFE02,
 278	i40e_aqc_opc_oem_ocbb_initialize	= 0xFE03,
 279
 280	/* debug commands */
 281	i40e_aqc_opc_debug_read_reg		= 0xFF03,
 282	i40e_aqc_opc_debug_write_reg		= 0xFF04,
 283	i40e_aqc_opc_debug_modify_reg		= 0xFF07,
 284	i40e_aqc_opc_debug_dump_internals	= 0xFF08,
 285};
 286
 287/* command structures and indirect data structures */
 288
 289/* Structure naming conventions:
 290 * - no suffix for direct command descriptor structures
 291 * - _data for indirect sent data
 292 * - _resp for indirect return data (data which is both will use _data)
 293 * - _completion for direct return data
 294 * - _element_ for repeated elements (may also be _data or _resp)
 295 *
 296 * Command structures are expected to overlay the params.raw member of the basic
 297 * descriptor, and as such cannot exceed 16 bytes in length.
 298 */
 299
 300/* This macro is used to generate a compilation error if a structure
 301 * is not exactly the correct length. It gives a divide by zero error if the
 302 * structure is not of the correct size, otherwise it creates an enum that is
 303 * never used.
 304 */
 305#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
 306	{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 307
 308/* This macro is used extensively to ensure that command structures are 16
 309 * bytes in length as they have to map to the raw array of that size.
 310 */
 311#define I40E_CHECK_CMD_LENGTH(X)	I40E_CHECK_STRUCT_LEN(16, X)
 312
 313/* internal (0x00XX) commands */
 314
 315/* Get version (direct 0x0001) */
 316struct i40e_aqc_get_version {
 317	__le32 rom_ver;
 318	__le32 fw_build;
 319	__le16 fw_major;
 320	__le16 fw_minor;
 321	__le16 api_major;
 322	__le16 api_minor;
 323};
 324
 325I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
 326
 327/* Send driver version (indirect 0x0002) */
 328struct i40e_aqc_driver_version {
 329	u8	driver_major_ver;
 330	u8	driver_minor_ver;
 331	u8	driver_build_ver;
 332	u8	driver_subbuild_ver;
 333	u8	reserved[4];
 334	__le32	address_high;
 335	__le32	address_low;
 336};
 337
 338I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
 339
 340/* Queue Shutdown (direct 0x0003) */
 341struct i40e_aqc_queue_shutdown {
 342	__le32	driver_unloading;
 343#define I40E_AQ_DRIVER_UNLOADING	0x1
 344	u8	reserved[12];
 345};
 346
 347I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
 348
 349/* Set PF context (0x0004, direct) */
 350struct i40e_aqc_set_pf_context {
 351	u8	pf_id;
 352	u8	reserved[15];
 353};
 354
 355I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
 356
 357/* Request resource ownership (direct 0x0008)
 358 * Release resource ownership (direct 0x0009)
 359 */
 360#define I40E_AQ_RESOURCE_NVM			1
 361#define I40E_AQ_RESOURCE_SDP			2
 362#define I40E_AQ_RESOURCE_ACCESS_READ		1
 363#define I40E_AQ_RESOURCE_ACCESS_WRITE		2
 364#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT	3000
 365#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT	180000
 366
 367struct i40e_aqc_request_resource {
 368	__le16	resource_id;
 369	__le16	access_type;
 370	__le32	timeout;
 371	__le32	resource_number;
 372	u8	reserved[4];
 373};
 374
 375I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
 376
 377/* Get function capabilities (indirect 0x000A)
 378 * Get device capabilities (indirect 0x000B)
 379 */
 380struct i40e_aqc_list_capabilites {
 381	u8 command_flags;
 382#define I40E_AQ_LIST_CAP_PF_INDEX_EN	1
 383	u8 pf_index;
 384	u8 reserved[2];
 385	__le32 count;
 386	__le32 addr_high;
 387	__le32 addr_low;
 388};
 389
 390I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
 391
 392struct i40e_aqc_list_capabilities_element_resp {
 393	__le16	id;
 394	u8	major_rev;
 395	u8	minor_rev;
 396	__le32	number;
 397	__le32	logical_id;
 398	__le32	phys_id;
 399	u8	reserved[16];
 400};
 401
 402/* list of caps */
 403
 404#define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001
 405#define I40E_AQ_CAP_ID_MNG_MODE		0x0002
 406#define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003
 407#define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004
 408#define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005
 409#define I40E_AQ_CAP_ID_ALTERNATE_RAM	0x0006
 410#define I40E_AQ_CAP_ID_WOL_AND_PROXY	0x0008
 411#define I40E_AQ_CAP_ID_SRIOV		0x0012
 412#define I40E_AQ_CAP_ID_VF		0x0013
 413#define I40E_AQ_CAP_ID_VMDQ		0x0014
 414#define I40E_AQ_CAP_ID_8021QBG		0x0015
 415#define I40E_AQ_CAP_ID_8021QBR		0x0016
 416#define I40E_AQ_CAP_ID_VSI		0x0017
 417#define I40E_AQ_CAP_ID_DCB		0x0018
 418#define I40E_AQ_CAP_ID_FCOE		0x0021
 419#define I40E_AQ_CAP_ID_ISCSI		0x0022
 420#define I40E_AQ_CAP_ID_RSS		0x0040
 421#define I40E_AQ_CAP_ID_RXQ		0x0041
 422#define I40E_AQ_CAP_ID_TXQ		0x0042
 423#define I40E_AQ_CAP_ID_MSIX		0x0043
 424#define I40E_AQ_CAP_ID_VF_MSIX		0x0044
 425#define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045
 426#define I40E_AQ_CAP_ID_1588		0x0046
 427#define I40E_AQ_CAP_ID_IWARP		0x0051
 428#define I40E_AQ_CAP_ID_LED		0x0061
 429#define I40E_AQ_CAP_ID_SDP		0x0062
 430#define I40E_AQ_CAP_ID_MDIO		0x0063
 431#define I40E_AQ_CAP_ID_WSR_PROT		0x0064
 432#define I40E_AQ_CAP_ID_FLEX10		0x00F1
 433#define I40E_AQ_CAP_ID_CEM		0x00F2
 434
 435/* Set CPPM Configuration (direct 0x0103) */
 436struct i40e_aqc_cppm_configuration {
 437	__le16	command_flags;
 438#define I40E_AQ_CPPM_EN_LTRC	0x0800
 439#define I40E_AQ_CPPM_EN_DMCTH	0x1000
 440#define I40E_AQ_CPPM_EN_DMCTLX	0x2000
 441#define I40E_AQ_CPPM_EN_HPTC	0x4000
 442#define I40E_AQ_CPPM_EN_DMARC	0x8000
 443	__le16	ttlx;
 444	__le32	dmacr;
 445	__le16	dmcth;
 446	u8	hptc;
 447	u8	reserved;
 448	__le32	pfltrc;
 449};
 450
 451I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
 452
 453/* Set ARP Proxy command / response (indirect 0x0104) */
 454struct i40e_aqc_arp_proxy_data {
 455	__le16	command_flags;
 456#define I40E_AQ_ARP_INIT_IPV4	0x0008
 457#define I40E_AQ_ARP_UNSUP_CTL	0x0010
 458#define I40E_AQ_ARP_ENA		0x0020
 459#define I40E_AQ_ARP_ADD_IPV4	0x0040
 460#define I40E_AQ_ARP_DEL_IPV4	0x0080
 461	__le16	table_id;
 462	__le32	pfpm_proxyfc;
 463	__le32	ip_addr;
 464	u8	mac_addr[6];
 465	u8	reserved[2];
 466};
 467
 468I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
 469
 470/* Set NS Proxy Table Entry Command (indirect 0x0105) */
 471struct i40e_aqc_ns_proxy_data {
 472	__le16	table_idx_mac_addr_0;
 473	__le16	table_idx_mac_addr_1;
 474	__le16	table_idx_ipv6_0;
 475	__le16	table_idx_ipv6_1;
 476	__le16	control;
 477#define I40E_AQ_NS_PROXY_ADD_0		0x0100
 478#define I40E_AQ_NS_PROXY_DEL_0		0x0200
 479#define I40E_AQ_NS_PROXY_ADD_1		0x0400
 480#define I40E_AQ_NS_PROXY_DEL_1		0x0800
 481#define I40E_AQ_NS_PROXY_ADD_IPV6_0	0x1000
 482#define I40E_AQ_NS_PROXY_DEL_IPV6_0	0x2000
 483#define I40E_AQ_NS_PROXY_ADD_IPV6_1	0x4000
 484#define I40E_AQ_NS_PROXY_DEL_IPV6_1	0x8000
 485#define I40E_AQ_NS_PROXY_COMMAND_SEQ	0x0001
 486#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL	0x0002
 487#define I40E_AQ_NS_PROXY_INIT_MAC_TBL	0x0004
 488	u8	mac_addr_0[6];
 489	u8	mac_addr_1[6];
 490	u8	local_mac_addr[6];
 491	u8	ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 492	u8	ipv6_addr_1[16];
 493};
 494
 495I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
 496
 497/* Manage LAA Command (0x0106) - obsolete */
 498struct i40e_aqc_mng_laa {
 499	__le16	command_flags;
 500#define I40E_AQ_LAA_FLAG_WR	0x8000
 501	u8	reserved[2];
 502	__le32	sal;
 503	__le16	sah;
 504	u8	reserved2[6];
 505};
 506
 507I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
 508
 509/* Manage MAC Address Read Command (indirect 0x0107) */
 510struct i40e_aqc_mac_address_read {
 511	__le16	command_flags;
 512#define I40E_AQC_LAN_ADDR_VALID		0x10
 513#define I40E_AQC_SAN_ADDR_VALID		0x20
 514#define I40E_AQC_PORT_ADDR_VALID	0x40
 515#define I40E_AQC_WOL_ADDR_VALID		0x80
 516#define I40E_AQC_MC_MAG_EN_VALID	0x100
 517#define I40E_AQC_ADDR_VALID_MASK	0x1F0
 518	u8	reserved[6];
 519	__le32	addr_high;
 520	__le32	addr_low;
 521};
 522
 523I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
 524
 525struct i40e_aqc_mac_address_read_data {
 526	u8 pf_lan_mac[6];
 527	u8 pf_san_mac[6];
 528	u8 port_mac[6];
 529	u8 pf_wol_mac[6];
 530};
 531
 532I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
 533
 534/* Manage MAC Address Write Command (0x0108) */
 535struct i40e_aqc_mac_address_write {
 536	__le16	command_flags;
 537#define I40E_AQC_WRITE_TYPE_LAA_ONLY	0x0000
 538#define I40E_AQC_WRITE_TYPE_LAA_WOL	0x4000
 539#define I40E_AQC_WRITE_TYPE_PORT	0x8000
 540#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG	0xC000
 541#define I40E_AQC_WRITE_TYPE_MASK	0xC000
 542
 543	__le16	mac_sah;
 544	__le32	mac_sal;
 545	u8	reserved[8];
 546};
 547
 548I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
 549
 550/* PXE commands (0x011x) */
 551
 552/* Clear PXE Command and response  (direct 0x0110) */
 553struct i40e_aqc_clear_pxe {
 554	u8	rx_cnt;
 555	u8	reserved[15];
 556};
 557
 558I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
 559
 560/* Switch configuration commands (0x02xx) */
 561
 562/* Used by many indirect commands that only pass an seid and a buffer in the
 563 * command
 564 */
 565struct i40e_aqc_switch_seid {
 566	__le16	seid;
 567	u8	reserved[6];
 568	__le32	addr_high;
 569	__le32	addr_low;
 570};
 571
 572I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
 573
 574/* Get Switch Configuration command (indirect 0x0200)
 575 * uses i40e_aqc_switch_seid for the descriptor
 576 */
 577struct i40e_aqc_get_switch_config_header_resp {
 578	__le16	num_reported;
 579	__le16	num_total;
 580	u8	reserved[12];
 581};
 582
 583I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
 584
 585struct i40e_aqc_switch_config_element_resp {
 586	u8	element_type;
 587#define I40E_AQ_SW_ELEM_TYPE_MAC	1
 588#define I40E_AQ_SW_ELEM_TYPE_PF		2
 589#define I40E_AQ_SW_ELEM_TYPE_VF		3
 590#define I40E_AQ_SW_ELEM_TYPE_EMP	4
 591#define I40E_AQ_SW_ELEM_TYPE_BMC	5
 592#define I40E_AQ_SW_ELEM_TYPE_PV		16
 593#define I40E_AQ_SW_ELEM_TYPE_VEB	17
 594#define I40E_AQ_SW_ELEM_TYPE_PA		18
 595#define I40E_AQ_SW_ELEM_TYPE_VSI	19
 596	u8	revision;
 597#define I40E_AQ_SW_ELEM_REV_1		1
 598	__le16	seid;
 599	__le16	uplink_seid;
 600	__le16	downlink_seid;
 601	u8	reserved[3];
 602	u8	connection_type;
 603#define I40E_AQ_CONN_TYPE_REGULAR	0x1
 604#define I40E_AQ_CONN_TYPE_DEFAULT	0x2
 605#define I40E_AQ_CONN_TYPE_CASCADED	0x3
 606	__le16	scheduler_id;
 607	__le16	element_info;
 608};
 609
 610I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
 611
 612/* Get Switch Configuration (indirect 0x0200)
 613 *    an array of elements are returned in the response buffer
 614 *    the first in the array is the header, remainder are elements
 615 */
 616struct i40e_aqc_get_switch_config_resp {
 617	struct i40e_aqc_get_switch_config_header_resp	header;
 618	struct i40e_aqc_switch_config_element_resp	element[1];
 619};
 620
 621I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
 622
 623/* Add Statistics (direct 0x0201)
 624 * Remove Statistics (direct 0x0202)
 625 */
 626struct i40e_aqc_add_remove_statistics {
 627	__le16	seid;
 628	__le16	vlan;
 629	__le16	stat_index;
 630	u8	reserved[10];
 631};
 632
 633I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
 634
 635/* Set Port Parameters command (direct 0x0203) */
 636struct i40e_aqc_set_port_parameters {
 637	__le16	command_flags;
 638#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS	1
 639#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS	2 /* must set! */
 640#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA	4
 641	__le16	bad_frame_vsi;
 642	__le16	default_seid;        /* reserved for command */
 643	u8	reserved[10];
 644};
 645
 646I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
 647
 648/* Get Switch Resource Allocation (indirect 0x0204) */
 649struct i40e_aqc_get_switch_resource_alloc {
 650	u8	num_entries;         /* reserved for command */
 651	u8	reserved[7];
 652	__le32	addr_high;
 653	__le32	addr_low;
 654};
 655
 656I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
 657
 658/* expect an array of these structs in the response buffer */
 659struct i40e_aqc_switch_resource_alloc_element_resp {
 660	u8	resource_type;
 661#define I40E_AQ_RESOURCE_TYPE_VEB		0x0
 662#define I40E_AQ_RESOURCE_TYPE_VSI		0x1
 663#define I40E_AQ_RESOURCE_TYPE_MACADDR		0x2
 664#define I40E_AQ_RESOURCE_TYPE_STAG		0x3
 665#define I40E_AQ_RESOURCE_TYPE_ETAG		0x4
 666#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH	0x5
 667#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH	0x6
 668#define I40E_AQ_RESOURCE_TYPE_VLAN		0x7
 669#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY	0x8
 670#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY	0x9
 671#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL	0xA
 672#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE	0xB
 673#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS	0xC
 674#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS	0xD
 675#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS	0xF
 676#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS	0x10
 677#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS	0x11
 678#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS		0x12
 679#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS	0x13
 680	u8	reserved1;
 681	__le16	guaranteed;
 682	__le16	total;
 683	__le16	used;
 684	__le16	total_unalloced;
 685	u8	reserved2[6];
 686};
 687
 688I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
 689
 690/* Set Switch Configuration (direct 0x0205) */
 691struct i40e_aqc_set_switch_config {
 692	__le16	flags;
 693#define I40E_AQ_SET_SWITCH_CFG_PROMISC		0x0001
 694#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER	0x0002
 695	__le16	valid_flags;
 696	u8	reserved[12];
 697};
 698
 699I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
 700
 701/* Read Receive control registers  (direct 0x0206)
 702 * Write Receive control registers (direct 0x0207)
 703 *     used for accessing Rx control registers that can be
 704 *     slow and need special handling when under high Rx load
 705 */
 706struct i40e_aqc_rx_ctl_reg_read_write {
 707	__le32 reserved1;
 708	__le32 address;
 709	__le32 reserved2;
 710	__le32 value;
 711};
 712
 713I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
 714
 715/* Add VSI (indirect 0x0210)
 716 *    this indirect command uses struct i40e_aqc_vsi_properties_data
 717 *    as the indirect buffer (128 bytes)
 718 *
 719 * Update VSI (indirect 0x211)
 720 *     uses the same data structure as Add VSI
 721 *
 722 * Get VSI (indirect 0x0212)
 723 *     uses the same completion and data structure as Add VSI
 724 */
 725struct i40e_aqc_add_get_update_vsi {
 726	__le16	uplink_seid;
 727	u8	connection_type;
 728#define I40E_AQ_VSI_CONN_TYPE_NORMAL	0x1
 729#define I40E_AQ_VSI_CONN_TYPE_DEFAULT	0x2
 730#define I40E_AQ_VSI_CONN_TYPE_CASCADED	0x3
 731	u8	reserved1;
 732	u8	vf_id;
 733	u8	reserved2;
 734	__le16	vsi_flags;
 735#define I40E_AQ_VSI_TYPE_SHIFT		0x0
 736#define I40E_AQ_VSI_TYPE_MASK		(0x3 << I40E_AQ_VSI_TYPE_SHIFT)
 737#define I40E_AQ_VSI_TYPE_VF		0x0
 738#define I40E_AQ_VSI_TYPE_VMDQ2		0x1
 739#define I40E_AQ_VSI_TYPE_PF		0x2
 740#define I40E_AQ_VSI_TYPE_EMP_MNG	0x3
 741#define I40E_AQ_VSI_FLAG_CASCADED_PV	0x4
 742	__le32	addr_high;
 743	__le32	addr_low;
 744};
 745
 746I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
 747
 748struct i40e_aqc_add_get_update_vsi_completion {
 749	__le16 seid;
 750	__le16 vsi_number;
 751	__le16 vsi_used;
 752	__le16 vsi_free;
 753	__le32 addr_high;
 754	__le32 addr_low;
 755};
 756
 757I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
 758
 759struct i40e_aqc_vsi_properties_data {
 760	/* first 96 byte are written by SW */
 761	__le16	valid_sections;
 762#define I40E_AQ_VSI_PROP_SWITCH_VALID		0x0001
 763#define I40E_AQ_VSI_PROP_SECURITY_VALID		0x0002
 764#define I40E_AQ_VSI_PROP_VLAN_VALID		0x0004
 765#define I40E_AQ_VSI_PROP_CAS_PV_VALID		0x0008
 766#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID	0x0010
 767#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID	0x0020
 768#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID	0x0040
 769#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID	0x0080
 770#define I40E_AQ_VSI_PROP_OUTER_UP_VALID		0x0100
 771#define I40E_AQ_VSI_PROP_SCHED_VALID		0x0200
 772	/* switch section */
 773	__le16	switch_id; /* 12bit id combined with flags below */
 774#define I40E_AQ_VSI_SW_ID_SHIFT		0x0000
 775#define I40E_AQ_VSI_SW_ID_MASK		(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
 776#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG	0x1000
 777#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB	0x2000
 778#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB	0x4000
 779	u8	sw_reserved[2];
 780	/* security section */
 781	u8	sec_flags;
 782#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	0x01
 783#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK	0x02
 784#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK	0x04
 785	u8	sec_reserved;
 786	/* VLAN section */
 787	__le16	pvid; /* VLANS include priority bits */
 788	__le16	fcoe_pvid;
 789	u8	port_vlan_flags;
 790#define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
 791#define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
 792					 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
 793#define I40E_AQ_VSI_PVLAN_MODE_TAGGED	0x01
 794#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED	0x02
 795#define I40E_AQ_VSI_PVLAN_MODE_ALL	0x03
 796#define I40E_AQ_VSI_PVLAN_INSERT_PVID	0x04
 797#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT	0x03
 798#define I40E_AQ_VSI_PVLAN_EMOD_MASK	(0x3 << \
 799					 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
 800#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH	0x0
 801#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP	0x08
 802#define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
 803#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
 804	u8	pvlan_reserved[3];
 805	/* ingress egress up sections */
 806	__le32	ingress_table; /* bitmap, 3 bits per up */
 807#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT	0
 808#define I40E_AQ_VSI_UP_TABLE_UP0_MASK	(0x7 << \
 809					 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
 810#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT	3
 811#define I40E_AQ_VSI_UP_TABLE_UP1_MASK	(0x7 << \
 812					 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
 813#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT	6
 814#define I40E_AQ_VSI_UP_TABLE_UP2_MASK	(0x7 << \
 815					 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
 816#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT	9
 817#define I40E_AQ_VSI_UP_TABLE_UP3_MASK	(0x7 << \
 818					 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
 819#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT	12
 820#define I40E_AQ_VSI_UP_TABLE_UP4_MASK	(0x7 << \
 821					 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
 822#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT	15
 823#define I40E_AQ_VSI_UP_TABLE_UP5_MASK	(0x7 << \
 824					 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
 825#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT	18
 826#define I40E_AQ_VSI_UP_TABLE_UP6_MASK	(0x7 << \
 827					 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
 828#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT	21
 829#define I40E_AQ_VSI_UP_TABLE_UP7_MASK	(0x7 << \
 830					 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
 831	__le32	egress_table;   /* same defines as for ingress table */
 832	/* cascaded PV section */
 833	__le16	cas_pv_tag;
 834	u8	cas_pv_flags;
 835#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT		0x00
 836#define I40E_AQ_VSI_CAS_PV_TAGX_MASK		(0x03 << \
 837						 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
 838#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE		0x00
 839#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE		0x01
 840#define I40E_AQ_VSI_CAS_PV_TAGX_COPY		0x02
 841#define I40E_AQ_VSI_CAS_PV_INSERT_TAG		0x10
 842#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE		0x20
 843#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG	0x40
 844	u8	cas_pv_reserved;
 845	/* queue mapping section */
 846	__le16	mapping_flags;
 847#define I40E_AQ_VSI_QUE_MAP_CONTIG	0x0
 848#define I40E_AQ_VSI_QUE_MAP_NONCONTIG	0x1
 849	__le16	queue_mapping[16];
 850#define I40E_AQ_VSI_QUEUE_SHIFT		0x0
 851#define I40E_AQ_VSI_QUEUE_MASK		(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
 852	__le16	tc_mapping[8];
 853#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT	0
 854#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK	(0x1FF << \
 855					 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 856#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT	9
 857#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK	(0x7 << \
 858					 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 859	/* queueing option section */
 860	u8	queueing_opt_flags;
 861#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA	0x04
 862#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA	0x08
 863#define I40E_AQ_VSI_QUE_OPT_TCP_ENA	0x10
 864#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA	0x20
 865#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF	0x00
 866#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI	0x40
 867	u8	queueing_opt_reserved[3];
 868	/* scheduler section */
 869	u8	up_enable_bits;
 870	u8	sched_reserved;
 871	/* outer up section */
 872	__le32	outer_up_table; /* same structure and defines as ingress tbl */
 873	u8	cmd_reserved[8];
 874	/* last 32 bytes are written by FW */
 875	__le16	qs_handle[8];
 876#define I40E_AQ_VSI_QS_HANDLE_INVALID	0xFFFF
 877	__le16	stat_counter_idx;
 878	__le16	sched_id;
 879	u8	resp_reserved[12];
 880};
 881
 882I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
 883
 884/* Add Port Virtualizer (direct 0x0220)
 885 * also used for update PV (direct 0x0221) but only flags are used
 886 * (IS_CTRL_PORT only works on add PV)
 887 */
 888struct i40e_aqc_add_update_pv {
 889	__le16	command_flags;
 890#define I40E_AQC_PV_FLAG_PV_TYPE		0x1
 891#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN	0x2
 892#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN	0x4
 893#define I40E_AQC_PV_FLAG_IS_CTRL_PORT		0x8
 894	__le16	uplink_seid;
 895	__le16	connected_seid;
 896	u8	reserved[10];
 897};
 898
 899I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
 900
 901struct i40e_aqc_add_update_pv_completion {
 902	/* reserved for update; for add also encodes error if rc == ENOSPC */
 903	__le16	pv_seid;
 904#define I40E_AQC_PV_ERR_FLAG_NO_PV	0x1
 905#define I40E_AQC_PV_ERR_FLAG_NO_SCHED	0x2
 906#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER	0x4
 907#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY	0x8
 908	u8	reserved[14];
 909};
 910
 911I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
 912
 913/* Get PV Params (direct 0x0222)
 914 * uses i40e_aqc_switch_seid for the descriptor
 915 */
 916
 917struct i40e_aqc_get_pv_params_completion {
 918	__le16	seid;
 919	__le16	default_stag;
 920	__le16	pv_flags; /* same flags as add_pv */
 921#define I40E_AQC_GET_PV_PV_TYPE			0x1
 922#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG	0x2
 923#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG	0x4
 924	u8	reserved[8];
 925	__le16	default_port_seid;
 926};
 927
 928I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
 929
 930/* Add VEB (direct 0x0230) */
 931struct i40e_aqc_add_veb {
 932	__le16	uplink_seid;
 933	__le16	downlink_seid;
 934	__le16	veb_flags;
 935#define I40E_AQC_ADD_VEB_FLOATING		0x1
 936#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT	1
 937#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK		(0x3 << \
 938					I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
 939#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT	0x2
 940#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA		0x4
 941#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER	0x8     /* deprecated */
 942#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS	0x10
 943	u8	enable_tcs;
 944	u8	reserved[9];
 945};
 946
 947I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
 948
 949struct i40e_aqc_add_veb_completion {
 950	u8	reserved[6];
 951	__le16	switch_seid;
 952	/* also encodes error if rc == ENOSPC; codes are the same as add_pv */
 953	__le16	veb_seid;
 954#define I40E_AQC_VEB_ERR_FLAG_NO_VEB		0x1
 955#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED		0x2
 956#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER	0x4
 957#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY		0x8
 958	__le16	statistic_index;
 959	__le16	vebs_used;
 960	__le16	vebs_free;
 961};
 962
 963I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
 964
 965/* Get VEB Parameters (direct 0x0232)
 966 * uses i40e_aqc_switch_seid for the descriptor
 967 */
 968struct i40e_aqc_get_veb_parameters_completion {
 969	__le16	seid;
 970	__le16	switch_id;
 971	__le16	veb_flags; /* only the first/last flags from 0x0230 is valid */
 972	__le16	statistic_index;
 973	__le16	vebs_used;
 974	__le16	vebs_free;
 975	u8	reserved[4];
 976};
 977
 978I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
 979
 980/* Delete Element (direct 0x0243)
 981 * uses the generic i40e_aqc_switch_seid
 982 */
 983
 984/* Add MAC-VLAN (indirect 0x0250) */
 985
 986/* used for the command for most vlan commands */
 987struct i40e_aqc_macvlan {
 988	__le16	num_addresses;
 989	__le16	seid[3];
 990#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT	0
 991#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK	(0x3FF << \
 992					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
 993#define I40E_AQC_MACVLAN_CMD_SEID_VALID		0x8000
 994	__le32	addr_high;
 995	__le32	addr_low;
 996};
 997
 998I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
 999
1000/* indirect data for command and response */
1001struct i40e_aqc_add_macvlan_element_data {
1002	u8	mac_addr[6];
1003	__le16	vlan_tag;
1004	__le16	flags;
1005#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH	0x0001
1006#define I40E_AQC_MACVLAN_ADD_HASH_MATCH		0x0002
1007#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN	0x0004
1008#define I40E_AQC_MACVLAN_ADD_TO_QUEUE		0x0008
1009#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC	0x0010
1010	__le16	queue_number;
1011#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT	0
1012#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK		(0x7FF << \
1013					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1014	/* response section */
1015	u8	match_method;
1016#define I40E_AQC_MM_PERFECT_MATCH	0x01
1017#define I40E_AQC_MM_HASH_MATCH		0x02
1018#define I40E_AQC_MM_ERR_NO_RES		0xFF
1019	u8	reserved1[3];
1020};
1021
1022struct i40e_aqc_add_remove_macvlan_completion {
1023	__le16 perfect_mac_used;
1024	__le16 perfect_mac_free;
1025	__le16 unicast_hash_free;
1026	__le16 multicast_hash_free;
1027	__le32 addr_high;
1028	__le32 addr_low;
1029};
1030
1031I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1032
1033/* Remove MAC-VLAN (indirect 0x0251)
1034 * uses i40e_aqc_macvlan for the descriptor
1035 * data points to an array of num_addresses of elements
1036 */
1037
1038struct i40e_aqc_remove_macvlan_element_data {
1039	u8	mac_addr[6];
1040	__le16	vlan_tag;
1041	u8	flags;
1042#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH	0x01
1043#define I40E_AQC_MACVLAN_DEL_HASH_MATCH		0x02
1044#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN	0x08
1045#define I40E_AQC_MACVLAN_DEL_ALL_VSIS		0x10
1046	u8	reserved[3];
1047	/* reply section */
1048	u8	error_code;
1049#define I40E_AQC_REMOVE_MACVLAN_SUCCESS		0x0
1050#define I40E_AQC_REMOVE_MACVLAN_FAIL		0xFF
1051	u8	reply_reserved[3];
1052};
1053
1054/* Add VLAN (indirect 0x0252)
1055 * Remove VLAN (indirect 0x0253)
1056 * use the generic i40e_aqc_macvlan for the command
1057 */
1058struct i40e_aqc_add_remove_vlan_element_data {
1059	__le16	vlan_tag;
1060	u8	vlan_flags;
1061/* flags for add VLAN */
1062#define I40E_AQC_ADD_VLAN_LOCAL			0x1
1063#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT		1
1064#define I40E_AQC_ADD_PVLAN_TYPE_MASK	(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1065#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR		0x0
1066#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY		0x2
1067#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY	0x4
1068#define I40E_AQC_VLAN_PTYPE_SHIFT		3
1069#define I40E_AQC_VLAN_PTYPE_MASK	(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1070#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI		0x0
1071#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI		0x8
1072#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI	0x10
1073#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI	0x18
1074/* flags for remove VLAN */
1075#define I40E_AQC_REMOVE_VLAN_ALL	0x1
1076	u8	reserved;
1077	u8	result;
1078/* flags for add VLAN */
1079#define I40E_AQC_ADD_VLAN_SUCCESS	0x0
1080#define I40E_AQC_ADD_VLAN_FAIL_REQUEST	0xFE
1081#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE	0xFF
1082/* flags for remove VLAN */
1083#define I40E_AQC_REMOVE_VLAN_SUCCESS	0x0
1084#define I40E_AQC_REMOVE_VLAN_FAIL	0xFF
1085	u8	reserved1[3];
1086};
1087
1088struct i40e_aqc_add_remove_vlan_completion {
1089	u8	reserved[4];
1090	__le16	vlans_used;
1091	__le16	vlans_free;
1092	__le32	addr_high;
1093	__le32	addr_low;
1094};
1095
1096/* Set VSI Promiscuous Modes (direct 0x0254) */
1097struct i40e_aqc_set_vsi_promiscuous_modes {
1098	__le16	promiscuous_flags;
1099	__le16	valid_flags;
1100/* flags used for both fields above */
1101#define I40E_AQC_SET_VSI_PROMISC_UNICAST	0x01
1102#define I40E_AQC_SET_VSI_PROMISC_MULTICAST	0x02
1103#define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
1104#define I40E_AQC_SET_VSI_DEFAULT		0x08
1105#define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
1106#define I40E_AQC_SET_VSI_PROMISC_TX		0x8000
1107	__le16	seid;
1108#define I40E_AQC_VSI_PROM_CMD_SEID_MASK		0x3FF
1109	__le16	vlan_tag;
1110#define I40E_AQC_SET_VSI_VLAN_MASK		0x0FFF
1111#define I40E_AQC_SET_VSI_VLAN_VALID		0x8000
1112	u8	reserved[8];
1113};
1114
1115I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1116
1117/* Add S/E-tag command (direct 0x0255)
1118 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1119 */
1120struct i40e_aqc_add_tag {
1121	__le16	flags;
1122#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE		0x0001
1123	__le16	seid;
1124#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT	0
1125#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1126					I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1127	__le16	tag;
1128	__le16	queue_number;
1129	u8	reserved[8];
1130};
1131
1132I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1133
1134struct i40e_aqc_add_remove_tag_completion {
1135	u8	reserved[12];
1136	__le16	tags_used;
1137	__le16	tags_free;
1138};
1139
1140I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1141
1142/* Remove S/E-tag command (direct 0x0256)
1143 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1144 */
1145struct i40e_aqc_remove_tag {
1146	__le16	seid;
1147#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT	0
1148#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1149					I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1150	__le16	tag;
1151	u8	reserved[12];
1152};
1153
1154I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1155
1156/* Add multicast E-Tag (direct 0x0257)
1157 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1158 * and no external data
1159 */
1160struct i40e_aqc_add_remove_mcast_etag {
1161	__le16	pv_seid;
1162	__le16	etag;
1163	u8	num_unicast_etags;
1164	u8	reserved[3];
1165	__le32	addr_high;          /* address of array of 2-byte s-tags */
1166	__le32	addr_low;
1167};
1168
1169I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1170
1171struct i40e_aqc_add_remove_mcast_etag_completion {
1172	u8	reserved[4];
1173	__le16	mcast_etags_used;
1174	__le16	mcast_etags_free;
1175	__le32	addr_high;
1176	__le32	addr_low;
1177
1178};
1179
1180I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1181
1182/* Update S/E-Tag (direct 0x0259) */
1183struct i40e_aqc_update_tag {
1184	__le16	seid;
1185#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT	0
1186#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1187					I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1188	__le16	old_tag;
1189	__le16	new_tag;
1190	u8	reserved[10];
1191};
1192
1193I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1194
1195struct i40e_aqc_update_tag_completion {
1196	u8	reserved[12];
1197	__le16	tags_used;
1198	__le16	tags_free;
1199};
1200
1201I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1202
1203/* Add Control Packet filter (direct 0x025A)
1204 * Remove Control Packet filter (direct 0x025B)
1205 * uses the i40e_aqc_add_oveb_cloud,
1206 * and the generic direct completion structure
1207 */
1208struct i40e_aqc_add_remove_control_packet_filter {
1209	u8	mac[6];
1210	__le16	etype;
1211	__le16	flags;
1212#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC	0x0001
1213#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP		0x0002
1214#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE	0x0004
1215#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX		0x0008
1216#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX		0x0000
1217	__le16	seid;
1218#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT	0
1219#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK	(0x3FF << \
1220				I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1221	__le16	queue;
1222	u8	reserved[2];
1223};
1224
1225I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1226
1227struct i40e_aqc_add_remove_control_packet_filter_completion {
1228	__le16	mac_etype_used;
1229	__le16	etype_used;
1230	__le16	mac_etype_free;
1231	__le16	etype_free;
1232	u8	reserved[8];
1233};
1234
1235I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1236
1237/* Add Cloud filters (indirect 0x025C)
1238 * Remove Cloud filters (indirect 0x025D)
1239 * uses the i40e_aqc_add_remove_cloud_filters,
1240 * and the generic indirect completion structure
1241 */
1242struct i40e_aqc_add_remove_cloud_filters {
1243	u8	num_filters;
1244	u8	reserved;
1245	__le16	seid;
1246#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0
1247#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \
1248					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1249	u8	reserved2[4];
1250	__le32	addr_high;
1251	__le32	addr_low;
1252};
1253
1254I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1255
1256struct i40e_aqc_add_remove_cloud_filters_element_data {
1257	u8	outer_mac[6];
1258	u8	inner_mac[6];
1259	__le16	inner_vlan;
1260	union {
1261		struct {
1262			u8 reserved[12];
1263			u8 data[4];
1264		} v4;
1265		struct {
1266			u8 data[16];
1267		} v6;
1268	} ipaddr;
1269	__le16	flags;
1270#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0
1271#define I40E_AQC_ADD_CLOUD_FILTER_MASK	(0x3F << \
1272					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1273/* 0x0000 reserved */
1274#define I40E_AQC_ADD_CLOUD_FILTER_OIP			0x0001
1275/* 0x0002 reserved */
1276#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN		0x0003
1277#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID	0x0004
1278/* 0x0005 reserved */
1279#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID		0x0006
1280/* 0x0007 reserved */
1281/* 0x0008 reserved */
1282#define I40E_AQC_ADD_CLOUD_FILTER_OMAC			0x0009
1283#define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A
1284#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B
1285#define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C
1286
1287#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080
1288#define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6
1289#define I40E_AQC_ADD_CLOUD_VNK_MASK			0x00C0
1290#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4			0
1291#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6			0x0100
1292
1293#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT		9
1294#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK		0x1E00
1295#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN		0
1296#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC		1
1297#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE		2
1298#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP			3
1299#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED		4
1300#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE		5
1301
1302#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC	0x2000
1303#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC	0x4000
1304#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP	0x8000
1305
1306	__le32	tenant_id;
1307	u8	reserved[4];
1308	__le16	queue_number;
1309#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT		0
1310#define I40E_AQC_ADD_CLOUD_QUEUE_MASK		(0x7FF << \
1311						 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1312	u8	reserved2[14];
1313	/* response section */
1314	u8	allocation_result;
1315#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS	0x0
1316#define I40E_AQC_ADD_CLOUD_FILTER_FAIL		0xFF
1317	u8	response_reserved[7];
1318};
1319
1320struct i40e_aqc_remove_cloud_filters_completion {
1321	__le16 perfect_ovlan_used;
1322	__le16 perfect_ovlan_free;
1323	__le16 vlan_used;
1324	__le16 vlan_free;
1325	__le32 addr_high;
1326	__le32 addr_low;
1327};
1328
1329I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1330
1331/* Add Mirror Rule (indirect or direct 0x0260)
1332 * Delete Mirror Rule (indirect or direct 0x0261)
1333 * note: some rule types (4,5) do not use an external buffer.
1334 *       take care to set the flags correctly.
1335 */
1336struct i40e_aqc_add_delete_mirror_rule {
1337	__le16 seid;
1338	__le16 rule_type;
1339#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT		0
1340#define I40E_AQC_MIRROR_RULE_TYPE_MASK		(0x7 << \
1341						I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1342#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS	1
1343#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS	2
1344#define I40E_AQC_MIRROR_RULE_TYPE_VLAN		3
1345#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS	4
1346#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS	5
1347	__le16 num_entries;
1348	__le16 destination;  /* VSI for add, rule id for delete */
1349	__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1350	__le32 addr_low;
1351};
1352
1353I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1354
1355struct i40e_aqc_add_delete_mirror_rule_completion {
1356	u8	reserved[2];
1357	__le16	rule_id;  /* only used on add */
1358	__le16	mirror_rules_used;
1359	__le16	mirror_rules_free;
1360	__le32	addr_high;
1361	__le32	addr_low;
1362};
1363
1364I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1365
1366/* DCB 0x03xx*/
1367
1368/* PFC Ignore (direct 0x0301)
1369 *    the command and response use the same descriptor structure
1370 */
1371struct i40e_aqc_pfc_ignore {
1372	u8	tc_bitmap;
1373	u8	command_flags; /* unused on response */
1374#define I40E_AQC_PFC_IGNORE_SET		0x80
1375#define I40E_AQC_PFC_IGNORE_CLEAR	0x0
1376	u8	reserved[14];
1377};
1378
1379I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1380
1381/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1382 * with no parameters
1383 */
1384
1385/* TX scheduler 0x04xx */
1386
1387/* Almost all the indirect commands use
1388 * this generic struct to pass the SEID in param0
1389 */
1390struct i40e_aqc_tx_sched_ind {
1391	__le16	vsi_seid;
1392	u8	reserved[6];
1393	__le32	addr_high;
1394	__le32	addr_low;
1395};
1396
1397I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1398
1399/* Several commands respond with a set of queue set handles */
1400struct i40e_aqc_qs_handles_resp {
1401	__le16 qs_handles[8];
1402};
1403
1404/* Configure VSI BW limits (direct 0x0400) */
1405struct i40e_aqc_configure_vsi_bw_limit {
1406	__le16	vsi_seid;
1407	u8	reserved[2];
1408	__le16	credit;
1409	u8	reserved1[2];
1410	u8	max_credit; /* 0-3, limit = 2^max */
1411	u8	reserved2[7];
1412};
1413
1414I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1415
1416/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1417 *    responds with i40e_aqc_qs_handles_resp
1418 */
1419struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1420	u8	tc_valid_bits;
1421	u8	reserved[15];
1422	__le16	tc_bw_credits[8]; /* FW writesback QS handles here */
1423
1424	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1425	__le16	tc_bw_max[2];
1426	u8	reserved1[28];
1427};
1428
1429I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1430
1431/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1432 *    responds with i40e_aqc_qs_handles_resp
1433 */
1434struct i40e_aqc_configure_vsi_tc_bw_data {
1435	u8	tc_valid_bits;
1436	u8	reserved[3];
1437	u8	tc_bw_credits[8];
1438	u8	reserved1[4];
1439	__le16	qs_handles[8];
1440};
1441
1442I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1443
1444/* Query vsi bw configuration (indirect 0x0408) */
1445struct i40e_aqc_query_vsi_bw_config_resp {
1446	u8	tc_valid_bits;
1447	u8	tc_suspended_bits;
1448	u8	reserved[14];
1449	__le16	qs_handles[8];
1450	u8	reserved1[4];
1451	__le16	port_bw_limit;
1452	u8	reserved2[2];
1453	u8	max_bw; /* 0-3, limit = 2^max */
1454	u8	reserved3[23];
1455};
1456
1457I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1458
1459/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1460struct i40e_aqc_query_vsi_ets_sla_config_resp {
1461	u8	tc_valid_bits;
1462	u8	reserved[3];
1463	u8	share_credits[8];
1464	__le16	credits[8];
1465
1466	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1467	__le16	tc_bw_max[2];
1468};
1469
1470I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1471
1472/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1473struct i40e_aqc_configure_switching_comp_bw_limit {
1474	__le16	seid;
1475	u8	reserved[2];
1476	__le16	credit;
1477	u8	reserved1[2];
1478	u8	max_bw; /* 0-3, limit = 2^max */
1479	u8	reserved2[7];
1480};
1481
1482I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1483
1484/* Enable  Physical Port ETS (indirect 0x0413)
1485 * Modify  Physical Port ETS (indirect 0x0414)
1486 * Disable Physical Port ETS (indirect 0x0415)
1487 */
1488struct i40e_aqc_configure_switching_comp_ets_data {
1489	u8	reserved[4];
1490	u8	tc_valid_bits;
1491	u8	seepage;
1492#define I40E_AQ_ETS_SEEPAGE_EN_MASK	0x1
1493	u8	tc_strict_priority_flags;
1494	u8	reserved1[17];
1495	u8	tc_bw_share_credits[8];
1496	u8	reserved2[96];
1497};
1498
1499I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1500
1501/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1502struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1503	u8	tc_valid_bits;
1504	u8	reserved[15];
1505	__le16	tc_bw_credit[8];
1506
1507	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1508	__le16	tc_bw_max[2];
1509	u8	reserved1[28];
1510};
1511
1512I40E_CHECK_STRUCT_LEN(0x40,
1513		      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1514
1515/* Configure Switching Component Bandwidth Allocation per Tc
1516 * (indirect 0x0417)
1517 */
1518struct i40e_aqc_configure_switching_comp_bw_config_data {
1519	u8	tc_valid_bits;
1520	u8	reserved[2];
1521	u8	absolute_credits; /* bool */
1522	u8	tc_bw_share_credits[8];
1523	u8	reserved1[20];
1524};
1525
1526I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1527
1528/* Query Switching Component Configuration (indirect 0x0418) */
1529struct i40e_aqc_query_switching_comp_ets_config_resp {
1530	u8	tc_valid_bits;
1531	u8	reserved[35];
1532	__le16	port_bw_limit;
1533	u8	reserved1[2];
1534	u8	tc_bw_max; /* 0-3, limit = 2^max */
1535	u8	reserved2[23];
1536};
1537
1538I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1539
1540/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1541struct i40e_aqc_query_port_ets_config_resp {
1542	u8	reserved[4];
1543	u8	tc_valid_bits;
1544	u8	reserved1;
1545	u8	tc_strict_priority_bits;
1546	u8	reserved2;
1547	u8	tc_bw_share_credits[8];
1548	__le16	tc_bw_limits[8];
1549
1550	/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1551	__le16	tc_bw_max[2];
1552	u8	reserved3[32];
1553};
1554
1555I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1556
1557/* Query Switching Component Bandwidth Allocation per Traffic Type
1558 * (indirect 0x041A)
1559 */
1560struct i40e_aqc_query_switching_comp_bw_config_resp {
1561	u8	tc_valid_bits;
1562	u8	reserved[2];
1563	u8	absolute_credits_enable; /* bool */
1564	u8	tc_bw_share_credits[8];
1565	__le16	tc_bw_limits[8];
1566
1567	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1568	__le16	tc_bw_max[2];
1569};
1570
1571I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1572
1573/* Suspend/resume port TX traffic
1574 * (direct 0x041B and 0x041C) uses the generic SEID struct
1575 */
1576
1577/* Configure partition BW
1578 * (indirect 0x041D)
1579 */
1580struct i40e_aqc_configure_partition_bw_data {
1581	__le16	pf_valid_bits;
1582	u8	min_bw[16];      /* guaranteed bandwidth */
1583	u8	max_bw[16];      /* bandwidth limit */
1584};
1585
1586I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1587
1588/* Get and set the active HMC resource profile and status.
1589 * (direct 0x0500) and (direct 0x0501)
1590 */
1591struct i40e_aq_get_set_hmc_resource_profile {
1592	u8	pm_profile;
1593	u8	pe_vf_enabled;
1594	u8	reserved[14];
1595};
1596
1597I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1598
1599enum i40e_aq_hmc_profile {
1600	/* I40E_HMC_PROFILE_NO_CHANGE    = 0, reserved */
1601	I40E_HMC_PROFILE_DEFAULT	= 1,
1602	I40E_HMC_PROFILE_FAVOR_VF	= 2,
1603	I40E_HMC_PROFILE_EQUAL		= 3,
1604};
1605
1606#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK	0xF
1607#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK	0x3F
1608
1609/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1610
1611/* set in param0 for get phy abilities to report qualified modules */
1612#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES	0x0001
1613#define I40E_AQ_PHY_REPORT_INITIAL_VALUES	0x0002
1614
1615enum i40e_aq_phy_type {
1616	I40E_PHY_TYPE_SGMII			= 0x0,
1617	I40E_PHY_TYPE_1000BASE_KX		= 0x1,
1618	I40E_PHY_TYPE_10GBASE_KX4		= 0x2,
1619	I40E_PHY_TYPE_10GBASE_KR		= 0x3,
1620	I40E_PHY_TYPE_40GBASE_KR4		= 0x4,
1621	I40E_PHY_TYPE_XAUI			= 0x5,
1622	I40E_PHY_TYPE_XFI			= 0x6,
1623	I40E_PHY_TYPE_SFI			= 0x7,
1624	I40E_PHY_TYPE_XLAUI			= 0x8,
1625	I40E_PHY_TYPE_XLPPI			= 0x9,
1626	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,
1627	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,
1628	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,
1629	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,
1630	I40E_PHY_TYPE_100BASE_TX		= 0x11,
1631	I40E_PHY_TYPE_1000BASE_T		= 0x12,
1632	I40E_PHY_TYPE_10GBASE_T			= 0x13,
1633	I40E_PHY_TYPE_10GBASE_SR		= 0x14,
1634	I40E_PHY_TYPE_10GBASE_LR		= 0x15,
1635	I40E_PHY_TYPE_10GBASE_SFPP_CU		= 0x16,
1636	I40E_PHY_TYPE_10GBASE_CR1		= 0x17,
1637	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,
1638	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,
1639	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,
1640	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,
1641	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
1642	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
1643	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
1644	I40E_PHY_TYPE_MAX
1645};
1646
1647#define I40E_LINK_SPEED_100MB_SHIFT	0x1
1648#define I40E_LINK_SPEED_1000MB_SHIFT	0x2
1649#define I40E_LINK_SPEED_10GB_SHIFT	0x3
1650#define I40E_LINK_SPEED_40GB_SHIFT	0x4
1651#define I40E_LINK_SPEED_20GB_SHIFT	0x5
1652
1653enum i40e_aq_link_speed {
1654	I40E_LINK_SPEED_UNKNOWN	= 0,
1655	I40E_LINK_SPEED_100MB	= (1 << I40E_LINK_SPEED_100MB_SHIFT),
1656	I40E_LINK_SPEED_1GB	= (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1657	I40E_LINK_SPEED_10GB	= (1 << I40E_LINK_SPEED_10GB_SHIFT),
1658	I40E_LINK_SPEED_40GB	= (1 << I40E_LINK_SPEED_40GB_SHIFT),
1659	I40E_LINK_SPEED_20GB	= (1 << I40E_LINK_SPEED_20GB_SHIFT)
1660};
1661
1662struct i40e_aqc_module_desc {
1663	u8 oui[3];
1664	u8 reserved1;
1665	u8 part_number[16];
1666	u8 revision[4];
1667	u8 reserved2[8];
1668};
1669
1670I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1671
1672struct i40e_aq_get_phy_abilities_resp {
1673	__le32	phy_type;       /* bitmap using the above enum for offsets */
1674	u8	link_speed;     /* bitmap using the above enum bit patterns */
1675	u8	abilities;
1676#define I40E_AQ_PHY_FLAG_PAUSE_TX	0x01
1677#define I40E_AQ_PHY_FLAG_PAUSE_RX	0x02
1678#define I40E_AQ_PHY_FLAG_LOW_POWER	0x04
1679#define I40E_AQ_PHY_LINK_ENABLED	0x08
1680#define I40E_AQ_PHY_AN_ENABLED		0x10
1681#define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20
1682	__le16	eee_capability;
1683#define I40E_AQ_EEE_100BASE_TX		0x0002
1684#define I40E_AQ_EEE_1000BASE_T		0x0004
1685#define I40E_AQ_EEE_10GBASE_T		0x0008
1686#define I40E_AQ_EEE_1000BASE_KX		0x0010
1687#define I40E_AQ_EEE_10GBASE_KX4		0x0020
1688#define I40E_AQ_EEE_10GBASE_KR		0x0040
1689	__le32	eeer_val;
1690	u8	d3_lpan;
1691#define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
1692	u8	reserved[3];
1693	u8	phy_id[4];
1694	u8	module_type[3];
1695	u8	qualified_module_count;
1696#define I40E_AQ_PHY_MAX_QMS		16
1697	struct i40e_aqc_module_desc	qualified_module[I40E_AQ_PHY_MAX_QMS];
1698};
1699
1700I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1701
1702/* Set PHY Config (direct 0x0601) */
1703struct i40e_aq_set_phy_config { /* same bits as above in all */
1704	__le32	phy_type;
1705	u8	link_speed;
1706	u8	abilities;
1707/* bits 0-2 use the values from get_phy_abilities_resp */
1708#define I40E_AQ_PHY_ENABLE_LINK		0x08
1709#define I40E_AQ_PHY_ENABLE_AN		0x10
1710#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK	0x20
1711	__le16	eee_capability;
1712	__le32	eeer;
1713	u8	low_power_ctrl;
1714	u8	reserved[3];
1715};
1716
1717I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1718
1719/* Set MAC Config command data structure (direct 0x0603) */
1720struct i40e_aq_set_mac_config {
1721	__le16	max_frame_size;
1722	u8	params;
1723#define I40E_AQ_SET_MAC_CONFIG_CRC_EN		0x04
1724#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK	0x78
1725#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT	3
1726#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE	0x0
1727#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX	0xF
1728#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX	0x9
1729#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX	0x8
1730#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX	0x7
1731#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX	0x6
1732#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX	0x5
1733#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX	0x4
1734#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX	0x3
1735#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX	0x2
1736#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX	0x1
1737	u8	tx_timer_priority; /* bitmap */
1738	__le16	tx_timer_value;
1739	__le16	fc_refresh_threshold;
1740	u8	reserved[8];
1741};
1742
1743I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1744
1745/* Restart Auto-Negotiation (direct 0x605) */
1746struct i40e_aqc_set_link_restart_an {
1747	u8	command;
1748#define I40E_AQ_PHY_RESTART_AN	0x02
1749#define I40E_AQ_PHY_LINK_ENABLE	0x04
1750	u8	reserved[15];
1751};
1752
1753I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1754
1755/* Get Link Status cmd & response data structure (direct 0x0607) */
1756struct i40e_aqc_get_link_status {
1757	__le16	command_flags; /* only field set on command */
1758#define I40E_AQ_LSE_MASK		0x3
1759#define I40E_AQ_LSE_NOP			0x0
1760#define I40E_AQ_LSE_DISABLE		0x2
1761#define I40E_AQ_LSE_ENABLE		0x3
1762/* only response uses this flag */
1763#define I40E_AQ_LSE_IS_ENABLED		0x1
1764	u8	phy_type;    /* i40e_aq_phy_type   */
1765	u8	link_speed;  /* i40e_aq_link_speed */
1766	u8	link_info;
1767#define I40E_AQ_LINK_UP			0x01    /* obsolete */
1768#define I40E_AQ_LINK_UP_FUNCTION	0x01
1769#define I40E_AQ_LINK_FAULT		0x02
1770#define I40E_AQ_LINK_FAULT_TX		0x04
1771#define I40E_AQ_LINK_FAULT_RX		0x08
1772#define I40E_AQ_LINK_FAULT_REMOTE	0x10
1773#define I40E_AQ_LINK_UP_PORT		0x20
1774#define I40E_AQ_MEDIA_AVAILABLE		0x40
1775#define I40E_AQ_SIGNAL_DETECT		0x80
1776	u8	an_info;
1777#define I40E_AQ_AN_COMPLETED		0x01
1778#define I40E_AQ_LP_AN_ABILITY		0x02
1779#define I40E_AQ_PD_FAULT		0x04
1780#define I40E_AQ_FEC_EN			0x08
1781#define I40E_AQ_PHY_LOW_POWER		0x10
1782#define I40E_AQ_LINK_PAUSE_TX		0x20
1783#define I40E_AQ_LINK_PAUSE_RX		0x40
1784#define I40E_AQ_QUALIFIED_MODULE	0x80
1785	u8	ext_info;
1786#define I40E_AQ_LINK_PHY_TEMP_ALARM	0x01
1787#define I40E_AQ_LINK_XCESSIVE_ERRORS	0x02
1788#define I40E_AQ_LINK_TX_SHIFT		0x02
1789#define I40E_AQ_LINK_TX_MASK		(0x03 << I40E_AQ_LINK_TX_SHIFT)
1790#define I40E_AQ_LINK_TX_ACTIVE		0x00
1791#define I40E_AQ_LINK_TX_DRAINED		0x01
1792#define I40E_AQ_LINK_TX_FLUSHED		0x03
1793#define I40E_AQ_LINK_FORCED_40G		0x10
1794	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
1795	__le16	max_frame_size;
1796	u8	config;
1797#define I40E_AQ_CONFIG_CRC_ENA		0x04
1798#define I40E_AQ_CONFIG_PACING_MASK	0x78
1799	u8	external_power_ability;
1800#define I40E_AQ_LINK_POWER_CLASS_1	0x00
1801#define I40E_AQ_LINK_POWER_CLASS_2	0x01
1802#define I40E_AQ_LINK_POWER_CLASS_3	0x02
1803#define I40E_AQ_LINK_POWER_CLASS_4	0x03
1804	u8	reserved[4];
1805};
1806
1807I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1808
1809/* Set event mask command (direct 0x613) */
1810struct i40e_aqc_set_phy_int_mask {
1811	u8	reserved[8];
1812	__le16	event_mask;
1813#define I40E_AQ_EVENT_LINK_UPDOWN	0x0002
1814#define I40E_AQ_EVENT_MEDIA_NA		0x0004
1815#define I40E_AQ_EVENT_LINK_FAULT	0x0008
1816#define I40E_AQ_EVENT_PHY_TEMP_ALARM	0x0010
1817#define I40E_AQ_EVENT_EXCESSIVE_ERRORS	0x0020
1818#define I40E_AQ_EVENT_SIGNAL_DETECT	0x0040
1819#define I40E_AQ_EVENT_AN_COMPLETED	0x0080
1820#define I40E_AQ_EVENT_MODULE_QUAL_FAIL	0x0100
1821#define I40E_AQ_EVENT_PORT_TX_SUSPENDED	0x0200
1822	u8	reserved1[6];
1823};
1824
1825I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1826
1827/* Get Local AN advt register (direct 0x0614)
1828 * Set Local AN advt register (direct 0x0615)
1829 * Get Link Partner AN advt register (direct 0x0616)
1830 */
1831struct i40e_aqc_an_advt_reg {
1832	__le32	local_an_reg0;
1833	__le16	local_an_reg1;
1834	u8	reserved[10];
1835};
1836
1837I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1838
1839/* Set Loopback mode (0x0618) */
1840struct i40e_aqc_set_lb_mode {
1841	__le16	lb_mode;
1842#define I40E_AQ_LB_PHY_LOCAL	0x01
1843#define I40E_AQ_LB_PHY_REMOTE	0x02
1844#define I40E_AQ_LB_MAC_LOCAL	0x04
1845	u8	reserved[14];
1846};
1847
1848I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1849
1850/* Set PHY Debug command (0x0622) */
1851struct i40e_aqc_set_phy_debug {
1852	u8	command_flags;
1853#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL	0x02
1854#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT	2
1855#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK	(0x03 << \
1856					I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1857#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE	0x00
1858#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD	0x01
1859#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT	0x02
1860#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10
1861	u8	reserved[15];
1862};
1863
1864I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1865
1866enum i40e_aq_phy_reg_type {
1867	I40E_AQC_PHY_REG_INTERNAL	= 0x1,
1868	I40E_AQC_PHY_REG_EXERNAL_BASET	= 0x2,
1869	I40E_AQC_PHY_REG_EXERNAL_MODULE	= 0x3
1870};
1871
1872/* Run PHY Activity (0x0626) */
1873struct i40e_aqc_run_phy_activity {
1874	__le16  activity_id;
1875	u8      flags;
1876	u8      reserved1;
1877	__le32  control;
1878	__le32  data;
1879	u8      reserved2[4];
1880};
1881
1882I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1883
1884/* NVM Read command (indirect 0x0701)
1885 * NVM Erase commands (direct 0x0702)
1886 * NVM Update commands (indirect 0x0703)
1887 */
1888struct i40e_aqc_nvm_update {
1889	u8	command_flags;
1890#define I40E_AQ_NVM_LAST_CMD	0x01
1891#define I40E_AQ_NVM_FLASH_ONLY	0x80
1892	u8	module_pointer;
1893	__le16	length;
1894	__le32	offset;
1895	__le32	addr_high;
1896	__le32	addr_low;
1897};
1898
1899I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1900
1901/* NVM Config Read (indirect 0x0704) */
1902struct i40e_aqc_nvm_config_read {
1903	__le16	cmd_flags;
1904#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK	1 
1905#define I40E_AQ_ANVM_READ_SINGLE_FEATURE		0 
1906#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES		1
1907	__le16	element_count;
1908	__le16	element_id;	/* Feature/field ID */
1909	__le16	element_id_msw;	/* MSWord of field ID */
1910	__le32	address_high;
1911	__le32	address_low;
1912};
1913
1914I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1915
1916/* NVM Config Write (indirect 0x0705) */
1917struct i40e_aqc_nvm_config_write {
1918	__le16	cmd_flags;
1919	__le16	element_count;
1920	u8	reserved[4];
1921	__le32	address_high;
1922	__le32	address_low;
1923};
1924
1925I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1926
1927/* Used for 0x0704 as well as for 0x0705 commands */
1928#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT		1
1929#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1930				(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1931#define I40E_AQ_ANVM_FEATURE		0
1932#define I40E_AQ_ANVM_IMMEDIATE_FIELD	(1 << FEATURE_OR_IMMEDIATE_SHIFT)
1933struct i40e_aqc_nvm_config_data_feature {
1934	__le16 feature_id;
1935#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY		0x01
1936#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP		0x08
1937#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR		0x10
1938	__le16 feature_options;
1939	__le16 feature_selection;
1940};
1941
1942I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1943
1944struct i40e_aqc_nvm_config_data_immediate_field {
1945	__le32 field_id;
1946	__le32 field_value;
1947	__le16 field_options;
1948	__le16 reserved;
1949};
1950
1951I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1952
1953/* OEM Post Update (indirect 0x0720)
1954 * no command data struct used
1955 */
1956struct i40e_aqc_nvm_oem_post_update {
1957#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA	0x01
1958	u8 sel_data;
1959	u8 reserved[7];
1960};
1961
1962I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1963
1964struct i40e_aqc_nvm_oem_post_update_buffer {
1965	u8 str_len;
1966	u8 dev_addr;
1967	__le16 eeprom_addr;
1968	u8 data[36];
1969};
1970
1971I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1972
1973/* Thermal Sensor (indirect 0x0721)
1974 *     read or set thermal sensor configs and values
1975 *     takes a sensor and command specific data buffer, not detailed here
1976 */
1977struct i40e_aqc_thermal_sensor {
1978	u8 sensor_action;
1979#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG	0
1980#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG	1
1981#define I40E_AQ_THERMAL_SENSOR_READ_TEMP	2
1982	u8 reserved[7];
1983	__le32	addr_high;
1984	__le32	addr_low;
1985};
1986
1987I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1988
1989/* Send to PF command (indirect 0x0801) id is only used by PF
1990 * Send to VF command (indirect 0x0802) id is only used by PF
1991 * Send to Peer PF command (indirect 0x0803)
1992 */
1993struct i40e_aqc_pf_vf_message {
1994	__le32	id;
1995	u8	reserved[4];
1996	__le32	addr_high;
1997	__le32	addr_low;
1998};
1999
2000I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2001
2002/* Alternate structure */
2003
2004/* Direct write (direct 0x0900)
2005 * Direct read (direct 0x0902)
2006 */
2007struct i40e_aqc_alternate_write {
2008	__le32 address0;
2009	__le32 data0;
2010	__le32 address1;
2011	__le32 data1;
2012};
2013
2014I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2015
2016/* Indirect write (indirect 0x0901)
2017 * Indirect read (indirect 0x0903)
2018 */
2019
2020struct i40e_aqc_alternate_ind_write {
2021	__le32 address;
2022	__le32 length;
2023	__le32 addr_high;
2024	__le32 addr_low;
2025};
2026
2027I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2028
2029/* Done alternate write (direct 0x0904)
2030 * uses i40e_aq_desc
2031 */
2032struct i40e_aqc_alternate_write_done {
2033	__le16	cmd_flags;
2034#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK	1
2035#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY	0
2036#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI	1
2037#define I40E_AQ_ALTERNATE_RESET_NEEDED		2
2038	u8	reserved[14];
2039};
2040
2041I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2042
2043/* Set OEM mode (direct 0x0905) */
2044struct i40e_aqc_alternate_set_mode {
2045	__le32	mode;
2046#define I40E_AQ_ALTERNATE_MODE_NONE	0
2047#define I40E_AQ_ALTERNATE_MODE_OEM	1
2048	u8	reserved[12];
2049};
2050
2051I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2052
2053/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2054
2055/* async events 0x10xx */
2056
2057/* Lan Queue Overflow Event (direct, 0x1001) */
2058struct i40e_aqc_lan_overflow {
2059	__le32	prtdcb_rupto;
2060	__le32	otx_ctl;
2061	u8	reserved[8];
2062};
2063
2064I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2065
2066/* Get LLDP MIB (indirect 0x0A00) */
2067struct i40e_aqc_lldp_get_mib {
2068	u8	type;
2069	u8	reserved1;
2070#define I40E_AQ_LLDP_MIB_TYPE_MASK		0x3
2071#define I40E_AQ_LLDP_MIB_LOCAL			0x0
2072#define I40E_AQ_LLDP_MIB_REMOTE			0x1
2073#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE	0x2
2074#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK		0xC
2075#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT		0x2
2076#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE	0x0
2077#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR	0x1
2078#define I40E_AQ_LLDP_TX_SHIFT			0x4
2079#define I40E_AQ_LLDP_TX_MASK			(0x03 << I40E_AQ_LLDP_TX_SHIFT)
2080/* TX pause flags use I40E_AQ_LINK_TX_* above */
2081	__le16	local_len;
2082	__le16	remote_len;
2083	u8	reserved2[2];
2084	__le32	addr_high;
2085	__le32	addr_low;
2086};
2087
2088I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2089
2090/* Configure LLDP MIB Change Event (direct 0x0A01)
2091 * also used for the event (with type in the command field)
2092 */
2093struct i40e_aqc_lldp_update_mib {
2094	u8	command;
2095#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE	0x0
2096#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE	0x1
2097	u8	reserved[7];
2098	__le32	addr_high;
2099	__le32	addr_low;
2100};
2101
2102I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2103
2104/* Add LLDP TLV (indirect 0x0A02)
2105 * Delete LLDP TLV (indirect 0x0A04)
2106 */
2107struct i40e_aqc_lldp_add_tlv {
2108	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2109	u8	reserved1[1];
2110	__le16	len;
2111	u8	reserved2[4];
2112	__le32	addr_high;
2113	__le32	addr_low;
2114};
2115
2116I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2117
2118/* Update LLDP TLV (indirect 0x0A03) */
2119struct i40e_aqc_lldp_update_tlv {
2120	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2121	u8	reserved;
2122	__le16	old_len;
2123	__le16	new_offset;
2124	__le16	new_len;
2125	__le32	addr_high;
2126	__le32	addr_low;
2127};
2128
2129I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2130
2131/* Stop LLDP (direct 0x0A05) */
2132struct i40e_aqc_lldp_stop {
2133	u8	command;
2134#define I40E_AQ_LLDP_AGENT_STOP		0x0
2135#define I40E_AQ_LLDP_AGENT_SHUTDOWN	0x1
2136	u8	reserved[15];
2137};
2138
2139I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2140
2141/* Start LLDP (direct 0x0A06) */
2142
2143struct i40e_aqc_lldp_start {
2144	u8	command;
2145#define I40E_AQ_LLDP_AGENT_START	0x1
2146	u8	reserved[15];
2147};
2148
2149I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2150
2151/* Get CEE DCBX Oper Config (0x0A07)
2152 * uses the generic descriptor struct
2153 * returns below as indirect response
2154 */
2155
2156#define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2157#define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2158#define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2159#define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2160#define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2161#define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2162
2163#define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2164#define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2165#define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2166#define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2167#define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2168#define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2169#define I40E_AQC_CEE_FCOE_STATUS_SHIFT	0x8
2170#define I40E_AQC_CEE_FCOE_STATUS_MASK	(0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2171#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT	0xB
2172#define I40E_AQC_CEE_ISCSI_STATUS_MASK	(0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2173#define I40E_AQC_CEE_FIP_STATUS_SHIFT	0x10
2174#define I40E_AQC_CEE_FIP_STATUS_MASK	(0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2175
2176/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2177 * word boundary layout issues, which the Linux compilers silently deal
2178 * with by adding padding, making the actual struct larger than designed.
2179 * However, the FW compiler for the NIC is less lenient and complains
2180 * about the struct.  Hence, the struct defined here has an extra byte in
2181 * fields reserved3 and reserved4 to directly acknowledge that padding,
2182 * and the new length is used in the length check macro.
2183 */
2184struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2185	u8	reserved1;
2186	u8	oper_num_tc;
2187	u8	oper_prio_tc[4];
2188	u8	reserved2;
2189	u8	oper_tc_bw[8];
2190	u8	oper_pfc_en;
2191	u8	reserved3[2];
2192	__le16	oper_app_prio;
2193	u8	reserved4[2];
2194	__le16	tlv_status;
2195};
2196
2197I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2198
2199struct i40e_aqc_get_cee_dcb_cfg_resp {
2200	u8	oper_num_tc;
2201	u8	oper_prio_tc[4];
2202	u8	oper_tc_bw[8];
2203	u8	oper_pfc_en;
2204	__le16	oper_app_prio;
2205#define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2206#define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2207#define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2208#define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2209#define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2210#define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2211#define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2212	__le32	tlv_status;
2213#define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2214#define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2215#define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2216#define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2217#define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2218#define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2219	u8	reserved[12];
2220};
2221
2222I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2223
2224/*	Set Local LLDP MIB (indirect 0x0A08)
2225 *	Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2226 */
2227struct i40e_aqc_lldp_set_local_mib {
2228#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT	0
2229#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK	(1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2230#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK	(1 << \
2231					SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2232#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB	0x0
2233#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT	(1)
2234#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK	(1 << \
2235				SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2236#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS		0x1
2237	u8	type;
2238	u8	reserved0;
2239	__le16	length;
2240	u8	reserved1[4];
2241	__le32	address_high;
2242	__le32	address_low;
2243};
2244
2245I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2246
2247/*	Stop/Start LLDP Agent (direct 0x0A09)
2248 *	Used for stopping/starting specific LLDP agent. e.g. DCBx
2249 */
2250struct i40e_aqc_lldp_stop_start_specific_agent {
2251#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT	0
2252#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2253				(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2254	u8	command;
2255	u8	reserved[15];
2256};
2257
2258I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2259
2260/* Add Udp Tunnel command and completion (direct 0x0B00) */
2261struct i40e_aqc_add_udp_tunnel {
2262	__le16	udp_port;
2263	u8	reserved0[3];
2264	u8	protocol_type;
2265#define I40E_AQC_TUNNEL_TYPE_VXLAN	0x00
2266#define I40E_AQC_TUNNEL_TYPE_NGE	0x01
2267#define I40E_AQC_TUNNEL_TYPE_TEREDO	0x10
2268#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE	0x11
2269	u8	reserved1[10];
2270};
2271
2272I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2273
2274struct i40e_aqc_add_udp_tunnel_completion {
2275	__le16	udp_port;
2276	u8	filter_entry_index;
2277	u8	multiple_pfs;
2278#define I40E_AQC_SINGLE_PF		0x0
2279#define I40E_AQC_MULTIPLE_PFS		0x1
2280	u8	total_filters;
2281	u8	reserved[11];
2282};
2283
2284I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2285
2286/* remove UDP Tunnel command (0x0B01) */
2287struct i40e_aqc_remove_udp_tunnel {
2288	u8	reserved[2];
2289	u8	index; /* 0 to 15 */
2290	u8	reserved2[13];
2291};
2292
2293I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2294
2295struct i40e_aqc_del_udp_tunnel_completion {
2296	__le16	udp_port;
2297	u8	index; /* 0 to 15 */
2298	u8	multiple_pfs;
2299	u8	total_filters_used;
2300	u8	reserved1[11];
2301};
2302
2303I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2304
2305struct i40e_aqc_get_set_rss_key {
2306#define I40E_AQC_SET_RSS_KEY_VSI_VALID		(0x1 << 15)
2307#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT	0
2308#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK	(0x3FF << \
2309					I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2310	__le16	vsi_id;
2311	u8	reserved[6];
2312	__le32	addr_high;
2313	__le32	addr_low;
2314};
2315
2316I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2317
2318struct i40e_aqc_get_set_rss_key_data {
2319	u8 standard_rss_key[0x28];
2320	u8 extended_hash_key[0xc];
2321};
2322
2323I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2324
2325struct  i40e_aqc_get_set_rss_lut {
2326#define I40E_AQC_SET_RSS_LUT_VSI_VALID		(0x1 << 15)
2327#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT	0
2328#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK	(0x3FF << \
2329					I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2330	__le16	vsi_id;
2331#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT	0
2332#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK	(0x1 << \
2333					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2334
2335#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI	0
2336#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF	1
2337	__le16	flags;
2338	u8	reserved[4];
2339	__le32	addr_high;
2340	__le32	addr_low;
2341};
2342
2343I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2344
2345/* tunnel key structure 0x0B10 */
2346
2347struct i40e_aqc_tunnel_key_structure {
2348	u8	key1_off;
2349	u8	key2_off;
2350	u8	key1_len;  /* 0 to 15 */
2351	u8	key2_len;  /* 0 to 15 */
2352	u8	flags;
2353#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE	0x01
2354/* response flags */
2355#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS	0x01
2356#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED	0x02
2357#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN	0x03
2358	u8	network_key_index;
2359#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN		0x0
2360#define I40E_AQC_NETWORK_KEY_INDEX_NGE			0x1
2361#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP	0x2
2362#define I40E_AQC_NETWORK_KEY_INDEX_GRE			0x3
2363	u8	reserved[10];
2364};
2365
2366I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2367
2368/* OEM mode commands (direct 0xFE0x) */
2369struct i40e_aqc_oem_param_change {
2370	__le32	param_type;
2371#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL	0
2372#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL	1
2373#define I40E_AQ_OEM_PARAM_MAC		2
2374	__le32	param_value1;
2375	__le16	param_value2;
2376	u8	reserved[6];
2377};
2378
2379I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2380
2381struct i40e_aqc_oem_state_change {
2382	__le32	state;
2383#define I40E_AQ_OEM_STATE_LINK_DOWN	0x0
2384#define I40E_AQ_OEM_STATE_LINK_UP	0x1
2385	u8	reserved[12];
2386};
2387
2388I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2389
2390/* Initialize OCSD (0xFE02, direct) */
2391struct i40e_aqc_opc_oem_ocsd_initialize {
2392	u8 type_status;
2393	u8 reserved1[3];
2394	__le32 ocsd_memory_block_addr_high;
2395	__le32 ocsd_memory_block_addr_low;
2396	__le32 requested_update_interval;
2397};
2398
2399I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2400
2401/* Initialize OCBB  (0xFE03, direct) */
2402struct i40e_aqc_opc_oem_ocbb_initialize {
2403	u8 type_status;
2404	u8 reserved1[3];
2405	__le32 ocbb_memory_block_addr_high;
2406	__le32 ocbb_memory_block_addr_low;
2407	u8 reserved2[4];
2408};
2409
2410I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2411
2412/* debug commands */
2413
2414/* get device id (0xFF00) uses the generic structure */
2415
2416/* set test more (0xFF01, internal) */
2417
2418struct i40e_acq_set_test_mode {
2419	u8	mode;
2420#define I40E_AQ_TEST_PARTIAL	0
2421#define I40E_AQ_TEST_FULL	1
2422#define I40E_AQ_TEST_NVM	2
2423	u8	reserved[3];
2424	u8	command;
2425#define I40E_AQ_TEST_OPEN	0
2426#define I40E_AQ_TEST_CLOSE	1
2427#define I40E_AQ_TEST_INC	2
2428	u8	reserved2[3];
2429	__le32	address_high;
2430	__le32	address_low;
2431};
2432
2433I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2434
2435/* Debug Read Register command (0xFF03)
2436 * Debug Write Register command (0xFF04)
2437 */
2438struct i40e_aqc_debug_reg_read_write {
2439	__le32 reserved;
2440	__le32 address;
2441	__le32 value_high;
2442	__le32 value_low;
2443};
2444
2445I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2446
2447/* Scatter/gather Reg Read  (indirect 0xFF05)
2448 * Scatter/gather Reg Write (indirect 0xFF06)
2449 */
2450
2451/* i40e_aq_desc is used for the command */
2452struct i40e_aqc_debug_reg_sg_element_data {
2453	__le32 address;
2454	__le32 value;
2455};
2456
2457/* Debug Modify register (direct 0xFF07) */
2458struct i40e_aqc_debug_modify_reg {
2459	__le32 address;
2460	__le32 value;
2461	__le32 clear_mask;
2462	__le32 set_mask;
2463};
2464
2465I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2466
2467/* dump internal data (0xFF08, indirect) */
2468
2469#define I40E_AQ_CLUSTER_ID_AUX		0
2470#define I40E_AQ_CLUSTER_ID_SWITCH_FLU	1
2471#define I40E_AQ_CLUSTER_ID_TXSCHED	2
2472#define I40E_AQ_CLUSTER_ID_HMC		3
2473#define I40E_AQ_CLUSTER_ID_MAC0		4
2474#define I40E_AQ_CLUSTER_ID_MAC1		5
2475#define I40E_AQ_CLUSTER_ID_MAC2		6
2476#define I40E_AQ_CLUSTER_ID_MAC3		7
2477#define I40E_AQ_CLUSTER_ID_DCB		8
2478#define I40E_AQ_CLUSTER_ID_EMP_MEM	9
2479#define I40E_AQ_CLUSTER_ID_PKT_BUF	10
2480#define I40E_AQ_CLUSTER_ID_ALTRAM	11
2481
2482struct i40e_aqc_debug_dump_internals {
2483	u8	cluster_id;
2484	u8	table_id;
2485	__le16	data_size;
2486	__le32	idx;
2487	__le32	address_high;
2488	__le32	address_low;
2489};
2490
2491I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2492
2493struct i40e_aqc_debug_modify_internals {
2494	u8	cluster_id;
2495	u8	cluster_specific_params[7];
2496	__le32	address_high;
2497	__le32	address_low;
2498};
2499
2500I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2501
2502#endif /* _I40E_ADMINQ_CMD_H_ */