1/*
  2 * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
  3 *
  4 * Copyright (C) 2014-2015 Intel Corporation.
  5 *
  6 * This program is free software; you can redistribute it and/or modify it
  7 * under the terms and conditions of the GNU General Public License,
  8 * version 2, as published by the Free Software Foundation.
  9 *
 10 * This program is distributed in the hope it will be useful, but WITHOUT
 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13 * more details.
 14 */
 15
 16#ifndef __INTEL_TH_MSU_H__
 17#define __INTEL_TH_MSU_H__
 18
 19enum {
 20	REG_MSU_MSUPARAMS	= 0x0000,
 21	REG_MSU_MSUSTS		= 0x0008,
 22	REG_MSU_MSC0CTL		= 0x0100, /* MSC0 control */
 23	REG_MSU_MSC0STS		= 0x0104, /* MSC0 status */
 24	REG_MSU_MSC0BAR		= 0x0108, /* MSC0 output base address */
 25	REG_MSU_MSC0SIZE	= 0x010c, /* MSC0 output size */
 26	REG_MSU_MSC0MWP		= 0x0110, /* MSC0 write pointer */
 27	REG_MSU_MSC0NWSA	= 0x011c, /* MSC0 next window start address */
 28
 29	REG_MSU_MSC1CTL		= 0x0200, /* MSC1 control */
 30	REG_MSU_MSC1STS		= 0x0204, /* MSC1 status */
 31	REG_MSU_MSC1BAR		= 0x0208, /* MSC1 output base address */
 32	REG_MSU_MSC1SIZE	= 0x020c, /* MSC1 output size */
 33	REG_MSU_MSC1MWP		= 0x0210, /* MSC1 write pointer */
 34	REG_MSU_MSC1NWSA	= 0x021c, /* MSC1 next window start address */
 35};
 36
 37/* MSUSTS bits */
 38#define MSUSTS_MSU_INT	BIT(0)
 39
 40/* MSCnCTL bits */
 41#define MSC_EN		BIT(0)
 42#define MSC_WRAPEN	BIT(1)
 43#define MSC_RD_HDR_OVRD	BIT(2)
 44#define MSC_MODE	(BIT(4) | BIT(5))
 45#define MSC_LEN		(BIT(8) | BIT(9) | BIT(10))
 46
 47/* MSC operating modes (MSC_MODE) */
 48enum {
 49	MSC_MODE_SINGLE	= 0,
 50	MSC_MODE_MULTI,
 51	MSC_MODE_EXI,
 52	MSC_MODE_DEBUG,
 53};
 54
 55/* MSCnSTS bits */
 56#define MSCSTS_WRAPSTAT	BIT(1)	/* Wrap occurred */
 57#define MSCSTS_PLE	BIT(2)	/* Pipeline Empty */
 58
 59/*
 60 * Multiblock/multiwindow block descriptor
 61 */
 62struct msc_block_desc {
 63	u32	sw_tag;
 64	u32	block_sz;
 65	u32	next_blk;
 66	u32	next_win;
 67	u32	res0[4];
 68	u32	hw_tag;
 69	u32	valid_dw;
 70	u32	ts_low;
 71	u32	ts_high;
 72	u32	res1[4];
 73} __packed;
 74
 75#define MSC_BDESC	sizeof(struct msc_block_desc)
 76#define DATA_IN_PAGE	(PAGE_SIZE - MSC_BDESC)
 77
 78/* MSC multiblock sw tag bits */
 79#define MSC_SW_TAG_LASTBLK	BIT(0)
 80#define MSC_SW_TAG_LASTWIN	BIT(1)
 81
 82/* MSC multiblock hw tag bits */
 83#define MSC_HW_TAG_TRIGGER	BIT(0)
 84#define MSC_HW_TAG_BLOCKWRAP	BIT(1)
 85#define MSC_HW_TAG_WINWRAP	BIT(2)
 86#define MSC_HW_TAG_ENDBIT	BIT(3)
 87
 88static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
 89{
 90	if (!bdesc->valid_dw)
 91		return 0;
 92
 93	return bdesc->valid_dw * 4 - MSC_BDESC;
 94}
 95
 96static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
 97{
 98	if (bdesc->hw_tag & MSC_HW_TAG_BLOCKWRAP)
 99		return true;
100
101	return false;
102}
103
104static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
105{
106	if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
107	    (msc_data_sz(bdesc) != DATA_IN_PAGE))
108		return true;
109
110	return false;
111}
112
113/* waiting for Pipeline Empty bit(s) to assert for MSC */
114#define MSC_PLE_WAITLOOP_DEPTH	10000
115
116#endif /* __INTEL_TH_MSU_H__ */