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1/*
2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/iopoll.h>
12#include <linux/math64.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/regmap.h>
16#include <linux/mfd/syscon.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_mipi_dsi.h>
21#include <drm/drm_of.h>
22#include <drm/drm_panel.h>
23#include <drm/drmP.h>
24#include <video/mipi_display.h>
25
26#include "rockchip_drm_drv.h"
27#include "rockchip_drm_vop.h"
28
29#define DRIVER_NAME "dw-mipi-dsi"
30
31#define GRF_SOC_CON6 0x025c
32#define DSI0_SEL_VOP_LIT (1 << 6)
33#define DSI1_SEL_VOP_LIT (1 << 9)
34
35#define DSI_VERSION 0x00
36#define DSI_PWR_UP 0x04
37#define RESET 0
38#define POWERUP BIT(0)
39
40#define DSI_CLKMGR_CFG 0x08
41#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
42#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
43
44#define DSI_DPI_VCID 0x0c
45#define DPI_VID(vid) (((vid) & 0x3) << 0)
46
47#define DSI_DPI_COLOR_CODING 0x10
48#define EN18_LOOSELY BIT(8)
49#define DPI_COLOR_CODING_16BIT_1 0x0
50#define DPI_COLOR_CODING_16BIT_2 0x1
51#define DPI_COLOR_CODING_16BIT_3 0x2
52#define DPI_COLOR_CODING_18BIT_1 0x3
53#define DPI_COLOR_CODING_18BIT_2 0x4
54#define DPI_COLOR_CODING_24BIT 0x5
55
56#define DSI_DPI_CFG_POL 0x14
57#define COLORM_ACTIVE_LOW BIT(4)
58#define SHUTD_ACTIVE_LOW BIT(3)
59#define HSYNC_ACTIVE_LOW BIT(2)
60#define VSYNC_ACTIVE_LOW BIT(1)
61#define DATAEN_ACTIVE_LOW BIT(0)
62
63#define DSI_DPI_LP_CMD_TIM 0x18
64#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
65#define INVACT_LPCMD_TIME(p) ((p) & 0xff)
66
67#define DSI_DBI_CFG 0x20
68#define DSI_DBI_CMDSIZE 0x28
69
70#define DSI_PCKHDL_CFG 0x2c
71#define EN_CRC_RX BIT(4)
72#define EN_ECC_RX BIT(3)
73#define EN_BTA BIT(2)
74#define EN_EOTP_RX BIT(1)
75#define EN_EOTP_TX BIT(0)
76
77#define DSI_MODE_CFG 0x34
78#define ENABLE_VIDEO_MODE 0
79#define ENABLE_CMD_MODE BIT(0)
80
81#define DSI_VID_MODE_CFG 0x38
82#define FRAME_BTA_ACK BIT(14)
83#define ENABLE_LOW_POWER (0x3f << 8)
84#define ENABLE_LOW_POWER_MASK (0x3f << 8)
85#define VID_MODE_TYPE_BURST_SYNC_PULSES 0x2
86#define VID_MODE_TYPE_MASK 0x3
87
88#define DSI_VID_PKT_SIZE 0x3c
89#define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
90#define VID_PKT_MAX_SIZE 0x3fff
91
92#define DSI_VID_HSA_TIME 0x48
93#define DSI_VID_HBP_TIME 0x4c
94#define DSI_VID_HLINE_TIME 0x50
95#define DSI_VID_VSA_LINES 0x54
96#define DSI_VID_VBP_LINES 0x58
97#define DSI_VID_VFP_LINES 0x5c
98#define DSI_VID_VACTIVE_LINES 0x60
99#define DSI_CMD_MODE_CFG 0x68
100#define MAX_RD_PKT_SIZE_LP BIT(24)
101#define DCS_LW_TX_LP BIT(19)
102#define DCS_SR_0P_TX_LP BIT(18)
103#define DCS_SW_1P_TX_LP BIT(17)
104#define DCS_SW_0P_TX_LP BIT(16)
105#define GEN_LW_TX_LP BIT(14)
106#define GEN_SR_2P_TX_LP BIT(13)
107#define GEN_SR_1P_TX_LP BIT(12)
108#define GEN_SR_0P_TX_LP BIT(11)
109#define GEN_SW_2P_TX_LP BIT(10)
110#define GEN_SW_1P_TX_LP BIT(9)
111#define GEN_SW_0P_TX_LP BIT(8)
112#define EN_ACK_RQST BIT(1)
113#define EN_TEAR_FX BIT(0)
114
115#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
116 DCS_LW_TX_LP | \
117 DCS_SR_0P_TX_LP | \
118 DCS_SW_1P_TX_LP | \
119 DCS_SW_0P_TX_LP | \
120 GEN_LW_TX_LP | \
121 GEN_SR_2P_TX_LP | \
122 GEN_SR_1P_TX_LP | \
123 GEN_SR_0P_TX_LP | \
124 GEN_SW_2P_TX_LP | \
125 GEN_SW_1P_TX_LP | \
126 GEN_SW_0P_TX_LP)
127
128#define DSI_GEN_HDR 0x6c
129#define GEN_HDATA(data) (((data) & 0xffff) << 8)
130#define GEN_HDATA_MASK (0xffff << 8)
131#define GEN_HTYPE(type) (((type) & 0xff) << 0)
132#define GEN_HTYPE_MASK 0xff
133
134#define DSI_GEN_PLD_DATA 0x70
135
136#define DSI_CMD_PKT_STATUS 0x74
137#define GEN_CMD_EMPTY BIT(0)
138#define GEN_CMD_FULL BIT(1)
139#define GEN_PLD_W_EMPTY BIT(2)
140#define GEN_PLD_W_FULL BIT(3)
141#define GEN_PLD_R_EMPTY BIT(4)
142#define GEN_PLD_R_FULL BIT(5)
143#define GEN_RD_CMD_BUSY BIT(6)
144
145#define DSI_TO_CNT_CFG 0x78
146#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
147#define LPRX_TO_CNT(p) ((p) & 0xffff)
148
149#define DSI_BTA_TO_CNT 0x8c
150
151#define DSI_LPCLK_CTRL 0x94
152#define AUTO_CLKLANE_CTRL BIT(1)
153#define PHY_TXREQUESTCLKHS BIT(0)
154
155#define DSI_PHY_TMR_LPCLK_CFG 0x98
156#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
157#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
158
159#define DSI_PHY_TMR_CFG 0x9c
160#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
161#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
162#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
163
164#define DSI_PHY_RSTZ 0xa0
165#define PHY_DISFORCEPLL 0
166#define PHY_ENFORCEPLL BIT(3)
167#define PHY_DISABLECLK 0
168#define PHY_ENABLECLK BIT(2)
169#define PHY_RSTZ 0
170#define PHY_UNRSTZ BIT(1)
171#define PHY_SHUTDOWNZ 0
172#define PHY_UNSHUTDOWNZ BIT(0)
173
174#define DSI_PHY_IF_CFG 0xa4
175#define N_LANES(n) ((((n) - 1) & 0x3) << 0)
176#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
177
178#define DSI_PHY_STATUS 0xb0
179#define LOCK BIT(0)
180#define STOP_STATE_CLK_LANE BIT(2)
181
182#define DSI_PHY_TST_CTRL0 0xb4
183#define PHY_TESTCLK BIT(1)
184#define PHY_UNTESTCLK 0
185#define PHY_TESTCLR BIT(0)
186#define PHY_UNTESTCLR 0
187
188#define DSI_PHY_TST_CTRL1 0xb8
189#define PHY_TESTEN BIT(16)
190#define PHY_UNTESTEN 0
191#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
192#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
193
194#define DSI_INT_ST0 0xbc
195#define DSI_INT_ST1 0xc0
196#define DSI_INT_MSK0 0xc4
197#define DSI_INT_MSK1 0xc8
198
199#define PHY_STATUS_TIMEOUT_US 10000
200#define CMD_PKT_STATUS_TIMEOUT_US 20000
201
202#define BYPASS_VCO_RANGE BIT(7)
203#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
204#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
205#define VCO_IN_CAP_CON_LOW (0x1 << 1)
206#define VCO_IN_CAP_CON_HIGH (0x2 << 1)
207#define REF_BIAS_CUR_SEL BIT(0)
208
209#define CP_CURRENT_3MA BIT(3)
210#define CP_PROGRAM_EN BIT(7)
211#define LPF_PROGRAM_EN BIT(6)
212#define LPF_RESISTORS_20_KOHM 0
213
214#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
215
216#define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
217#define LOW_PROGRAM_EN 0
218#define HIGH_PROGRAM_EN BIT(7)
219#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
220#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
221#define PLL_LOOP_DIV_EN BIT(5)
222#define PLL_INPUT_DIV_EN BIT(4)
223
224#define POWER_CONTROL BIT(6)
225#define INTERNAL_REG_CURRENT BIT(3)
226#define BIAS_BLOCK_ON BIT(2)
227#define BANDGAP_ON BIT(0)
228
229#define TER_RESISTOR_HIGH BIT(7)
230#define TER_RESISTOR_LOW 0
231#define LEVEL_SHIFTERS_ON BIT(6)
232#define TER_CAL_DONE BIT(5)
233#define SETRD_MAX (0x7 << 2)
234#define POWER_MANAGE BIT(1)
235#define TER_RESISTORS_ON BIT(0)
236
237#define BIASEXTR_SEL(val) ((val) & 0x7)
238#define BANDGAP_SEL(val) ((val) & 0x7)
239#define TLP_PROGRAM_EN BIT(7)
240#define THS_PRE_PROGRAM_EN BIT(7)
241#define THS_ZERO_PROGRAM_EN BIT(6)
242
243enum {
244 BANDGAP_97_07,
245 BANDGAP_98_05,
246 BANDGAP_99_02,
247 BANDGAP_100_00,
248 BANDGAP_93_17,
249 BANDGAP_94_15,
250 BANDGAP_95_12,
251 BANDGAP_96_10,
252};
253
254enum {
255 BIASEXTR_87_1,
256 BIASEXTR_91_5,
257 BIASEXTR_95_9,
258 BIASEXTR_100,
259 BIASEXTR_105_94,
260 BIASEXTR_111_88,
261 BIASEXTR_118_8,
262 BIASEXTR_127_7,
263};
264
265struct dw_mipi_dsi_plat_data {
266 unsigned int max_data_lanes;
267 enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
268 struct drm_display_mode *mode);
269};
270
271struct dw_mipi_dsi {
272 struct drm_encoder encoder;
273 struct drm_connector connector;
274 struct mipi_dsi_host dsi_host;
275 struct drm_panel *panel;
276 struct device *dev;
277 struct regmap *grf_regmap;
278 void __iomem *base;
279
280 struct clk *pllref_clk;
281 struct clk *pclk;
282
283 unsigned int lane_mbps; /* per lane */
284 u32 channel;
285 u32 lanes;
286 u32 format;
287 u16 input_div;
288 u16 feedback_div;
289 struct drm_display_mode *mode;
290
291 const struct dw_mipi_dsi_plat_data *pdata;
292};
293
294enum dw_mipi_dsi_mode {
295 DW_MIPI_DSI_CMD_MODE,
296 DW_MIPI_DSI_VID_MODE,
297};
298
299struct dphy_pll_testdin_map {
300 unsigned int max_mbps;
301 u8 testdin;
302};
303
304/* The table is based on 27MHz DPHY pll reference clock. */
305static const struct dphy_pll_testdin_map dptdin_map[] = {
306 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
307 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
308 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
309 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
310 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
311 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
312 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
313 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
314 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
315 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
316};
317
318static int max_mbps_to_testdin(unsigned int max_mbps)
319{
320 int i;
321
322 for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
323 if (dptdin_map[i].max_mbps > max_mbps)
324 return dptdin_map[i].testdin;
325
326 return -EINVAL;
327}
328
329/*
330 * The controller should generate 2 frames before
331 * preparing the peripheral.
332 */
333static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
334{
335 int refresh, two_frames;
336
337 refresh = drm_mode_vrefresh(dsi->mode);
338 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
339 msleep(two_frames);
340}
341
342static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
343{
344 return container_of(host, struct dw_mipi_dsi, dsi_host);
345}
346
347static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
348{
349 return container_of(con, struct dw_mipi_dsi, connector);
350}
351
352static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
353{
354 return container_of(encoder, struct dw_mipi_dsi, encoder);
355}
356static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
357{
358 writel(val, dsi->base + reg);
359}
360
361static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
362{
363 return readl(dsi->base + reg);
364}
365
366static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
367 u8 test_data)
368{
369 /*
370 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
371 * is latched internally as the current test code. Test data is
372 * programmed internally by rising edge on TESTCLK.
373 */
374 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
375
376 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
377 PHY_TESTDIN(test_code));
378
379 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
380
381 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
382 PHY_TESTDIN(test_data));
383
384 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
385}
386
387static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
388{
389 int ret, testdin, vco, val;
390
391 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
392
393 testdin = max_mbps_to_testdin(dsi->lane_mbps);
394 if (testdin < 0) {
395 dev_err(dsi->dev,
396 "failed to get testdin for %dmbps lane clock\n",
397 dsi->lane_mbps);
398 return testdin;
399 }
400
401 dsi_write(dsi, DSI_PWR_UP, POWERUP);
402
403 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
404 VCO_RANGE_CON_SEL(vco) |
405 VCO_IN_CAP_CON_LOW |
406 REF_BIAS_CUR_SEL);
407
408 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
409 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
410 LPF_RESISTORS_20_KOHM);
411
412 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
413
414 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
415 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
416 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
417 LOW_PROGRAM_EN);
418 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
419 HIGH_PROGRAM_EN);
420
421 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
422 BIAS_BLOCK_ON | BANDGAP_ON);
423
424 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
425 SETRD_MAX | TER_RESISTORS_ON);
426 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
427 SETRD_MAX | POWER_MANAGE |
428 TER_RESISTORS_ON);
429
430 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
431 BIASEXTR_SEL(BIASEXTR_127_7));
432 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
433 BANDGAP_SEL(BANDGAP_96_10));
434
435 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
436 dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
437 dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
438
439 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
440 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
441
442
443 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
444 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
445 if (ret < 0) {
446 dev_err(dsi->dev, "failed to wait for phy lock state\n");
447 return ret;
448 }
449
450 ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
451 val, val & STOP_STATE_CLK_LANE, 1000,
452 PHY_STATUS_TIMEOUT_US);
453 if (ret < 0) {
454 dev_err(dsi->dev,
455 "failed to wait for phy clk lane stop state\n");
456 return ret;
457 }
458
459 return ret;
460}
461
462static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
463{
464 unsigned int i, pre;
465 unsigned long mpclk, pllref, tmp;
466 unsigned int m = 1, n = 1, target_mbps = 1000;
467 unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
468 int bpp;
469
470 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
471 if (bpp < 0) {
472 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
473 dsi->format);
474 return bpp;
475 }
476
477 mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
478 if (mpclk) {
479 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
480 tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
481 if (tmp < max_mbps)
482 target_mbps = tmp;
483 else
484 dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
485 }
486
487 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
488 tmp = pllref;
489
490 for (i = 1; i < 6; i++) {
491 pre = pllref / i;
492 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
493 tmp = target_mbps % pre;
494 n = i;
495 m = target_mbps / pre;
496 }
497 if (tmp == 0)
498 break;
499 }
500
501 dsi->lane_mbps = pllref / n * m;
502 dsi->input_div = n;
503 dsi->feedback_div = m;
504
505 return 0;
506}
507
508static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
509 struct mipi_dsi_device *device)
510{
511 struct dw_mipi_dsi *dsi = host_to_dsi(host);
512
513 if (device->lanes > dsi->pdata->max_data_lanes) {
514 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
515 device->lanes);
516 return -EINVAL;
517 }
518
519 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
520 !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
521 dev_err(dsi->dev, "device mode is unsupported\n");
522 return -EINVAL;
523 }
524
525 dsi->lanes = device->lanes;
526 dsi->channel = device->channel;
527 dsi->format = device->format;
528 dsi->panel = of_drm_find_panel(device->dev.of_node);
529 if (dsi->panel)
530 return drm_panel_attach(dsi->panel, &dsi->connector);
531
532 return -EINVAL;
533}
534
535static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
536 struct mipi_dsi_device *device)
537{
538 struct dw_mipi_dsi *dsi = host_to_dsi(host);
539
540 drm_panel_detach(dsi->panel);
541
542 return 0;
543}
544
545static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
546{
547 int ret;
548
549 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
550 val, !(val & GEN_CMD_FULL), 1000,
551 CMD_PKT_STATUS_TIMEOUT_US);
552 if (ret < 0) {
553 dev_err(dsi->dev, "failed to get available command FIFO\n");
554 return ret;
555 }
556
557 dsi_write(dsi, DSI_GEN_HDR, val);
558
559 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
560 val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
561 1000, CMD_PKT_STATUS_TIMEOUT_US);
562 if (ret < 0) {
563 dev_err(dsi->dev, "failed to write command FIFO\n");
564 return ret;
565 }
566
567 return 0;
568}
569
570static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
571 const struct mipi_dsi_msg *msg)
572{
573 const u16 *tx_buf = msg->tx_buf;
574 u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
575
576 if (msg->tx_len > 2) {
577 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
578 msg->tx_len);
579 return -EINVAL;
580 }
581
582 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
583}
584
585static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
586 const struct mipi_dsi_msg *msg)
587{
588 const u32 *tx_buf = msg->tx_buf;
589 int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
590 u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
591 u32 remainder = 0;
592
593 if (msg->tx_len < 3) {
594 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
595 msg->tx_len);
596 return -EINVAL;
597 }
598
599 while (DIV_ROUND_UP(len, pld_data_bytes)) {
600 if (len < pld_data_bytes) {
601 memcpy(&remainder, tx_buf, len);
602 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
603 len = 0;
604 } else {
605 dsi_write(dsi, DSI_GEN_PLD_DATA, *tx_buf);
606 tx_buf++;
607 len -= pld_data_bytes;
608 }
609
610 ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
611 val, !(val & GEN_PLD_W_FULL), 1000,
612 CMD_PKT_STATUS_TIMEOUT_US);
613 if (ret < 0) {
614 dev_err(dsi->dev,
615 "failed to get available write payload FIFO\n");
616 return ret;
617 }
618 }
619
620 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
621}
622
623static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
624 const struct mipi_dsi_msg *msg)
625{
626 struct dw_mipi_dsi *dsi = host_to_dsi(host);
627 int ret;
628
629 switch (msg->type) {
630 case MIPI_DSI_DCS_SHORT_WRITE:
631 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
632 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
633 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
634 break;
635 case MIPI_DSI_DCS_LONG_WRITE:
636 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
637 break;
638 default:
639 dev_err(dsi->dev, "unsupported message type\n");
640 ret = -EINVAL;
641 }
642
643 return ret;
644}
645
646static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
647 .attach = dw_mipi_dsi_host_attach,
648 .detach = dw_mipi_dsi_host_detach,
649 .transfer = dw_mipi_dsi_host_transfer,
650};
651
652static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
653{
654 u32 val;
655
656 val = VID_MODE_TYPE_BURST_SYNC_PULSES | ENABLE_LOW_POWER;
657
658 dsi_write(dsi, DSI_VID_MODE_CFG, val);
659}
660
661static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
662 enum dw_mipi_dsi_mode mode)
663{
664 if (mode == DW_MIPI_DSI_CMD_MODE) {
665 dsi_write(dsi, DSI_PWR_UP, RESET);
666 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
667 dsi_write(dsi, DSI_PWR_UP, POWERUP);
668 } else {
669 dsi_write(dsi, DSI_PWR_UP, RESET);
670 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
671 dw_mipi_dsi_video_mode_config(dsi);
672 dsi_write(dsi, DSI_PWR_UP, POWERUP);
673 }
674}
675
676static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
677{
678 dsi_write(dsi, DSI_PWR_UP, RESET);
679 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
680}
681
682static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
683{
684 dsi_write(dsi, DSI_PWR_UP, RESET);
685 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
686 | PHY_RSTZ | PHY_SHUTDOWNZ);
687 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
688 TX_ESC_CLK_DIVIDSION(7));
689 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
690}
691
692static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
693 struct drm_display_mode *mode)
694{
695 u32 val = 0, color = 0;
696
697 switch (dsi->format) {
698 case MIPI_DSI_FMT_RGB888:
699 color = DPI_COLOR_CODING_24BIT;
700 break;
701 case MIPI_DSI_FMT_RGB666:
702 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
703 break;
704 case MIPI_DSI_FMT_RGB666_PACKED:
705 color = DPI_COLOR_CODING_18BIT_1;
706 break;
707 case MIPI_DSI_FMT_RGB565:
708 color = DPI_COLOR_CODING_16BIT_1;
709 break;
710 }
711
712 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
713 val |= VSYNC_ACTIVE_LOW;
714 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
715 val |= HSYNC_ACTIVE_LOW;
716
717 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
718 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
719 dsi_write(dsi, DSI_DPI_CFG_POL, val);
720 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
721 | INVACT_LPCMD_TIME(4));
722}
723
724static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
725{
726 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
727}
728
729static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
730 struct drm_display_mode *mode)
731{
732 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
733}
734
735static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
736{
737 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
738 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
739 dsi_write(dsi, DSI_CMD_MODE_CFG, CMD_MODE_ALL_LP);
740 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
741}
742
743/* Get lane byte clock cycles. */
744static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
745 u32 hcomponent)
746{
747 u32 frac, lbcc;
748
749 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
750
751 frac = lbcc % dsi->mode->clock;
752 lbcc = lbcc / dsi->mode->clock;
753 if (frac)
754 lbcc++;
755
756 return lbcc;
757}
758
759static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
760{
761 u32 htotal, hsa, hbp, lbcc;
762 struct drm_display_mode *mode = dsi->mode;
763
764 htotal = mode->htotal;
765 hsa = mode->hsync_end - mode->hsync_start;
766 hbp = mode->htotal - mode->hsync_end;
767
768 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, htotal);
769 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
770
771 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hsa);
772 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
773
774 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, hbp);
775 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
776}
777
778static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
779{
780 u32 vactive, vsa, vfp, vbp;
781 struct drm_display_mode *mode = dsi->mode;
782
783 vactive = mode->vdisplay;
784 vsa = mode->vsync_end - mode->vsync_start;
785 vfp = mode->vsync_start - mode->vdisplay;
786 vbp = mode->vtotal - mode->vsync_end;
787
788 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
789 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
790 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
791 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
792}
793
794static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
795{
796 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
797 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
798
799 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
800 | PHY_CLKLP2HS_TIME(0x40));
801}
802
803static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
804{
805 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
806 N_LANES(dsi->lanes));
807}
808
809static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
810{
811 dsi_read(dsi, DSI_INT_ST0);
812 dsi_read(dsi, DSI_INT_ST1);
813 dsi_write(dsi, DSI_INT_MSK0, 0);
814 dsi_write(dsi, DSI_INT_MSK1, 0);
815}
816
817static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
818 struct drm_display_mode *mode,
819 struct drm_display_mode *adjusted_mode)
820{
821 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
822 int ret;
823
824 dsi->mode = adjusted_mode;
825
826 ret = dw_mipi_dsi_get_lane_bps(dsi);
827 if (ret < 0)
828 return;
829
830 if (clk_prepare_enable(dsi->pclk)) {
831 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
832 return;
833 }
834
835 dw_mipi_dsi_init(dsi);
836 dw_mipi_dsi_dpi_config(dsi, mode);
837 dw_mipi_dsi_packet_handler_config(dsi);
838 dw_mipi_dsi_video_mode_config(dsi);
839 dw_mipi_dsi_video_packet_config(dsi, mode);
840 dw_mipi_dsi_command_mode_config(dsi);
841 dw_mipi_dsi_line_timer_config(dsi);
842 dw_mipi_dsi_vertical_timing_config(dsi);
843 dw_mipi_dsi_dphy_timing_config(dsi);
844 dw_mipi_dsi_dphy_interface_config(dsi);
845 dw_mipi_dsi_clear_err(dsi);
846 if (drm_panel_prepare(dsi->panel))
847 dev_err(dsi->dev, "failed to prepare panel\n");
848
849 clk_disable_unprepare(dsi->pclk);
850}
851
852static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
853{
854 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
855
856 drm_panel_disable(dsi->panel);
857
858 if (clk_prepare_enable(dsi->pclk)) {
859 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
860 return;
861 }
862
863 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
864 drm_panel_unprepare(dsi->panel);
865 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
866
867 /*
868 * This is necessary to make sure the peripheral will be driven
869 * normally when the display is enabled again later.
870 */
871 msleep(120);
872
873 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
874 dw_mipi_dsi_disable(dsi);
875 clk_disable_unprepare(dsi->pclk);
876}
877
878static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
879{
880 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
881 int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
882 u32 interface_pix_fmt;
883 u32 val;
884
885 if (clk_prepare_enable(dsi->pclk)) {
886 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
887 return;
888 }
889
890 dw_mipi_dsi_phy_init(dsi);
891 dw_mipi_dsi_wait_for_two_frames(dsi);
892
893 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
894 drm_panel_enable(dsi->panel);
895
896 clk_disable_unprepare(dsi->pclk);
897
898 switch (dsi->format) {
899 case MIPI_DSI_FMT_RGB888:
900 interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
901 break;
902 case MIPI_DSI_FMT_RGB666:
903 interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
904 break;
905 case MIPI_DSI_FMT_RGB565:
906 interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
907 break;
908 default:
909 WARN_ON(1);
910 return;
911 }
912
913 rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
914 interface_pix_fmt);
915
916 if (mux)
917 val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
918 else
919 val = DSI0_SEL_VOP_LIT << 16;
920
921 regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
922 dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
923}
924
925static struct drm_encoder_helper_funcs
926dw_mipi_dsi_encoder_helper_funcs = {
927 .commit = dw_mipi_dsi_encoder_commit,
928 .mode_set = dw_mipi_dsi_encoder_mode_set,
929 .disable = dw_mipi_dsi_encoder_disable,
930};
931
932static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
933 .destroy = drm_encoder_cleanup,
934};
935
936static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
937{
938 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
939
940 return drm_panel_get_modes(dsi->panel);
941}
942
943static enum drm_mode_status dw_mipi_dsi_mode_valid(
944 struct drm_connector *connector,
945 struct drm_display_mode *mode)
946{
947 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
948
949 enum drm_mode_status mode_status = MODE_OK;
950
951 if (dsi->pdata->mode_valid)
952 mode_status = dsi->pdata->mode_valid(connector, mode);
953
954 return mode_status;
955}
956
957static struct drm_encoder *dw_mipi_dsi_connector_best_encoder(
958 struct drm_connector *connector)
959{
960 struct dw_mipi_dsi *dsi = con_to_dsi(connector);
961
962 return &dsi->encoder;
963}
964
965static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
966 .get_modes = dw_mipi_dsi_connector_get_modes,
967 .mode_valid = dw_mipi_dsi_mode_valid,
968 .best_encoder = dw_mipi_dsi_connector_best_encoder,
969};
970
971static enum drm_connector_status
972dw_mipi_dsi_detect(struct drm_connector *connector, bool force)
973{
974 return connector_status_connected;
975}
976
977static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
978{
979 drm_connector_unregister(connector);
980 drm_connector_cleanup(connector);
981}
982
983static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
984 .dpms = drm_atomic_helper_connector_dpms,
985 .fill_modes = drm_helper_probe_single_connector_modes,
986 .detect = dw_mipi_dsi_detect,
987 .destroy = dw_mipi_dsi_drm_connector_destroy,
988 .reset = drm_atomic_helper_connector_reset,
989 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
990 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
991};
992
993static int dw_mipi_dsi_register(struct drm_device *drm,
994 struct dw_mipi_dsi *dsi)
995{
996 struct drm_encoder *encoder = &dsi->encoder;
997 struct drm_connector *connector = &dsi->connector;
998 struct device *dev = dsi->dev;
999 int ret;
1000
1001 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1002 dev->of_node);
1003 /*
1004 * If we failed to find the CRTC(s) which this encoder is
1005 * supposed to be connected to, it's because the CRTC has
1006 * not been registered yet. Defer probing, and hope that
1007 * the required CRTC is added later.
1008 */
1009 if (encoder->possible_crtcs == 0)
1010 return -EPROBE_DEFER;
1011
1012 drm_encoder_helper_add(&dsi->encoder,
1013 &dw_mipi_dsi_encoder_helper_funcs);
1014 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1015 DRM_MODE_ENCODER_DSI, NULL);
1016 if (ret) {
1017 dev_err(dev, "Failed to initialize encoder with drm\n");
1018 return ret;
1019 }
1020
1021 drm_connector_helper_add(connector,
1022 &dw_mipi_dsi_connector_helper_funcs);
1023
1024 drm_connector_init(drm, &dsi->connector,
1025 &dw_mipi_dsi_atomic_connector_funcs,
1026 DRM_MODE_CONNECTOR_DSI);
1027
1028 drm_mode_connector_attach_encoder(connector, encoder);
1029
1030 return 0;
1031}
1032
1033static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1034{
1035 struct device_node *np = dsi->dev->of_node;
1036
1037 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1038 if (IS_ERR(dsi->grf_regmap)) {
1039 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1040 return PTR_ERR(dsi->grf_regmap);
1041 }
1042
1043 return 0;
1044}
1045
1046static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
1047 struct drm_connector *connector,
1048 struct drm_display_mode *mode)
1049{
1050 /*
1051 * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
1052 * register is 11-bit.
1053 */
1054 if (mode->hdisplay > 0x7ff)
1055 return MODE_BAD_HVALUE;
1056
1057 /*
1058 * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
1059 * register is 11-bit.
1060 */
1061 if (mode->vdisplay > 0x7ff)
1062 return MODE_BAD_VVALUE;
1063
1064 return MODE_OK;
1065}
1066
1067static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1068 .max_data_lanes = 4,
1069 .mode_valid = rk3288_mipi_dsi_mode_valid,
1070};
1071
1072static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1073 {
1074 .compatible = "rockchip,rk3288-mipi-dsi",
1075 .data = &rk3288_mipi_dsi_drv_data,
1076 },
1077 { /* sentinel */ }
1078};
1079MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1080
1081static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1082 void *data)
1083{
1084 const struct of_device_id *of_id =
1085 of_match_device(dw_mipi_dsi_dt_ids, dev);
1086 const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1087 struct platform_device *pdev = to_platform_device(dev);
1088 struct drm_device *drm = data;
1089 struct dw_mipi_dsi *dsi;
1090 struct resource *res;
1091 int ret;
1092
1093 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1094 if (!dsi)
1095 return -ENOMEM;
1096
1097 dsi->dev = dev;
1098 dsi->pdata = pdata;
1099
1100 ret = rockchip_mipi_parse_dt(dsi);
1101 if (ret)
1102 return ret;
1103
1104 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105 if (!res)
1106 return -ENODEV;
1107
1108 dsi->base = devm_ioremap_resource(dev, res);
1109 if (IS_ERR(dsi->base))
1110 return PTR_ERR(dsi->base);
1111
1112 dsi->pllref_clk = devm_clk_get(dev, "ref");
1113 if (IS_ERR(dsi->pllref_clk)) {
1114 ret = PTR_ERR(dsi->pllref_clk);
1115 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1116 return ret;
1117 }
1118
1119 dsi->pclk = devm_clk_get(dev, "pclk");
1120 if (IS_ERR(dsi->pclk)) {
1121 ret = PTR_ERR(dsi->pclk);
1122 dev_err(dev, "Unable to get pclk: %d\n", ret);
1123 return ret;
1124 }
1125
1126 ret = clk_prepare_enable(dsi->pllref_clk);
1127 if (ret) {
1128 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1129 return ret;
1130 }
1131
1132 ret = dw_mipi_dsi_register(drm, dsi);
1133 if (ret) {
1134 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1135 goto err_pllref;
1136 }
1137
1138 dev_set_drvdata(dev, dsi);
1139
1140 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1141 dsi->dsi_host.dev = dev;
1142 return mipi_dsi_host_register(&dsi->dsi_host);
1143
1144err_pllref:
1145 clk_disable_unprepare(dsi->pllref_clk);
1146 return ret;
1147}
1148
1149static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1150 void *data)
1151{
1152 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1153
1154 mipi_dsi_host_unregister(&dsi->dsi_host);
1155 clk_disable_unprepare(dsi->pllref_clk);
1156}
1157
1158static const struct component_ops dw_mipi_dsi_ops = {
1159 .bind = dw_mipi_dsi_bind,
1160 .unbind = dw_mipi_dsi_unbind,
1161};
1162
1163static int dw_mipi_dsi_probe(struct platform_device *pdev)
1164{
1165 return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1166}
1167
1168static int dw_mipi_dsi_remove(struct platform_device *pdev)
1169{
1170 component_del(&pdev->dev, &dw_mipi_dsi_ops);
1171 return 0;
1172}
1173
1174static struct platform_driver dw_mipi_dsi_driver = {
1175 .probe = dw_mipi_dsi_probe,
1176 .remove = dw_mipi_dsi_remove,
1177 .driver = {
1178 .of_match_table = dw_mipi_dsi_dt_ids,
1179 .name = DRIVER_NAME,
1180 },
1181};
1182module_platform_driver(dw_mipi_dsi_driver);
1183
1184MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1185MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1186MODULE_LICENSE("GPL");
1187MODULE_ALIAS("platform:" DRIVER_NAME);