1/*
  2* Copyright (C) 2014 Texas Instruments Ltd
  3*
  4* This program is free software; you can redistribute it and/or modify it
  5* under the terms of the GNU General Public License version 2 as published by
  6* the Free Software Foundation.
  7*
  8* You should have received a copy of the GNU General Public License along with
  9* this program.  If not, see <http://www.gnu.org/licenses/>.
 10*/
 11
 12#include <linux/clk.h>
 13#include <linux/delay.h>
 14#include <linux/err.h>
 15#include <linux/io.h>
 16#include <linux/kernel.h>
 17#include <linux/platform_device.h>
 18#include <linux/sched.h>
 19
 20#include <video/omapdss.h>
 21
 22#include "dss.h"
 23#include "dss_features.h"
 24
 25struct dss_video_pll {
 26	struct dss_pll pll;
 27
 28	struct device *dev;
 29
 30	void __iomem *clkctrl_base;
 31};
 32
 33#define REG_MOD(reg, val, start, end) \
 34	writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
 35
 36static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
 37{
 38	REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
 39}
 40
 41static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
 42{
 43	REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
 44}
 45
 46static void dss_dpll_power_enable(struct dss_video_pll *vpll)
 47{
 48	REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
 49
 50	/*
 51	 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
 52	 * so we have to use fixed delay here.
 53	 */
 54	msleep(1);
 55}
 56
 57static void dss_dpll_power_disable(struct dss_video_pll *vpll)
 58{
 59	REG_MOD(vpll->clkctrl_base, 0, 31, 30);	/* PLL_POWER_OFF */
 60}
 61
 62static int dss_video_pll_enable(struct dss_pll *pll)
 63{
 64	struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
 65	int r;
 66
 67	r = dss_runtime_get();
 68	if (r)
 69		return r;
 70
 71	dss_ctrl_pll_enable(pll->id, true);
 72
 73	dss_dpll_enable_scp_clk(vpll);
 74
 75	r = dss_pll_wait_reset_done(pll);
 76	if (r)
 77		goto err_reset;
 78
 79	dss_dpll_power_enable(vpll);
 80
 81	return 0;
 82
 83err_reset:
 84	dss_dpll_disable_scp_clk(vpll);
 85	dss_ctrl_pll_enable(pll->id, false);
 86	dss_runtime_put();
 87
 88	return r;
 89}
 90
 91static void dss_video_pll_disable(struct dss_pll *pll)
 92{
 93	struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
 94
 95	dss_dpll_power_disable(vpll);
 96
 97	dss_dpll_disable_scp_clk(vpll);
 98
 99	dss_ctrl_pll_enable(pll->id, false);
100
101	dss_runtime_put();
102}
103
104static const struct dss_pll_ops dss_pll_ops = {
105	.enable = dss_video_pll_enable,
106	.disable = dss_video_pll_disable,
107	.set_config = dss_pll_write_config_type_a,
108};
109
110static const struct dss_pll_hw dss_dra7_video_pll_hw = {
111	.n_max = (1 << 8) - 1,
112	.m_max = (1 << 12) - 1,
113	.mX_max = (1 << 5) - 1,
114	.fint_min = 500000,
115	.fint_max = 2500000,
116	.clkdco_max = 1800000000,
117
118	.n_msb = 8,
119	.n_lsb = 1,
120	.m_msb = 20,
121	.m_lsb = 9,
122
123	.mX_msb[0] = 25,
124	.mX_lsb[0] = 21,
125	.mX_msb[1] = 30,
126	.mX_lsb[1] = 26,
127
128	.has_refsel = true,
129};
130
131struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
132	struct regulator *regulator)
133{
134	const char * const reg_name[] = { "pll1", "pll2" };
135	const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
136	const char * const clkin_name[] = { "video1_clk", "video2_clk" };
137
138	struct resource *res;
139	struct dss_video_pll *vpll;
140	void __iomem *pll_base, *clkctrl_base;
141	struct clk *clk;
142	struct dss_pll *pll;
143	int r;
144
145	/* PLL CONTROL */
146
147	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]);
148	if (!res) {
149		dev_err(&pdev->dev,
150			"missing platform resource data for pll%d\n", id);
151		return ERR_PTR(-ENODEV);
152	}
153
154	pll_base = devm_ioremap_resource(&pdev->dev, res);
155	if (IS_ERR(pll_base)) {
156		dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
157		return ERR_CAST(pll_base);
158	}
159
160	/* CLOCK CONTROL */
161
162	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
163		clkctrl_name[id]);
164	if (!res) {
165		dev_err(&pdev->dev,
166			"missing platform resource data for pll%d\n", id);
167		return ERR_PTR(-ENODEV);
168	}
169
170	clkctrl_base = devm_ioremap_resource(&pdev->dev, res);
171	if (IS_ERR(clkctrl_base)) {
172		dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
173		return ERR_CAST(clkctrl_base);
174	}
175
176	/* CLKIN */
177
178	clk = devm_clk_get(&pdev->dev, clkin_name[id]);
179	if (IS_ERR(clk)) {
180		DSSERR("can't get video pll clkin\n");
181		return ERR_CAST(clk);
182	}
183
184	vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
185	if (!vpll)
186		return ERR_PTR(-ENOMEM);
187
188	vpll->dev = &pdev->dev;
189	vpll->clkctrl_base = clkctrl_base;
190
191	pll = &vpll->pll;
192
193	pll->name = id == 0 ? "video0" : "video1";
194	pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
195	pll->clkin = clk;
196	pll->regulator = regulator;
197	pll->base = pll_base;
198	pll->hw = &dss_dra7_video_pll_hw;
199	pll->ops = &dss_pll_ops;
200
201	r = dss_pll_register(pll);
202	if (r)
203		return ERR_PTR(r);
204
205	return pll;
206}
207
208void dss_video_pll_uninit(struct dss_pll *pll)
209{
210	dss_pll_unregister(pll);
211}