1/*
  2 * linux/drivers/video/omap2/dss/dss.h
  3 *
  4 * Copyright (C) 2009 Nokia Corporation
  5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6 *
  7 * Some code and ideas taken from drivers/video/omap/ driver
  8 * by Imre Deak.
  9 *
 10 * This program is free software; you can redistribute it and/or modify it
 11 * under the terms of the GNU General Public License version 2 as published by
 12 * the Free Software Foundation.
 13 *
 14 * This program is distributed in the hope that it will be useful, but WITHOUT
 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 17 * more details.
 18 *
 19 * You should have received a copy of the GNU General Public License along with
 20 * this program.  If not, see <http://www.gnu.org/licenses/>.
 21 */
 22
 23#ifndef __OMAP2_DSS_H
 24#define __OMAP2_DSS_H
 25
 26#include <linux/interrupt.h>
 27
 28#include "omapdss.h"
 29
 30#ifdef pr_fmt
 31#undef pr_fmt
 32#endif
 33
 34#ifdef DSS_SUBSYS_NAME
 35#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
 36#else
 37#define pr_fmt(fmt) fmt
 38#endif
 39
 40#define DSSDBG(format, ...) \
 41	pr_debug(format, ## __VA_ARGS__)
 42
 43#ifdef DSS_SUBSYS_NAME
 44#define DSSERR(format, ...) \
 45	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
 46	## __VA_ARGS__)
 47#else
 48#define DSSERR(format, ...) \
 49	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
 50#endif
 51
 52#ifdef DSS_SUBSYS_NAME
 53#define DSSINFO(format, ...) \
 54	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
 55	## __VA_ARGS__)
 56#else
 57#define DSSINFO(format, ...) \
 58	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
 59#endif
 60
 61#ifdef DSS_SUBSYS_NAME
 62#define DSSWARN(format, ...) \
 63	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
 64	## __VA_ARGS__)
 65#else
 66#define DSSWARN(format, ...) \
 67	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
 68#endif
 69
 70/* OMAP TRM gives bitfields as start:end, where start is the higher bit
 71   number. For example 7:0 */
 72#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
 73#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
 74#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
 75#define FLD_MOD(orig, val, start, end) \
 76	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
 77
 78enum dss_io_pad_mode {
 79	DSS_IO_PAD_MODE_RESET,
 80	DSS_IO_PAD_MODE_RFBI,
 81	DSS_IO_PAD_MODE_BYPASS,
 82};
 83
 84enum dss_hdmi_venc_clk_source_select {
 85	DSS_VENC_TV_CLK = 0,
 86	DSS_HDMI_M_PCLK = 1,
 87};
 88
 89enum dss_dsi_content_type {
 90	DSS_DSI_CONTENT_DCS,
 91	DSS_DSI_CONTENT_GENERIC,
 92};
 93
 94enum dss_writeback_channel {
 95	DSS_WB_LCD1_MGR =	0,
 96	DSS_WB_LCD2_MGR =	1,
 97	DSS_WB_TV_MGR =		2,
 98	DSS_WB_OVL0 =		3,
 99	DSS_WB_OVL1 =		4,
100	DSS_WB_OVL2 =		5,
101	DSS_WB_OVL3 =		6,
102	DSS_WB_LCD3_MGR =	7,
103};
104
105enum dss_pll_id {
106	DSS_PLL_DSI1,
107	DSS_PLL_DSI2,
108	DSS_PLL_HDMI,
109	DSS_PLL_VIDEO1,
110	DSS_PLL_VIDEO2,
111};
112
113struct dss_pll;
114
115#define DSS_PLL_MAX_HSDIVS 4
116
117/*
118 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
119 * Type-B PLLs: clkout[0] refers to m2.
120 */
121struct dss_pll_clock_info {
122	/* rates that we get with dividers below */
123	unsigned long fint;
124	unsigned long clkdco;
125	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
126
127	/* dividers */
128	u16 n;
129	u16 m;
130	u32 mf;
131	u16 mX[DSS_PLL_MAX_HSDIVS];
132	u16 sd;
133};
134
135struct dss_pll_ops {
136	int (*enable)(struct dss_pll *pll);
137	void (*disable)(struct dss_pll *pll);
138	int (*set_config)(struct dss_pll *pll,
139		const struct dss_pll_clock_info *cinfo);
140};
141
142struct dss_pll_hw {
143	unsigned n_max;
144	unsigned m_min;
145	unsigned m_max;
146	unsigned mX_max;
147
148	unsigned long fint_min, fint_max;
149	unsigned long clkdco_min, clkdco_low, clkdco_max;
150
151	u8 n_msb, n_lsb;
152	u8 m_msb, m_lsb;
153	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
154
155	bool has_stopmode;
156	bool has_freqsel;
157	bool has_selfreqdco;
158	bool has_refsel;
159};
160
161struct dss_pll {
162	const char *name;
163	enum dss_pll_id id;
164
165	struct clk *clkin;
166	struct regulator *regulator;
167
168	void __iomem *base;
169
170	const struct dss_pll_hw *hw;
171
172	const struct dss_pll_ops *ops;
173
174	struct dss_pll_clock_info cinfo;
175};
176
177struct dispc_clock_info {
178	/* rates that we get with dividers below */
179	unsigned long lck;
180	unsigned long pck;
181
182	/* dividers */
183	u16 lck_div;
184	u16 pck_div;
185};
186
187struct dss_lcd_mgr_config {
188	enum dss_io_pad_mode io_pad_mode;
189
190	bool stallmode;
191	bool fifohandcheck;
192
193	struct dispc_clock_info clock_info;
194
195	int video_port_width;
196
197	int lcden_sig_polarity;
198};
199
200struct seq_file;
201struct platform_device;
202
203/* core */
204struct platform_device *dss_get_core_pdev(void);
205int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
206void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
207int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
208int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
209
210static inline bool dss_mgr_is_lcd(enum omap_channel id)
211{
212	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
213			id == OMAP_DSS_CHANNEL_LCD3)
214		return true;
215	else
216		return false;
217}
218
219/* DSS */
220int dss_init_platform_driver(void) __init;
221void dss_uninit_platform_driver(void);
222
223int dss_runtime_get(void);
224void dss_runtime_put(void);
225
226unsigned long dss_get_dispc_clk_rate(void);
227int dss_dpi_select_source(int port, enum omap_channel channel);
228void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
229enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
230const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
231void dss_dump_clocks(struct seq_file *s);
232
233/* DSS VIDEO PLL */
234struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
235	struct regulator *regulator);
236void dss_video_pll_uninit(struct dss_pll *pll);
237
238/* dss-of */
239struct device_node *dss_of_port_get_parent_device(struct device_node *port);
240u32 dss_of_port_get_port_number(struct device_node *port);
241
242#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
243void dss_debug_dump_clocks(struct seq_file *s);
244#endif
245
246void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
247void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
248	enum omap_channel channel);
249
250void dss_sdi_init(int datapairs);
251int dss_sdi_enable(void);
252void dss_sdi_disable(void);
253
254void dss_select_dsi_clk_source(int dsi_module,
255		enum omap_dss_clk_source clk_src);
256void dss_select_lcd_clk_source(enum omap_channel channel,
257		enum omap_dss_clk_source clk_src);
258enum omap_dss_clk_source dss_get_dispc_clk_source(void);
259enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
260enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
261
262void dss_set_venc_output(enum omap_dss_venc_type type);
263void dss_set_dac_pwrdn_bgz(bool enable);
264
265int dss_set_fck_rate(unsigned long rate);
266
267typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
268bool dss_div_calc(unsigned long pck, unsigned long fck_min,
269		dss_div_calc_func func, void *data);
270
271/* SDI */
272int sdi_init_platform_driver(void) __init;
273void sdi_uninit_platform_driver(void);
274
275#ifdef CONFIG_OMAP2_DSS_SDI
276int sdi_init_port(struct platform_device *pdev, struct device_node *port);
277void sdi_uninit_port(struct device_node *port);
278#else
279static inline int sdi_init_port(struct platform_device *pdev,
280		struct device_node *port)
281{
282	return 0;
283}
284static inline void sdi_uninit_port(struct device_node *port)
285{
286}
287#endif
288
289/* DSI */
290
291#ifdef CONFIG_OMAP2_DSS_DSI
292
293struct dentry;
294struct file_operations;
295
296int dsi_init_platform_driver(void) __init;
297void dsi_uninit_platform_driver(void);
298
299void dsi_dump_clocks(struct seq_file *s);
300
301void dsi_irq_handler(void);
302u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
303
304#else
305static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
306{
307	WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
308	     __func__);
309	return 0;
310}
311#endif
312
313/* DPI */
314int dpi_init_platform_driver(void) __init;
315void dpi_uninit_platform_driver(void);
316
317#ifdef CONFIG_OMAP2_DSS_DPI
318int dpi_init_port(struct platform_device *pdev, struct device_node *port);
319void dpi_uninit_port(struct device_node *port);
320#else
321static inline int dpi_init_port(struct platform_device *pdev,
322		struct device_node *port)
323{
324	return 0;
325}
326static inline void dpi_uninit_port(struct device_node *port)
327{
328}
329#endif
330
331/* DISPC */
332int dispc_init_platform_driver(void) __init;
333void dispc_uninit_platform_driver(void);
334void dispc_dump_clocks(struct seq_file *s);
335
336void dispc_enable_sidle(void);
337void dispc_disable_sidle(void);
338
339void dispc_lcd_enable_signal(bool enable);
340void dispc_pck_free_enable(bool enable);
341void dispc_enable_fifomerge(bool enable);
342void dispc_enable_gamma_table(bool enable);
343
344typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
345		unsigned long pck, void *data);
346bool dispc_div_calc(unsigned long dispc,
347		unsigned long pck_min, unsigned long pck_max,
348		dispc_div_calc_func func, void *data);
349
350bool dispc_mgr_timings_ok(enum omap_channel channel,
351		const struct omap_video_timings *timings);
352int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
353		struct dispc_clock_info *cinfo);
354
355
356void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
357void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
358		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
359		bool manual_update);
360
361void dispc_mgr_set_clock_div(enum omap_channel channel,
362		const struct dispc_clock_info *cinfo);
363int dispc_mgr_get_clock_div(enum omap_channel channel,
364		struct dispc_clock_info *cinfo);
365void dispc_set_tv_pclk(unsigned long pclk);
366
367u32 dispc_wb_get_framedone_irq(void);
368bool dispc_wb_go_busy(void);
369void dispc_wb_go(void);
370void dispc_wb_enable(bool enable);
371bool dispc_wb_is_enabled(void);
372void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
373int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
374		bool mem_to_mem, const struct omap_video_timings *timings);
375
376/* VENC */
377int venc_init_platform_driver(void) __init;
378void venc_uninit_platform_driver(void);
379
380/* HDMI */
381int hdmi4_init_platform_driver(void) __init;
382void hdmi4_uninit_platform_driver(void);
383
384int hdmi5_init_platform_driver(void) __init;
385void hdmi5_uninit_platform_driver(void);
386
387/* RFBI */
388int rfbi_init_platform_driver(void) __init;
389void rfbi_uninit_platform_driver(void);
390
391
392#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
393static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
394{
395	int b;
396	for (b = 0; b < 32; ++b) {
397		if (irqstatus & (1 << b))
398			irq_arr[b]++;
399	}
400}
401#endif
402
403/* PLL */
404typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
405		unsigned long clkdco, void *data);
406typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
407		void *data);
408
409int dss_pll_register(struct dss_pll *pll);
410void dss_pll_unregister(struct dss_pll *pll);
411struct dss_pll *dss_pll_find(const char *name);
412int dss_pll_enable(struct dss_pll *pll);
413void dss_pll_disable(struct dss_pll *pll);
414int dss_pll_set_config(struct dss_pll *pll,
415		const struct dss_pll_clock_info *cinfo);
416
417bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
418		unsigned long out_min, unsigned long out_max,
419		dss_hsdiv_calc_func func, void *data);
420bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
421		unsigned long pll_min, unsigned long pll_max,
422		dss_pll_calc_func func, void *data);
423int dss_pll_write_config_type_a(struct dss_pll *pll,
424		const struct dss_pll_clock_info *cinfo);
425int dss_pll_write_config_type_b(struct dss_pll *pll,
426		const struct dss_pll_clock_info *cinfo);
427int dss_pll_wait_reset_done(struct dss_pll *pll);
428
429#endif