1#ifndef A3XX_XML
   2#define A3XX_XML
   3
   4/* Autogenerated file, DO NOT EDIT manually!
   5
   6This file was generated by the rules-ng-ng headergen tool in this git repository:
   7http://github.com/freedreno/envytools/
   8git clone https://github.com/freedreno/envytools.git
   9
  10The rules-ng-ng source files this header was generated from are:
  11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
  13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)
  15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16166 bytes, from 2016-02-11 21:20:31)
  16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)
  17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 109916 bytes, from 2016-02-20 18:44:48)
  18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20Copyright (C) 2013-2016 by the following authors:
  21- Rob Clark <robdclark@gmail.com> (robclark)
  22- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
  23
  24Permission is hereby granted, free of charge, to any person obtaining
  25a copy of this software and associated documentation files (the
  26"Software"), to deal in the Software without restriction, including
  27without limitation the rights to use, copy, modify, merge, publish,
  28distribute, sublicense, and/or sell copies of the Software, and to
  29permit persons to whom the Software is furnished to do so, subject to
  30the following conditions:
  31
  32The above copyright notice and this permission notice (including the
  33next paragraph) shall be included in all copies or substantial
  34portions of the Software.
  35
  36THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  38MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  39IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  40LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  41OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  42WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43*/
  44
  45
  46enum a3xx_tile_mode {
  47	LINEAR = 0,
  48	TILE_32X32 = 2,
  49};
  50
  51enum a3xx_state_block_id {
  52	HLSQ_BLOCK_ID_TP_TEX = 2,
  53	HLSQ_BLOCK_ID_TP_MIPMAP = 3,
  54	HLSQ_BLOCK_ID_SP_VS = 4,
  55	HLSQ_BLOCK_ID_SP_FS = 6,
  56};
  57
  58enum a3xx_cache_opcode {
  59	INVALIDATE = 1,
  60};
  61
  62enum a3xx_vtx_fmt {
  63	VFMT_32_FLOAT = 0,
  64	VFMT_32_32_FLOAT = 1,
  65	VFMT_32_32_32_FLOAT = 2,
  66	VFMT_32_32_32_32_FLOAT = 3,
  67	VFMT_16_FLOAT = 4,
  68	VFMT_16_16_FLOAT = 5,
  69	VFMT_16_16_16_FLOAT = 6,
  70	VFMT_16_16_16_16_FLOAT = 7,
  71	VFMT_32_FIXED = 8,
  72	VFMT_32_32_FIXED = 9,
  73	VFMT_32_32_32_FIXED = 10,
  74	VFMT_32_32_32_32_FIXED = 11,
  75	VFMT_16_SINT = 16,
  76	VFMT_16_16_SINT = 17,
  77	VFMT_16_16_16_SINT = 18,
  78	VFMT_16_16_16_16_SINT = 19,
  79	VFMT_16_UINT = 20,
  80	VFMT_16_16_UINT = 21,
  81	VFMT_16_16_16_UINT = 22,
  82	VFMT_16_16_16_16_UINT = 23,
  83	VFMT_16_SNORM = 24,
  84	VFMT_16_16_SNORM = 25,
  85	VFMT_16_16_16_SNORM = 26,
  86	VFMT_16_16_16_16_SNORM = 27,
  87	VFMT_16_UNORM = 28,
  88	VFMT_16_16_UNORM = 29,
  89	VFMT_16_16_16_UNORM = 30,
  90	VFMT_16_16_16_16_UNORM = 31,
  91	VFMT_32_UINT = 32,
  92	VFMT_32_32_UINT = 33,
  93	VFMT_32_32_32_UINT = 34,
  94	VFMT_32_32_32_32_UINT = 35,
  95	VFMT_32_SINT = 36,
  96	VFMT_32_32_SINT = 37,
  97	VFMT_32_32_32_SINT = 38,
  98	VFMT_32_32_32_32_SINT = 39,
  99	VFMT_8_UINT = 40,
 100	VFMT_8_8_UINT = 41,
 101	VFMT_8_8_8_UINT = 42,
 102	VFMT_8_8_8_8_UINT = 43,
 103	VFMT_8_UNORM = 44,
 104	VFMT_8_8_UNORM = 45,
 105	VFMT_8_8_8_UNORM = 46,
 106	VFMT_8_8_8_8_UNORM = 47,
 107	VFMT_8_SINT = 48,
 108	VFMT_8_8_SINT = 49,
 109	VFMT_8_8_8_SINT = 50,
 110	VFMT_8_8_8_8_SINT = 51,
 111	VFMT_8_SNORM = 52,
 112	VFMT_8_8_SNORM = 53,
 113	VFMT_8_8_8_SNORM = 54,
 114	VFMT_8_8_8_8_SNORM = 55,
 115	VFMT_10_10_10_2_UINT = 56,
 116	VFMT_10_10_10_2_UNORM = 57,
 117	VFMT_10_10_10_2_SINT = 58,
 118	VFMT_10_10_10_2_SNORM = 59,
 119	VFMT_2_10_10_10_UINT = 60,
 120	VFMT_2_10_10_10_UNORM = 61,
 121	VFMT_2_10_10_10_SINT = 62,
 122	VFMT_2_10_10_10_SNORM = 63,
 123};
 124
 125enum a3xx_tex_fmt {
 126	TFMT_5_6_5_UNORM = 4,
 127	TFMT_5_5_5_1_UNORM = 5,
 128	TFMT_4_4_4_4_UNORM = 7,
 129	TFMT_Z16_UNORM = 9,
 130	TFMT_X8Z24_UNORM = 10,
 131	TFMT_Z32_FLOAT = 11,
 132	TFMT_NV12_UV_TILED = 17,
 133	TFMT_NV12_Y_TILED = 19,
 134	TFMT_NV12_UV = 21,
 135	TFMT_NV12_Y = 23,
 136	TFMT_I420_Y = 24,
 137	TFMT_I420_U = 26,
 138	TFMT_I420_V = 27,
 139	TFMT_ATC_RGB = 32,
 140	TFMT_ATC_RGBA_EXPLICIT = 33,
 141	TFMT_ETC1 = 34,
 142	TFMT_ATC_RGBA_INTERPOLATED = 35,
 143	TFMT_DXT1 = 36,
 144	TFMT_DXT3 = 37,
 145	TFMT_DXT5 = 38,
 146	TFMT_2_10_10_10_UNORM = 40,
 147	TFMT_10_10_10_2_UNORM = 41,
 148	TFMT_9_9_9_E5_FLOAT = 42,
 149	TFMT_11_11_10_FLOAT = 43,
 150	TFMT_A8_UNORM = 44,
 151	TFMT_L8_UNORM = 45,
 152	TFMT_L8_A8_UNORM = 47,
 153	TFMT_8_UNORM = 48,
 154	TFMT_8_8_UNORM = 49,
 155	TFMT_8_8_8_UNORM = 50,
 156	TFMT_8_8_8_8_UNORM = 51,
 157	TFMT_8_SNORM = 52,
 158	TFMT_8_8_SNORM = 53,
 159	TFMT_8_8_8_SNORM = 54,
 160	TFMT_8_8_8_8_SNORM = 55,
 161	TFMT_8_UINT = 56,
 162	TFMT_8_8_UINT = 57,
 163	TFMT_8_8_8_UINT = 58,
 164	TFMT_8_8_8_8_UINT = 59,
 165	TFMT_8_SINT = 60,
 166	TFMT_8_8_SINT = 61,
 167	TFMT_8_8_8_SINT = 62,
 168	TFMT_8_8_8_8_SINT = 63,
 169	TFMT_16_FLOAT = 64,
 170	TFMT_16_16_FLOAT = 65,
 171	TFMT_16_16_16_16_FLOAT = 67,
 172	TFMT_16_UINT = 68,
 173	TFMT_16_16_UINT = 69,
 174	TFMT_16_16_16_16_UINT = 71,
 175	TFMT_16_SINT = 72,
 176	TFMT_16_16_SINT = 73,
 177	TFMT_16_16_16_16_SINT = 75,
 178	TFMT_16_UNORM = 76,
 179	TFMT_16_16_UNORM = 77,
 180	TFMT_16_16_16_16_UNORM = 79,
 181	TFMT_16_SNORM = 80,
 182	TFMT_16_16_SNORM = 81,
 183	TFMT_16_16_16_16_SNORM = 83,
 184	TFMT_32_FLOAT = 84,
 185	TFMT_32_32_FLOAT = 85,
 186	TFMT_32_32_32_32_FLOAT = 87,
 187	TFMT_32_UINT = 88,
 188	TFMT_32_32_UINT = 89,
 189	TFMT_32_32_32_32_UINT = 91,
 190	TFMT_32_SINT = 92,
 191	TFMT_32_32_SINT = 93,
 192	TFMT_32_32_32_32_SINT = 95,
 193	TFMT_2_10_10_10_UINT = 96,
 194	TFMT_10_10_10_2_UINT = 97,
 195	TFMT_ETC2_RG11_SNORM = 112,
 196	TFMT_ETC2_RG11_UNORM = 113,
 197	TFMT_ETC2_R11_SNORM = 114,
 198	TFMT_ETC2_R11_UNORM = 115,
 199	TFMT_ETC2_RGBA8 = 116,
 200	TFMT_ETC2_RGB8A1 = 117,
 201	TFMT_ETC2_RGB8 = 118,
 202};
 203
 204enum a3xx_tex_fetchsize {
 205	TFETCH_DISABLE = 0,
 206	TFETCH_1_BYTE = 1,
 207	TFETCH_2_BYTE = 2,
 208	TFETCH_4_BYTE = 3,
 209	TFETCH_8_BYTE = 4,
 210	TFETCH_16_BYTE = 5,
 211};
 212
 213enum a3xx_color_fmt {
 214	RB_R5G6B5_UNORM = 0,
 215	RB_R5G5B5A1_UNORM = 1,
 216	RB_R4G4B4A4_UNORM = 3,
 217	RB_R8G8B8_UNORM = 4,
 218	RB_R8G8B8A8_UNORM = 8,
 219	RB_R8G8B8A8_SNORM = 9,
 220	RB_R8G8B8A8_UINT = 10,
 221	RB_R8G8B8A8_SINT = 11,
 222	RB_R8G8_UNORM = 12,
 223	RB_R8G8_SNORM = 13,
 224	RB_R8_UINT = 14,
 225	RB_R8_SINT = 15,
 226	RB_R10G10B10A2_UNORM = 16,
 227	RB_A2R10G10B10_UNORM = 17,
 228	RB_R10G10B10A2_UINT = 18,
 229	RB_A2R10G10B10_UINT = 19,
 230	RB_A8_UNORM = 20,
 231	RB_R8_UNORM = 21,
 232	RB_R16_FLOAT = 24,
 233	RB_R16G16_FLOAT = 25,
 234	RB_R16G16B16A16_FLOAT = 27,
 235	RB_R11G11B10_FLOAT = 28,
 236	RB_R16_SNORM = 32,
 237	RB_R16G16_SNORM = 33,
 238	RB_R16G16B16A16_SNORM = 35,
 239	RB_R16_UNORM = 36,
 240	RB_R16G16_UNORM = 37,
 241	RB_R16G16B16A16_UNORM = 39,
 242	RB_R16_SINT = 40,
 243	RB_R16G16_SINT = 41,
 244	RB_R16G16B16A16_SINT = 43,
 245	RB_R16_UINT = 44,
 246	RB_R16G16_UINT = 45,
 247	RB_R16G16B16A16_UINT = 47,
 248	RB_R32_FLOAT = 48,
 249	RB_R32G32_FLOAT = 49,
 250	RB_R32G32B32A32_FLOAT = 51,
 251	RB_R32_SINT = 52,
 252	RB_R32G32_SINT = 53,
 253	RB_R32G32B32A32_SINT = 55,
 254	RB_R32_UINT = 56,
 255	RB_R32G32_UINT = 57,
 256	RB_R32G32B32A32_UINT = 59,
 257};
 258
 259enum a3xx_cp_perfcounter_select {
 260	CP_ALWAYS_COUNT = 0,
 261	CP_AHB_PFPTRANS_WAIT = 3,
 262	CP_AHB_NRTTRANS_WAIT = 6,
 263	CP_CSF_NRT_READ_WAIT = 8,
 264	CP_CSF_I1_FIFO_FULL = 9,
 265	CP_CSF_I2_FIFO_FULL = 10,
 266	CP_CSF_ST_FIFO_FULL = 11,
 267	CP_RESERVED_12 = 12,
 268	CP_CSF_RING_ROQ_FULL = 13,
 269	CP_CSF_I1_ROQ_FULL = 14,
 270	CP_CSF_I2_ROQ_FULL = 15,
 271	CP_CSF_ST_ROQ_FULL = 16,
 272	CP_RESERVED_17 = 17,
 273	CP_MIU_TAG_MEM_FULL = 18,
 274	CP_MIU_NRT_WRITE_STALLED = 22,
 275	CP_MIU_NRT_READ_STALLED = 23,
 276	CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
 277	CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
 278	CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
 279	CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
 280	CP_ME_MICRO_RB_STARVED = 30,
 281	CP_AHB_RBBM_DWORD_SENT = 40,
 282	CP_ME_BUSY_CLOCKS = 41,
 283	CP_ME_WAIT_CONTEXT_AVAIL = 42,
 284	CP_PFP_TYPE0_PACKET = 43,
 285	CP_PFP_TYPE3_PACKET = 44,
 286	CP_CSF_RB_WPTR_NEQ_RPTR = 45,
 287	CP_CSF_I1_SIZE_NEQ_ZERO = 46,
 288	CP_CSF_I2_SIZE_NEQ_ZERO = 47,
 289	CP_CSF_RBI1I2_FETCHING = 48,
 290};
 291
 292enum a3xx_gras_tse_perfcounter_select {
 293	GRAS_TSEPERF_INPUT_PRIM = 0,
 294	GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
 295	GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
 296	GRAS_TSEPERF_CLIPPED_PRIM = 3,
 297	GRAS_TSEPERF_NEW_PRIM = 4,
 298	GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
 299	GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
 300	GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
 301	GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
 302	GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
 303	GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
 304	GRAS_TSEPERF_POST_CLIP_PRIM = 11,
 305	GRAS_TSEPERF_WORKING_CYCLES = 12,
 306	GRAS_TSEPERF_PC_STARVE = 13,
 307	GRAS_TSERASPERF_STALL = 14,
 308};
 309
 310enum a3xx_gras_ras_perfcounter_select {
 311	GRAS_RASPERF_16X16_TILES = 0,
 312	GRAS_RASPERF_8X8_TILES = 1,
 313	GRAS_RASPERF_4X4_TILES = 2,
 314	GRAS_RASPERF_WORKING_CYCLES = 3,
 315	GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
 316	GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
 317	GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
 318};
 319
 320enum a3xx_hlsq_perfcounter_select {
 321	HLSQ_PERF_SP_VS_CONSTANT = 0,
 322	HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
 323	HLSQ_PERF_SP_FS_CONSTANT = 2,
 324	HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
 325	HLSQ_PERF_TP_STATE = 4,
 326	HLSQ_PERF_QUADS = 5,
 327	HLSQ_PERF_PIXELS = 6,
 328	HLSQ_PERF_VERTICES = 7,
 329	HLSQ_PERF_FS8_THREADS = 8,
 330	HLSQ_PERF_FS16_THREADS = 9,
 331	HLSQ_PERF_FS32_THREADS = 10,
 332	HLSQ_PERF_VS8_THREADS = 11,
 333	HLSQ_PERF_VS16_THREADS = 12,
 334	HLSQ_PERF_SP_VS_DATA_BYTES = 13,
 335	HLSQ_PERF_SP_FS_DATA_BYTES = 14,
 336	HLSQ_PERF_ACTIVE_CYCLES = 15,
 337	HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
 338	HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
 339	HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
 340	HLSQ_PERF_STALL_CYCLES_UCHE = 19,
 341	HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
 342	HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
 343	HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
 344	HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
 345	HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
 346	HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
 347	HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
 348	HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
 349	HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
 350};
 351
 352enum a3xx_pc_perfcounter_select {
 353	PC_PCPERF_VISIBILITY_STREAMS = 0,
 354	PC_PCPERF_TOTAL_INSTANCES = 1,
 355	PC_PCPERF_PRIMITIVES_PC_VPC = 2,
 356	PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
 357	PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
 358	PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
 359	PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
 360	PC_PCPERF_VERTICES_TO_VFD = 7,
 361	PC_PCPERF_REUSED_VERTICES = 8,
 362	PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
 363	PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
 364	PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
 365	PC_PCPERF_CYCLES_IS_WORKING = 12,
 366};
 367
 368enum a3xx_rb_perfcounter_select {
 369	RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
 370	RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
 371	RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
 372	RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
 373	RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
 374	RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
 375	RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
 376	RB_RBPERF_RB_MARB_DATA = 7,
 377	RB_RBPERF_SP_RB_QUAD = 8,
 378	RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
 379	RB_RBPERF_GMEM_CH0_READ = 10,
 380	RB_RBPERF_GMEM_CH1_READ = 11,
 381	RB_RBPERF_GMEM_CH0_WRITE = 12,
 382	RB_RBPERF_GMEM_CH1_WRITE = 13,
 383	RB_RBPERF_CP_CONTEXT_DONE = 14,
 384	RB_RBPERF_CP_CACHE_FLUSH = 15,
 385	RB_RBPERF_CP_ZPASS_DONE = 16,
 386};
 387
 388enum a3xx_rbbm_perfcounter_select {
 389	RBBM_ALAWYS_ON = 0,
 390	RBBM_VBIF_BUSY = 1,
 391	RBBM_TSE_BUSY = 2,
 392	RBBM_RAS_BUSY = 3,
 393	RBBM_PC_DCALL_BUSY = 4,
 394	RBBM_PC_VSD_BUSY = 5,
 395	RBBM_VFD_BUSY = 6,
 396	RBBM_VPC_BUSY = 7,
 397	RBBM_UCHE_BUSY = 8,
 398	RBBM_VSC_BUSY = 9,
 399	RBBM_HLSQ_BUSY = 10,
 400	RBBM_ANY_RB_BUSY = 11,
 401	RBBM_ANY_TEX_BUSY = 12,
 402	RBBM_ANY_USP_BUSY = 13,
 403	RBBM_ANY_MARB_BUSY = 14,
 404	RBBM_ANY_ARB_BUSY = 15,
 405	RBBM_AHB_STATUS_BUSY = 16,
 406	RBBM_AHB_STATUS_STALLED = 17,
 407	RBBM_AHB_STATUS_TXFR = 18,
 408	RBBM_AHB_STATUS_TXFR_SPLIT = 19,
 409	RBBM_AHB_STATUS_TXFR_ERROR = 20,
 410	RBBM_AHB_STATUS_LONG_STALL = 21,
 411	RBBM_RBBM_STATUS_MASKED = 22,
 412};
 413
 414enum a3xx_sp_perfcounter_select {
 415	SP_LM_LOAD_INSTRUCTIONS = 0,
 416	SP_LM_STORE_INSTRUCTIONS = 1,
 417	SP_LM_ATOMICS = 2,
 418	SP_UCHE_LOAD_INSTRUCTIONS = 3,
 419	SP_UCHE_STORE_INSTRUCTIONS = 4,
 420	SP_UCHE_ATOMICS = 5,
 421	SP_VS_TEX_INSTRUCTIONS = 6,
 422	SP_VS_CFLOW_INSTRUCTIONS = 7,
 423	SP_VS_EFU_INSTRUCTIONS = 8,
 424	SP_VS_FULL_ALU_INSTRUCTIONS = 9,
 425	SP_VS_HALF_ALU_INSTRUCTIONS = 10,
 426	SP_FS_TEX_INSTRUCTIONS = 11,
 427	SP_FS_CFLOW_INSTRUCTIONS = 12,
 428	SP_FS_EFU_INSTRUCTIONS = 13,
 429	SP_FS_FULL_ALU_INSTRUCTIONS = 14,
 430	SP_FS_HALF_ALU_INSTRUCTIONS = 15,
 431	SP_FS_BARY_INSTRUCTIONS = 16,
 432	SP_VS_INSTRUCTIONS = 17,
 433	SP_FS_INSTRUCTIONS = 18,
 434	SP_ADDR_LOCK_COUNT = 19,
 435	SP_UCHE_READ_TRANS = 20,
 436	SP_UCHE_WRITE_TRANS = 21,
 437	SP_EXPORT_VPC_TRANS = 22,
 438	SP_EXPORT_RB_TRANS = 23,
 439	SP_PIXELS_KILLED = 24,
 440	SP_ICL1_REQUESTS = 25,
 441	SP_ICL1_MISSES = 26,
 442	SP_ICL0_REQUESTS = 27,
 443	SP_ICL0_MISSES = 28,
 444	SP_ALU_ACTIVE_CYCLES = 29,
 445	SP_EFU_ACTIVE_CYCLES = 30,
 446	SP_STALL_CYCLES_BY_VPC = 31,
 447	SP_STALL_CYCLES_BY_TP = 32,
 448	SP_STALL_CYCLES_BY_UCHE = 33,
 449	SP_STALL_CYCLES_BY_RB = 34,
 450	SP_ACTIVE_CYCLES_ANY = 35,
 451	SP_ACTIVE_CYCLES_ALL = 36,
 452};
 453
 454enum a3xx_tp_perfcounter_select {
 455	TPL1_TPPERF_L1_REQUESTS = 0,
 456	TPL1_TPPERF_TP0_L1_REQUESTS = 1,
 457	TPL1_TPPERF_TP0_L1_MISSES = 2,
 458	TPL1_TPPERF_TP1_L1_REQUESTS = 3,
 459	TPL1_TPPERF_TP1_L1_MISSES = 4,
 460	TPL1_TPPERF_TP2_L1_REQUESTS = 5,
 461	TPL1_TPPERF_TP2_L1_MISSES = 6,
 462	TPL1_TPPERF_TP3_L1_REQUESTS = 7,
 463	TPL1_TPPERF_TP3_L1_MISSES = 8,
 464	TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
 465	TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
 466	TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
 467	TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
 468	TPL1_TPPERF_BILINEAR_OPS = 13,
 469	TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
 470	TPL1_TPPERF_QUADQUADS_SHADOW = 15,
 471	TPL1_TPPERF_QUADS_ARRAY = 16,
 472	TPL1_TPPERF_QUADS_PROJECTION = 17,
 473	TPL1_TPPERF_QUADS_GRADIENT = 18,
 474	TPL1_TPPERF_QUADS_1D2D = 19,
 475	TPL1_TPPERF_QUADS_3DCUBE = 20,
 476	TPL1_TPPERF_ZERO_LOD = 21,
 477	TPL1_TPPERF_OUTPUT_TEXELS = 22,
 478	TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
 479	TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
 480	TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
 481	TPL1_TPPERF_LATENCY = 26,
 482	TPL1_TPPERF_LATENCY_TRANS = 27,
 483};
 484
 485enum a3xx_vfd_perfcounter_select {
 486	VFD_PERF_UCHE_BYTE_FETCHED = 0,
 487	VFD_PERF_UCHE_TRANS = 1,
 488	VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
 489	VFD_PERF_FETCH_INSTRUCTIONS = 3,
 490	VFD_PERF_DECODE_INSTRUCTIONS = 4,
 491	VFD_PERF_ACTIVE_CYCLES = 5,
 492	VFD_PERF_STALL_CYCLES_UCHE = 6,
 493	VFD_PERF_STALL_CYCLES_HLSQ = 7,
 494	VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
 495	VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
 496};
 497
 498enum a3xx_vpc_perfcounter_select {
 499	VPC_PERF_SP_LM_PRIMITIVES = 0,
 500	VPC_PERF_COMPONENTS_FROM_SP = 1,
 501	VPC_PERF_SP_LM_COMPONENTS = 2,
 502	VPC_PERF_ACTIVE_CYCLES = 3,
 503	VPC_PERF_STALL_CYCLES_LM = 4,
 504	VPC_PERF_STALL_CYCLES_RAS = 5,
 505};
 506
 507enum a3xx_uche_perfcounter_select {
 508	UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
 509	UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
 510	UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
 511	UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
 512	UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
 513	UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
 514	UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
 515	UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
 516	UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
 517	UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
 518	UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
 519	UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
 520	UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
 521	UCHE_UCHEPERF_EVICTS = 16,
 522	UCHE_UCHEPERF_FLUSHES = 17,
 523	UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
 524	UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
 525	UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
 526};
 527
 528enum a3xx_rb_blend_opcode {
 529	BLEND_DST_PLUS_SRC = 0,
 530	BLEND_SRC_MINUS_DST = 1,
 531	BLEND_DST_MINUS_SRC = 2,
 532	BLEND_MIN_DST_SRC = 3,
 533	BLEND_MAX_DST_SRC = 4,
 534};
 535
 536enum a3xx_intp_mode {
 537	SMOOTH = 0,
 538	FLAT = 1,
 539	ZERO = 2,
 540	ONE = 3,
 541};
 542
 543enum a3xx_repl_mode {
 544	S = 1,
 545	T = 2,
 546	ONE_T = 3,
 547};
 548
 549enum a3xx_tex_filter {
 550	A3XX_TEX_NEAREST = 0,
 551	A3XX_TEX_LINEAR = 1,
 552	A3XX_TEX_ANISO = 2,
 553};
 554
 555enum a3xx_tex_clamp {
 556	A3XX_TEX_REPEAT = 0,
 557	A3XX_TEX_CLAMP_TO_EDGE = 1,
 558	A3XX_TEX_MIRROR_REPEAT = 2,
 559	A3XX_TEX_CLAMP_TO_BORDER = 3,
 560	A3XX_TEX_MIRROR_CLAMP = 4,
 561};
 562
 563enum a3xx_tex_aniso {
 564	A3XX_TEX_ANISO_1 = 0,
 565	A3XX_TEX_ANISO_2 = 1,
 566	A3XX_TEX_ANISO_4 = 2,
 567	A3XX_TEX_ANISO_8 = 3,
 568	A3XX_TEX_ANISO_16 = 4,
 569};
 570
 571enum a3xx_tex_swiz {
 572	A3XX_TEX_X = 0,
 573	A3XX_TEX_Y = 1,
 574	A3XX_TEX_Z = 2,
 575	A3XX_TEX_W = 3,
 576	A3XX_TEX_ZERO = 4,
 577	A3XX_TEX_ONE = 5,
 578};
 579
 580enum a3xx_tex_type {
 581	A3XX_TEX_1D = 0,
 582	A3XX_TEX_2D = 1,
 583	A3XX_TEX_CUBE = 2,
 584	A3XX_TEX_3D = 3,
 585};
 586
 587enum a3xx_tex_msaa {
 588	A3XX_TPL1_MSAA1X = 0,
 589	A3XX_TPL1_MSAA2X = 1,
 590	A3XX_TPL1_MSAA4X = 2,
 591	A3XX_TPL1_MSAA8X = 3,
 592};
 593
 594#define A3XX_INT0_RBBM_GPU_IDLE					0x00000001
 595#define A3XX_INT0_RBBM_AHB_ERROR				0x00000002
 596#define A3XX_INT0_RBBM_REG_TIMEOUT				0x00000004
 597#define A3XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
 598#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
 599#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00000020
 600#define A3XX_INT0_VFD_ERROR					0x00000040
 601#define A3XX_INT0_CP_SW_INT					0x00000080
 602#define A3XX_INT0_CP_T0_PACKET_IN_IB				0x00000100
 603#define A3XX_INT0_CP_OPCODE_ERROR				0x00000200
 604#define A3XX_INT0_CP_RESERVED_BIT_ERROR				0x00000400
 605#define A3XX_INT0_CP_HW_FAULT					0x00000800
 606#define A3XX_INT0_CP_DMA					0x00001000
 607#define A3XX_INT0_CP_IB2_INT					0x00002000
 608#define A3XX_INT0_CP_IB1_INT					0x00004000
 609#define A3XX_INT0_CP_RB_INT					0x00008000
 610#define A3XX_INT0_CP_REG_PROTECT_FAULT				0x00010000
 611#define A3XX_INT0_CP_RB_DONE_TS					0x00020000
 612#define A3XX_INT0_CP_VS_DONE_TS					0x00040000
 613#define A3XX_INT0_CP_PS_DONE_TS					0x00080000
 614#define A3XX_INT0_CACHE_FLUSH_TS				0x00100000
 615#define A3XX_INT0_CP_AHB_ERROR_HALT				0x00200000
 616#define A3XX_INT0_MISC_HANG_DETECT				0x01000000
 617#define A3XX_INT0_UCHE_OOB_ACCESS				0x02000000
 618#define REG_A3XX_RBBM_HW_VERSION				0x00000000
 619
 620#define REG_A3XX_RBBM_HW_RELEASE				0x00000001
 621
 622#define REG_A3XX_RBBM_HW_CONFIGURATION				0x00000002
 623
 624#define REG_A3XX_RBBM_CLOCK_CTL					0x00000010
 625
 626#define REG_A3XX_RBBM_SP_HYST_CNT				0x00000012
 627
 628#define REG_A3XX_RBBM_SW_RESET_CMD				0x00000018
 629
 630#define REG_A3XX_RBBM_AHB_CTL0					0x00000020
 631
 632#define REG_A3XX_RBBM_AHB_CTL1					0x00000021
 633
 634#define REG_A3XX_RBBM_AHB_CMD					0x00000022
 635
 636#define REG_A3XX_RBBM_AHB_ERROR_STATUS				0x00000027
 637
 638#define REG_A3XX_RBBM_GPR0_CTL					0x0000002e
 639
 640#define REG_A3XX_RBBM_STATUS					0x00000030
 641#define A3XX_RBBM_STATUS_HI_BUSY				0x00000001
 642#define A3XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
 643#define A3XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
 644#define A3XX_RBBM_STATUS_CP_NRT_BUSY				0x00004000
 645#define A3XX_RBBM_STATUS_VBIF_BUSY				0x00008000
 646#define A3XX_RBBM_STATUS_TSE_BUSY				0x00010000
 647#define A3XX_RBBM_STATUS_RAS_BUSY				0x00020000
 648#define A3XX_RBBM_STATUS_RB_BUSY				0x00040000
 649#define A3XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
 650#define A3XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
 651#define A3XX_RBBM_STATUS_VFD_BUSY				0x00200000
 652#define A3XX_RBBM_STATUS_VPC_BUSY				0x00400000
 653#define A3XX_RBBM_STATUS_UCHE_BUSY				0x00800000
 654#define A3XX_RBBM_STATUS_SP_BUSY				0x01000000
 655#define A3XX_RBBM_STATUS_TPL1_BUSY				0x02000000
 656#define A3XX_RBBM_STATUS_MARB_BUSY				0x04000000
 657#define A3XX_RBBM_STATUS_VSC_BUSY				0x08000000
 658#define A3XX_RBBM_STATUS_ARB_BUSY				0x10000000
 659#define A3XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
 660#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC				0x40000000
 661#define A3XX_RBBM_STATUS_GPU_BUSY				0x80000000
 662
 663#define REG_A3XX_RBBM_NQWAIT_UNTIL				0x00000040
 664
 665#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL			0x00000033
 666
 667#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL			0x00000050
 668
 669#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0			0x00000051
 670
 671#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1			0x00000054
 672
 673#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2			0x00000057
 674
 675#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3			0x0000005a
 676
 677#define REG_A3XX_RBBM_INT_SET_CMD				0x00000060
 678
 679#define REG_A3XX_RBBM_INT_CLEAR_CMD				0x00000061
 680
 681#define REG_A3XX_RBBM_INT_0_MASK				0x00000063
 682
 683#define REG_A3XX_RBBM_INT_0_STATUS				0x00000064
 684
 685#define REG_A3XX_RBBM_PERFCTR_CTL				0x00000080
 686#define A3XX_RBBM_PERFCTR_CTL_ENABLE				0x00000001
 687
 688#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0				0x00000081
 689
 690#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1				0x00000082
 691
 692#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000084
 693
 694#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000085
 695
 696#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT			0x00000086
 697
 698#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT			0x00000087
 699
 700#define REG_A3XX_RBBM_GPU_BUSY_MASKED				0x00000088
 701
 702#define REG_A3XX_RBBM_PERFCTR_CP_0_LO				0x00000090
 703
 704#define REG_A3XX_RBBM_PERFCTR_CP_0_HI				0x00000091
 705
 706#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO				0x00000092
 707
 708#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI				0x00000093
 709
 710#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO				0x00000094
 711
 712#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI				0x00000095
 713
 714#define REG_A3XX_RBBM_PERFCTR_PC_0_LO				0x00000096
 715
 716#define REG_A3XX_RBBM_PERFCTR_PC_0_HI				0x00000097
 717
 718#define REG_A3XX_RBBM_PERFCTR_PC_1_LO				0x00000098
 719
 720#define REG_A3XX_RBBM_PERFCTR_PC_1_HI				0x00000099
 721
 722#define REG_A3XX_RBBM_PERFCTR_PC_2_LO				0x0000009a
 723
 724#define REG_A3XX_RBBM_PERFCTR_PC_2_HI				0x0000009b
 725
 726#define REG_A3XX_RBBM_PERFCTR_PC_3_LO				0x0000009c
 727
 728#define REG_A3XX_RBBM_PERFCTR_PC_3_HI				0x0000009d
 729
 730#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO				0x0000009e
 731
 732#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI				0x0000009f
 733
 734#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO				0x000000a0
 735
 736#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI				0x000000a1
 737
 738#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO				0x000000a2
 739
 740#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI				0x000000a3
 741
 742#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO				0x000000a4
 743
 744#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI				0x000000a5
 745
 746#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO				0x000000a6
 747
 748#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI				0x000000a7
 749
 750#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO				0x000000a8
 751
 752#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI				0x000000a9
 753
 754#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO				0x000000aa
 755
 756#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI				0x000000ab
 757
 758#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO				0x000000ac
 759
 760#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI				0x000000ad
 761
 762#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO				0x000000ae
 763
 764#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI				0x000000af
 765
 766#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO				0x000000b0
 767
 768#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI				0x000000b1
 769
 770#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO				0x000000b2
 771
 772#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI				0x000000b3
 773
 774#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO				0x000000b4
 775
 776#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI				0x000000b5
 777
 778#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO				0x000000b6
 779
 780#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI				0x000000b7
 781
 782#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO				0x000000b8
 783
 784#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI				0x000000b9
 785
 786#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO				0x000000ba
 787
 788#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI				0x000000bb
 789
 790#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO				0x000000bc
 791
 792#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI				0x000000bd
 793
 794#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO				0x000000be
 795
 796#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI				0x000000bf
 797
 798#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO				0x000000c0
 799
 800#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI				0x000000c1
 801
 802#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO				0x000000c2
 803
 804#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI				0x000000c3
 805
 806#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO				0x000000c4
 807
 808#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI				0x000000c5
 809
 810#define REG_A3XX_RBBM_PERFCTR_TP_0_LO				0x000000c6
 811
 812#define REG_A3XX_RBBM_PERFCTR_TP_0_HI				0x000000c7
 813
 814#define REG_A3XX_RBBM_PERFCTR_TP_1_LO				0x000000c8
 815
 816#define REG_A3XX_RBBM_PERFCTR_TP_1_HI				0x000000c9
 817
 818#define REG_A3XX_RBBM_PERFCTR_TP_2_LO				0x000000ca
 819
 820#define REG_A3XX_RBBM_PERFCTR_TP_2_HI				0x000000cb
 821
 822#define REG_A3XX_RBBM_PERFCTR_TP_3_LO				0x000000cc
 823
 824#define REG_A3XX_RBBM_PERFCTR_TP_3_HI				0x000000cd
 825
 826#define REG_A3XX_RBBM_PERFCTR_TP_4_LO				0x000000ce
 827
 828#define REG_A3XX_RBBM_PERFCTR_TP_4_HI				0x000000cf
 829
 830#define REG_A3XX_RBBM_PERFCTR_TP_5_LO				0x000000d0
 831
 832#define REG_A3XX_RBBM_PERFCTR_TP_5_HI				0x000000d1
 833
 834#define REG_A3XX_RBBM_PERFCTR_SP_0_LO				0x000000d2
 835
 836#define REG_A3XX_RBBM_PERFCTR_SP_0_HI				0x000000d3
 837
 838#define REG_A3XX_RBBM_PERFCTR_SP_1_LO				0x000000d4
 839
 840#define REG_A3XX_RBBM_PERFCTR_SP_1_HI				0x000000d5
 841
 842#define REG_A3XX_RBBM_PERFCTR_SP_2_LO				0x000000d6
 843
 844#define REG_A3XX_RBBM_PERFCTR_SP_2_HI				0x000000d7
 845
 846#define REG_A3XX_RBBM_PERFCTR_SP_3_LO				0x000000d8
 847
 848#define REG_A3XX_RBBM_PERFCTR_SP_3_HI				0x000000d9
 849
 850#define REG_A3XX_RBBM_PERFCTR_SP_4_LO				0x000000da
 851
 852#define REG_A3XX_RBBM_PERFCTR_SP_4_HI				0x000000db
 853
 854#define REG_A3XX_RBBM_PERFCTR_SP_5_LO				0x000000dc
 855
 856#define REG_A3XX_RBBM_PERFCTR_SP_5_HI				0x000000dd
 857
 858#define REG_A3XX_RBBM_PERFCTR_SP_6_LO				0x000000de
 859
 860#define REG_A3XX_RBBM_PERFCTR_SP_6_HI				0x000000df
 861
 862#define REG_A3XX_RBBM_PERFCTR_SP_7_LO				0x000000e0
 863
 864#define REG_A3XX_RBBM_PERFCTR_SP_7_HI				0x000000e1
 865
 866#define REG_A3XX_RBBM_PERFCTR_RB_0_LO				0x000000e2
 867
 868#define REG_A3XX_RBBM_PERFCTR_RB_0_HI				0x000000e3
 869
 870#define REG_A3XX_RBBM_PERFCTR_RB_1_LO				0x000000e4
 871
 872#define REG_A3XX_RBBM_PERFCTR_RB_1_HI				0x000000e5
 873
 874#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO				0x000000ea
 875
 876#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI				0x000000eb
 877
 878#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO				0x000000ec
 879
 880#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI				0x000000ed
 881
 882#define REG_A3XX_RBBM_RBBM_CTL					0x00000100
 883
 884#define REG_A3XX_RBBM_DEBUG_BUS_CTL				0x00000111
 885
 886#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS			0x00000112
 887
 888#define REG_A3XX_CP_PFP_UCODE_ADDR				0x000001c9
 889
 890#define REG_A3XX_CP_PFP_UCODE_DATA				0x000001ca
 891
 892#define REG_A3XX_CP_ROQ_ADDR					0x000001cc
 893
 894#define REG_A3XX_CP_ROQ_DATA					0x000001cd
 895
 896#define REG_A3XX_CP_MERCIU_ADDR					0x000001d1
 897
 898#define REG_A3XX_CP_MERCIU_DATA					0x000001d2
 899
 900#define REG_A3XX_CP_MERCIU_DATA2				0x000001d3
 901
 902#define REG_A3XX_CP_MEQ_ADDR					0x000001da
 903
 904#define REG_A3XX_CP_MEQ_DATA					0x000001db
 905
 906#define REG_A3XX_CP_WFI_PEND_CTR				0x000001f5
 907
 908#define REG_A3XX_RBBM_PM_OVERRIDE2				0x0000039d
 909
 910#define REG_A3XX_CP_PERFCOUNTER_SELECT				0x00000445
 911
 912#define REG_A3XX_CP_HW_FAULT					0x0000045c
 913
 914#define REG_A3XX_CP_PROTECT_CTRL				0x0000045e
 915
 916#define REG_A3XX_CP_PROTECT_STATUS				0x0000045f
 917
 918static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 919
 920static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
 921
 922#define REG_A3XX_CP_AHB_FAULT					0x0000054d
 923
 924#define REG_A3XX_SQ_GPR_MANAGEMENT				0x00000d00
 925
 926#define REG_A3XX_SQ_INST_STORE_MANAGMENT			0x00000d02
 927
 928#define REG_A3XX_TP0_CHICKEN					0x00000e1e
 929
 930#define REG_A3XX_SP_GLOBAL_MEM_SIZE				0x00000e22
 931
 932#define REG_A3XX_SP_GLOBAL_MEM_ADDR				0x00000e23
 933
 934#define REG_A3XX_GRAS_CL_CLIP_CNTL				0x00002040
 935#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER			0x00001000
 936#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
 937#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
 938#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE		0x00080000
 939#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE			0x00100000
 940#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE		0x00200000
 941#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000
 942#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD				0x00800000
 943#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD				0x01000000
 944#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE			0x02000000
 945#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK	0x1c000000
 946#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT	26
 947static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
 948{
 949	return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
 950}
 951
 952#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ				0x00002044
 953#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK			0x000003ff
 954#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT			0
 955static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
 956{
 957	return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
 958}
 959#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK			0x000ffc00
 960#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT			10
 961static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
 962{
 963	return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
 964}
 965
 966#define REG_A3XX_GRAS_CL_VPORT_XOFFSET				0x00002048
 967#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
 968#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
 969static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
 970{
 971	return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
 972}
 973
 974#define REG_A3XX_GRAS_CL_VPORT_XSCALE				0x00002049
 975#define A3XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
 976#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
 977static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
 978{
 979	return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
 980}
 981
 982#define REG_A3XX_GRAS_CL_VPORT_YOFFSET				0x0000204a
 983#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
 984#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
 985static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
 986{
 987	return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
 988}
 989
 990#define REG_A3XX_GRAS_CL_VPORT_YSCALE				0x0000204b
 991#define A3XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
 992#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
 993static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
 994{
 995	return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
 996}
 997
 998#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET				0x0000204c
 999#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
1000#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
1001static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
1002{
1003	return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
1004}
1005
1006#define REG_A3XX_GRAS_CL_VPORT_ZSCALE				0x0000204d
1007#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
1008#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
1009static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
1010{
1011	return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
1012}
1013
1014#define REG_A3XX_GRAS_SU_POINT_MINMAX				0x00002068
1015#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
1016#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
1017static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1018{
1019	return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1020}
1021#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
1022#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT			16
1023static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1024{
1025	return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
1026}
1027
1028#define REG_A3XX_GRAS_SU_POINT_SIZE				0x00002069
1029#define A3XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
1030#define A3XX_GRAS_SU_POINT_SIZE__SHIFT				0
1031static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
1032{
1033	return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
1034}
1035
1036#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE			0x0000206c
1037#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK		0x00ffffff
1038#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT		0
1039static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
1040{
1041	return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
1042}
1043
1044#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET			0x0000206d
1045#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
1046#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
1047static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
1048{
1049	return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
1050}
1051
1052#define REG_A3XX_GRAS_SU_MODE_CONTROL				0x00002070
1053#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT			0x00000001
1054#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK			0x00000002
1055#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW			0x00000004
1056#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK		0x000007f8
1057#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT		3
1058static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
1059{
1060	return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
1061}
1062#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800
1063
1064#define REG_A3XX_GRAS_SC_CONTROL				0x00002072
1065#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK			0x000000f0
1066#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT			4
1067static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1068{
1069	return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
1070}
1071#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK			0x00000f00
1072#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT		8
1073static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
1074{
1075	return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
1076}
1077#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK			0x0000f000
1078#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT			12
1079static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
1080{
1081	return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
1082}
1083
1084#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL			0x00002074
1085#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
1086#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
1087#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
1088static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1089{
1090	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
1091}
1092#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
1093#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
1094static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1095{
1096	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
1097}
1098
1099#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR			0x00002075
1100#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
1101#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
1102#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
1103static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1104{
1105	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
1106}
1107#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
1108#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
1109static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1110{
1111	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
1112}
1113
1114#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL			0x00002079
1115#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
1116#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
1117#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
1118static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
1119{
1120	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
1121}
1122#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
1123#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
1124static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
1125{
1126	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
1127}
1128
1129#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000207a
1130#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
1131#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
1132#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
1133static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
1134{
1135	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
1136}
1137#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
1138#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
1139static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
1140{
1141	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
1142}
1143
1144#define REG_A3XX_RB_MODE_CONTROL				0x000020c0
1145#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS			0x00000080
1146#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK			0x00000700
1147#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT			8
1148static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1149{
1150	return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
1151}
1152#define A3XX_RB_MODE_CONTROL_MRT__MASK				0x00003000
1153#define A3XX_RB_MODE_CONTROL_MRT__SHIFT				12
1154static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
1155{
1156	return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
1157}
1158#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE		0x00008000
1159#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE		0x00010000
1160
1161#define REG_A3XX_RB_RENDER_CONTROL				0x000020c1
1162#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE		0x00000001
1163#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE			0x00000002
1164#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE		0x00000004
1165#define A3XX_RB_RENDER_CONTROL_FACENESS				0x00000008
1166#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK			0x00000ff0
1167#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT			4
1168static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
1169{
1170	return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
1171}
1172#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00001000
1173#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM			0x00002000
1174#define A3XX_RB_RENDER_CONTROL_XCOORD				0x00004000
1175#define A3XX_RB_RENDER_CONTROL_YCOORD				0x00008000
1176#define A3XX_RB_RENDER_CONTROL_ZCOORD				0x00010000
1177#define A3XX_RB_RENDER_CONTROL_WCOORD				0x00020000
1178#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE			0x00080000
1179#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE		0x00100000
1180#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST			0x00400000
1181#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK		0x07000000
1182#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT		24
1183static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1184{
1185	return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
1186}
1187#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE		0x40000000
1188#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE			0x80000000
1189
1190#define REG_A3XX_RB_MSAA_CONTROL				0x000020c2
1191#define A3XX_RB_MSAA_CONTROL_DISABLE				0x00000400
1192#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK			0x0000f000
1193#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT			12
1194static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
1195{
1196	return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
1197}
1198#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK			0xffff0000
1199#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT			16
1200static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
1201{
1202	return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
1203}
1204
1205#define REG_A3XX_RB_ALPHA_REF					0x000020c3
1206#define A3XX_RB_ALPHA_REF_UINT__MASK				0x0000ff00
1207#define A3XX_RB_ALPHA_REF_UINT__SHIFT				8
1208static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
1209{
1210	return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
1211}
1212#define A3XX_RB_ALPHA_REF_FLOAT__MASK				0xffff0000
1213#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT				16
1214static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
1215{
1216	return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1217}
1218
1219static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1220
1221static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1222#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
1223#define A3XX_RB_MRT_CONTROL_BLEND				0x00000010
1224#define A3XX_RB_MRT_CONTROL_BLEND2				0x00000020
1225#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000f00
1226#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT			8
1227static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
1228{
1229	return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
1230}
1231#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK			0x00003000
1232#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT			12
1233static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1234{
1235	return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
1236}
1237#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x0f000000
1238#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT		24
1239static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
1240{
1241	return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
1242}
1243
1244static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
1245#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x0000003f
1246#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
1247static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
1248{
1249	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1250}
1251#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x000000c0
1252#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT		6
1253static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
1254{
1255	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1256}
1257#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00000c00
1258#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT			10
1259static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1260{
1261	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1262}
1263#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00004000
1264#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0xfffe0000
1265#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		17
1266static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1267{
1268	return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1269}
1270
1271static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
1272#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK		0xfffffff0
1273#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT		4
1274static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
1275{
1276	return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
1277}
1278
1279static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
1280#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
1281#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
1282static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1283{
1284	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1285}
1286#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
1287#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
1288static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1289{
1290	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1291}
1292#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
1293#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT	8
1294static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1295{
1296	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1297}
1298#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
1299#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT	16
1300static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1301{
1302	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1303}
1304#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
1305#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
1306static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1307{
1308	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1309}
1310#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
1311#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT	24
1312static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1313{
1314	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1315}
1316#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE			0x20000000
1317
1318#define REG_A3XX_RB_BLEND_RED					0x000020e4
1319#define A3XX_RB_BLEND_RED_UINT__MASK				0x000000ff
1320#define A3XX_RB_BLEND_RED_UINT__SHIFT				0
1321static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
1322{
1323	return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
1324}
1325#define A3XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
1326#define A3XX_RB_BLEND_RED_FLOAT__SHIFT				16
1327static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
1328{
1329	return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1330}
1331
1332#define REG_A3XX_RB_BLEND_GREEN					0x000020e5
1333#define A3XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
1334#define A3XX_RB_BLEND_GREEN_UINT__SHIFT				0
1335static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
1336{
1337	return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
1338}
1339#define A3XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
1340#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT			16
1341static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
1342{
1343	return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1344}
1345
1346#define REG_A3XX_RB_BLEND_BLUE					0x000020e6
1347#define A3XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
1348#define A3XX_RB_BLEND_BLUE_UINT__SHIFT				0
1349static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
1350{
1351	return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
1352}
1353#define A3XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
1354#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT				16
1355static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
1356{
1357	return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1358}
1359
1360#define REG_A3XX_RB_BLEND_ALPHA					0x000020e7
1361#define A3XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
1362#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT				0
1363static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1364{
1365	return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
1366}
1367#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
1368#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16
1369static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
1370{
1371	return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1372}
1373
1374#define REG_A3XX_RB_CLEAR_COLOR_DW0				0x000020e8
1375
1376#define REG_A3XX_RB_CLEAR_COLOR_DW1				0x000020e9
1377
1378#define REG_A3XX_RB_CLEAR_COLOR_DW2				0x000020ea
1379
1380#define REG_A3XX_RB_CLEAR_COLOR_DW3				0x000020eb
1381
1382#define REG_A3XX_RB_COPY_CONTROL				0x000020ec
1383#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK			0x00000003
1384#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT		0
1385static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1386{
1387	return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1388}
1389#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR				0x00000008
1390#define A3XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
1391#define A3XX_RB_COPY_CONTROL_MODE__SHIFT			4
1392static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1393{
1394	return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
1395}
1396#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00
1397#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8
1398static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1399{
1400	return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1401}
1402#define A3XX_RB_COPY_CONTROL_UNK12				0x00001000
1403#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000
1404#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14
1405static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1406{
1407	return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1408}
1409
1410#define REG_A3XX_RB_COPY_DEST_BASE				0x000020ed
1411#define A3XX_RB_COPY_DEST_BASE_BASE__MASK			0xfffffff0
1412#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT			4
1413static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1414{
1415	return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
1416}
1417
1418#define REG_A3XX_RB_COPY_DEST_PITCH				0x000020ee
1419#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK			0xffffffff
1420#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0
1421static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1422{
1423	return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1424}
1425
1426#define REG_A3XX_RB_COPY_DEST_INFO				0x000020ef
1427#define A3XX_RB_COPY_DEST_INFO_TILE__MASK			0x00000003
1428#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT			0
1429static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
1430{
1431	return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
1432}
1433#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK			0x000000fc
1434#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT			2
1435static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
1436{
1437	return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1438}
1439#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK			0x00000300
1440#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT			8
1441static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1442{
1443	return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
1444}
1445#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
1446#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT		10
1447static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1448{
1449	return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1450}
1451#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK		0x0003c000
1452#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT		14
1453static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1454{
1455	return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1456}
1457#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK			0x001c0000
1458#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT			18
1459static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1460{
1461	return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1462}
1463
1464#define REG_A3XX_RB_DEPTH_CONTROL				0x00002100
1465#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z			0x00000001
1466#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE				0x00000002
1467#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE			0x00000004
1468#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00000008
1469#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK			0x00000070
1470#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT			4
1471static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1472{
1473	return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1474}
1475#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE				0x00000080
1476#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000
1477
1478#define REG_A3XX_RB_DEPTH_CLEAR					0x00002101
1479
1480#define REG_A3XX_RB_DEPTH_INFO					0x00002102
1481#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000003
1482#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
1483static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
1484{
1485	return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1486}
1487#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff800
1488#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			11
1489static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1490{
1491	return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1492}
1493
1494#define REG_A3XX_RB_DEPTH_PITCH					0x00002103
1495#define A3XX_RB_DEPTH_PITCH__MASK				0xffffffff
1496#define A3XX_RB_DEPTH_PITCH__SHIFT				0
1497static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
1498{
1499	return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
1500}
1501
1502#define REG_A3XX_RB_STENCIL_CONTROL				0x00002104
1503#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
1504#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
1505#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
1506#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
1507#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT			8
1508static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1509{
1510	return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
1511}
1512#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
1513#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT			11
1514static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1515{
1516	return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
1517}
1518#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
1519#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT			14
1520static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1521{
1522	return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1523}
1524#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
1525#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT			17
1526static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1527{
1528	return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1529}
1530#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
1531#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT			20
1532static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1533{
1534	return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1535}
1536#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
1537#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT			23
1538static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1539{
1540	return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1541}
1542#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
1543#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT			26
1544static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1545{
1546	return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1547}
1548#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
1549#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT			29
1550static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1551{
1552	return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1553}
1554
1555#define REG_A3XX_RB_STENCIL_CLEAR				0x00002105
1556
1557#define REG_A3XX_RB_STENCIL_INFO				0x00002106
1558#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK			0xfffff800
1559#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		11
1560static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1561{
1562	return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1563}
1564
1565#define REG_A3XX_RB_STENCIL_PITCH				0x00002107
1566#define A3XX_RB_STENCIL_PITCH__MASK				0xffffffff
1567#define A3XX_RB_STENCIL_PITCH__SHIFT				0
1568static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
1569{
1570	return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
1571}
1572
1573#define REG_A3XX_RB_STENCILREFMASK				0x00002108
1574#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
1575#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
1576static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1577{
1578	return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
1579}
1580#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
1581#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT		8
1582static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1583{
1584	return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1585}
1586#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
1587#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT		16
1588static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1589{
1590	return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1591}
1592
1593#define REG_A3XX_RB_STENCILREFMASK_BF				0x00002109
1594#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
1595#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
1596static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1597{
1598	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1599}
1600#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
1601#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT		8
1602static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1603{
1604	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1605}
1606#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
1607#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT	16
1608static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1609{
1610	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1611}
1612
1613#define REG_A3XX_RB_LRZ_VSC_CONTROL				0x0000210c
1614#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE			0x00000002
1615
1616#define REG_A3XX_RB_WINDOW_OFFSET				0x0000210e
1617#define A3XX_RB_WINDOW_OFFSET_X__MASK				0x0000ffff
1618#define A3XX_RB_WINDOW_OFFSET_X__SHIFT				0
1619static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
1620{
1621	return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
1622}
1623#define A3XX_RB_WINDOW_OFFSET_Y__MASK				0xffff0000
1624#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT				16
1625static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1626{
1627	return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
1628}
1629
1630#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL			0x00002110
1631#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET			0x00000001
1632#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
1633
1634#define REG_A3XX_RB_SAMPLE_COUNT_ADDR				0x00002111
1635
1636#define REG_A3XX_RB_Z_CLAMP_MIN					0x00002114
1637
1638#define REG_A3XX_RB_Z_CLAMP_MAX					0x00002115
1639
1640#define REG_A3XX_VGT_BIN_BASE					0x000021e1
1641
1642#define REG_A3XX_VGT_BIN_SIZE					0x000021e2
1643
1644#define REG_A3XX_PC_VSTREAM_CONTROL				0x000021e4
1645#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000
1646#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT			16
1647static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
1648{
1649	return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
1650}
1651#define A3XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000
1652#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT			22
1653static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
1654{
1655	return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
1656}
1657
1658#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL			0x000021ea
1659
1660#define REG_A3XX_PC_PRIM_VTX_CNTL				0x000021ec
1661#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK		0x0000001f
1662#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT		0
1663static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
1664{
1665	return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
1666}
1667#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK	0x000000e0
1668#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT	5
1669static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1670{
1671	return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
1672}
1673#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK		0x00000700
1674#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT	8
1675static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1676{
1677	return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
1678}
1679#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE			0x00001000
1680#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART			0x00100000
1681#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
1682#define A3XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000
1683
1684#define REG_A3XX_PC_RESTART_INDEX				0x000021ed
1685
1686#define REG_A3XX_HLSQ_CONTROL_0_REG				0x00002200
1687#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000030
1688#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT		4
1689static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1690{
1691	return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1692}
1693#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE		0x00000040
1694#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE			0x00000100
1695#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART			0x00000200
1696#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2			0x00000400
1697#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK	0x00fff000
1698#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT	12
1699static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
1700{
1701	return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
1702}
1703#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX			0x02000000
1704#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE			0x04000000
1705#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK			0x08000000
1706#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT		27
1707static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1708{
1709	return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1710}
1711#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE		0x10000000
1712#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE		0x20000000
1713#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE			0x40000000
1714#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT			0x80000000
1715
1716#define REG_A3XX_HLSQ_CONTROL_1_REG				0x00002201
1717#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK		0x000000c0
1718#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT		6
1719static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1720{
1721	return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1722}
1723#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE		0x00000100
1724#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK		0x00ff0000
1725#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT		16
1726static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
1727{
1728	return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
1729}
1730#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK		0xff000000
1731#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT		24
1732static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
1733{
1734	return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
1735}
1736
1737#define REG_A3XX_HLSQ_CONTROL_2_REG				0x00002202
1738#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK		0x000003fc
1739#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT		2
1740static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
1741{
1742	return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
1743}
1744#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK		0x03fc0000
1745#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT		18
1746static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
1747{
1748	return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
1749}
1750#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK	0xfc000000
1751#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT	26
1752static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1753{
1754	return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1755}
1756
1757#define REG_A3XX_HLSQ_CONTROL_3_REG				0x00002203
1758#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK			0x000000ff
1759#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT			0
1760static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1761{
1762	return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1763}
1764
1765#define REG_A3XX_HLSQ_VS_CONTROL_REG				0x00002204
1766#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK		0x000003ff
1767#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT		0
1768static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1769{
1770	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1771}
1772#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK		0x001ff000
1773#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT	12
1774static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1775{
1776	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1777}
1778#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
1779#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT		24
1780static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1781{
1782	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1783}
1784
1785#define REG_A3XX_HLSQ_FS_CONTROL_REG				0x00002205
1786#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK		0x000003ff
1787#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT		0
1788static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1789{
1790	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1791}
1792#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK		0x001ff000
1793#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT	12
1794static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1795{
1796	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1797}
1798#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
1799#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT		24
1800static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1801{
1802	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1803}
1804
1805#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG			0x00002206
1806#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK	0x000001ff
1807#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT	0
1808static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1809{
1810	return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
1811}
1812#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK	0x01ff0000
1813#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT	16
1814static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1815{
1816	return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
1817}
1818
1819#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG			0x00002207
1820#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK	0x000001ff
1821#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT	0
1822static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1823{
1824	return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
1825}
1826#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK	0x01ff0000
1827#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT	16
1828static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1829{
1830	return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
1831}
1832
1833#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG				0x0000220a
1834#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK		0x00000003
1835#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT		0
1836static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
1837{
1838	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
1839}
1840#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK		0x00000ffc
1841#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT		2
1842static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
1843{
1844	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
1845}
1846#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK		0x003ff000
1847#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT		12
1848static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
1849{
1850	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
1851}
1852#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK		0xffc00000
1853#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT		22
1854static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
1855{
1856	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
1857}
1858
1859static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1860
1861static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1862
1863static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
1864
1865#define REG_A3XX_HLSQ_CL_CONTROL_0_REG				0x00002211
1866
1867#define REG_A3XX_HLSQ_CL_CONTROL_1_REG				0x00002212
1868
1869#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG			0x00002214
1870
1871static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1872
1873static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1874
1875#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG			0x00002216
1876
1877#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG			0x00002217
1878
1879#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG				0x0000221a
1880
1881#define REG_A3XX_VFD_CONTROL_0					0x00002240
1882#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK			0x0003ffff
1883#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT			0
1884static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1885{
1886	return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1887}
1888#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK			0x003c0000
1889#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT			18
1890static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
1891{
1892	return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
1893}
1894#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK		0x07c00000
1895#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT		22
1896static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1897{
1898	return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1899}
1900#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK		0xf8000000
1901#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT		27
1902static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1903{
1904	return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1905}
1906
1907#define REG_A3XX_VFD_CONTROL_1					0x00002241
1908#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK			0x0000000f
1909#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT			0
1910static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1911{
1912	return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1913}
1914#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK			0x000000f0
1915#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT			4
1916static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
1917{
1918	return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
1919}
1920#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK			0x00000f00
1921#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT			8
1922static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
1923{
1924	return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
1925}
1926#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK			0x00ff0000
1927#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT			16
1928static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1929{
1930	return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
1931}
1932#define A3XX_VFD_CONTROL_1_REGID4INST__MASK			0xff000000
1933#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT			24
1934static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1935{
1936	return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
1937}
1938
1939#define REG_A3XX_VFD_INDEX_MIN					0x00002242
1940
1941#define REG_A3XX_VFD_INDEX_MAX					0x00002243
1942
1943#define REG_A3XX_VFD_INSTANCEID_OFFSET				0x00002244
1944
1945#define REG_A3XX_VFD_INDEX_OFFSET				0x00002245
1946
1947#define REG_A3XX_VFD_INDEX_OFFSET				0x00002245
1948
1949static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1950
1951static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1952#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
1953#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT			0
1954static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1955{
1956	return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1957}
1958#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK			0x0000ff80
1959#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT			7
1960static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1961{
1962	return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1963}
1964#define A3XX_VFD_FETCH_INSTR_0_INSTANCED			0x00010000
1965#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT			0x00020000
1966#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK			0x00fc0000
1967#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT			18
1968static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
1969{
1970	return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
1971}
1972#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK			0xff000000
1973#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT			24
1974static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
1975{
1976	return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
1977}
1978
1979static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
1980
1981static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1982
1983static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1984#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
1985#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT			0
1986static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1987{
1988	return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1989}
1990#define A3XX_VFD_DECODE_INSTR_CONSTFILL				0x00000010
1991#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK			0x00000fc0
1992#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT			6
1993static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
1994{
1995	return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
1996}
1997#define A3XX_VFD_DECODE_INSTR_REGID__MASK			0x000ff000
1998#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT			12
1999static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
2000{
2001	return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
2002}
2003#define A3XX_VFD_DECODE_INSTR_INT				0x00100000
2004#define A3XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
2005#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT			22
2006static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2007{
2008	return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
2009}
2010#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
2011#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT			24
2012static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2013{
2014	return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2015}
2016#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID			0x20000000
2017#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT			0x40000000
2018
2019#define REG_A3XX_VFD_VS_THREADING_THRESHOLD			0x0000227e
2020#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK	0x0000000f
2021#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT	0
2022static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
2023{
2024	return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
2025}
2026#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK	0x0000ff00
2027#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT	8
2028static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
2029{
2030	return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
2031}
2032
2033#define REG_A3XX_VPC_ATTR					0x00002280
2034#define A3XX_VPC_ATTR_TOTALATTR__MASK				0x000001ff
2035#define A3XX_VPC_ATTR_TOTALATTR__SHIFT				0
2036static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
2037{
2038	return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
2039}
2040#define A3XX_VPC_ATTR_PSIZE					0x00000200
2041#define A3XX_VPC_ATTR_THRDASSIGN__MASK				0x0ffff000
2042#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT				12
2043static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2044{
2045	return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
2046}
2047#define A3XX_VPC_ATTR_LMSIZE__MASK				0xf0000000
2048#define A3XX_VPC_ATTR_LMSIZE__SHIFT				28
2049static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
2050{
2051	return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
2052}
2053
2054#define REG_A3XX_VPC_PACK					0x00002281
2055#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK			0x0000ff00
2056#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT			8
2057static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2058{
2059	return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2060}
2061#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK			0x00ff0000
2062#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT			16
2063static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2064{
2065	return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2066}
2067
2068static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2069
2070static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2071#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK			0x00000003
2072#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT			0
2073static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
2074{
2075	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
2076}
2077#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK			0x0000000c
2078#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT			2
2079static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
2080{
2081	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
2082}
2083#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK			0x00000030
2084#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT			4
2085static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
2086{
2087	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
2088}
2089#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK			0x000000c0
2090#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT			6
2091static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
2092{
2093	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
2094}
2095#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK			0x00000300
2096#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT			8
2097static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
2098{
2099	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
2100}
2101#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK			0x00000c00
2102#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT			10
2103static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
2104{
2105	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
2106}
2107#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK			0x00003000
2108#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT			12
2109static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
2110{
2111	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
2112}
2113#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK			0x0000c000
2114#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT			14
2115static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
2116{
2117	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
2118}
2119#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK			0x00030000
2120#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT			16
2121static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
2122{
2123	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
2124}
2125#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK			0x000c0000
2126#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT			18
2127static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
2128{
2129	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
2130}
2131#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK			0x00300000
2132#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT			20
2133static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
2134{
2135	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
2136}
2137#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK			0x00c00000
2138#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT			22
2139static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
2140{
2141	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
2142}
2143#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK			0x03000000
2144#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT			24
2145static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
2146{
2147	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
2148}
2149#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK			0x0c000000
2150#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT			26
2151static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
2152{
2153	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
2154}
2155#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK			0x30000000
2156#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT			28
2157static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
2158{
2159	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
2160}
2161#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK			0xc0000000
2162#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT			30
2163static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
2164{
2165	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
2166}
2167
2168static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2169
2170static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2171#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK			0x00000003
2172#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT			0
2173static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
2174{
2175	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
2176}
2177#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK			0x0000000c
2178#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT			2
2179static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
2180{
2181	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
2182}
2183#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK			0x00000030
2184#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT			4
2185static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
2186{
2187	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
2188}
2189#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK			0x000000c0
2190#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT			6
2191static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
2192{
2193	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
2194}
2195#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK			0x00000300
2196#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT			8
2197static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
2198{
2199	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
2200}
2201#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK			0x00000c00
2202#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT			10
2203static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
2204{
2205	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
2206}
2207#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK			0x00003000
2208#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT			12
2209static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
2210{
2211	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
2212}
2213#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK			0x0000c000
2214#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT			14
2215static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
2216{
2217	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
2218}
2219#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK			0x00030000
2220#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT			16
2221static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
2222{
2223	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
2224}
2225#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK			0x000c0000
2226#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT			18
2227static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
2228{
2229	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
2230}
2231#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK			0x00300000
2232#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT			20
2233static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
2234{
2235	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
2236}
2237#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK			0x00c00000
2238#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT			22
2239static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
2240{
2241	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
2242}
2243#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK			0x03000000
2244#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT			24
2245static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
2246{
2247	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
2248}
2249#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK			0x0c000000
2250#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT			26
2251static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
2252{
2253	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
2254}
2255#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK			0x30000000
2256#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT			28
2257static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
2258{
2259	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
2260}
2261#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK			0xc0000000
2262#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT			30
2263static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
2264{
2265	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
2266}
2267
2268#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0			0x0000228a
2269
2270#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1			0x0000228b
2271
2272#define REG_A3XX_SP_SP_CTRL_REG					0x000022c0
2273#define A3XX_SP_SP_CTRL_REG_RESOLVE				0x00010000
2274#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK			0x00040000
2275#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT			18
2276static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
2277{
2278	return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
2279}
2280#define A3XX_SP_SP_CTRL_REG_BINNING				0x00080000
2281#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK			0x00300000
2282#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT			20
2283static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
2284{
2285	return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
2286}
2287#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK			0x00c00000
2288#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT			22
2289static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
2290{
2291	return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
2292}
2293
2294#define REG_A3XX_SP_VS_CTRL_REG0				0x000022c4
2295#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
2296#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
2297static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2298{
2299	return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2300}
2301#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK		0x00000002
2302#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT		1
2303static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2304{
2305	return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2306}
2307#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID			0x00000004
2308#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE				0x00000008
2309#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2310#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
2311static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2312{
2313	return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2314}
2315#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2316#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
2317static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2318{
2319	return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2320}
2321#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2322#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
2323static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2324{
2325	return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2326}
2327#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2328#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK			0xff000000
2329#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT			24
2330static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
2331{
2332	return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
2333}
2334
2335#define REG_A3XX_SP_VS_CTRL_REG1				0x000022c5
2336#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK			0x000003ff
2337#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2338static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2339{
2340	return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2341}
2342#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK		0x000ffc00
2343#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT		10
2344static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2345{
2346	return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2347}
2348#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x7f000000
2349#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		24
2350static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2351{
2352	return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2353}
2354
2355#define REG_A3XX_SP_VS_PARAM_REG				0x000022c6
2356#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK			0x000000ff
2357#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT			0
2358static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2359{
2360	return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
2361}
2362#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK			0x0000ff00
2363#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT			8
2364static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2365{
2366	return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2367}
2368#define A3XX_SP_VS_PARAM_REG_POS2DMODE				0x00010000
2369#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK		0x01f00000
2370#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT		20
2371static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2372{
2373	return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2374}
2375
2376static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2377
2378static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2379#define A3XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
2380#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
2381static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2382{
2383	return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
2384}
2385#define A3XX_SP_VS_OUT_REG_A_HALF				0x00000100
2386#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2387#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT			9
2388static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2389{
2390	return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2391}
2392#define A3XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
2393#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT			16
2394static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2395{
2396	return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
2397}
2398#define A3XX_SP_VS_OUT_REG_B_HALF				0x01000000
2399#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2400#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT			25
2401static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2402{
2403	return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2404}
2405
2406static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2407
2408static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2409#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x0000007f
2410#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
2411static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2412{
2413	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2414}
2415#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x00007f00
2416#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT			8
2417static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2418{
2419	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2420}
2421#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x007f0000
2422#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT			16
2423static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2424{
2425	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2426}
2427#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0x7f000000
2428#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT			24
2429static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2430{
2431	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2432}
2433
2434#define REG_A3XX_SP_VS_OBJ_OFFSET_REG				0x000022d4
2435#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK	0x0000ffff
2436#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT	0
2437static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2438{
2439	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2440}
2441#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2442#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2443static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2444{
2445	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2446}
2447#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2448#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2449static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2450{
2451	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2452}
2453
2454#define REG_A3XX_SP_VS_OBJ_START_REG				0x000022d5
2455
2456#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG			0x000022d6
2457#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK	0x000000ff
2458#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT	0
2459static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2460{
2461	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2462}
2463#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK	0x00ffff00
2464#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT	8
2465static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2466{
2467	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2468}
2469#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK	0xff000000
2470#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT	24
2471static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2472{
2473	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2474}
2475
2476#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG				0x000022d7
2477#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK		0x0000001f
2478#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT		0
2479static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2480{
2481	return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2482}
2483#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK	0xffffffe0
2484#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5
2485static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2486{
2487	return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2488}
2489
2490#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG				0x000022d8
2491
2492#define REG_A3XX_SP_VS_LENGTH_REG				0x000022df
2493#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK		0xffffffff
2494#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT		0
2495static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2496{
2497	return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
2498}
2499
2500#define REG_A3XX_SP_FS_CTRL_REG0				0x000022e0
2501#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
2502#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
2503static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2504{
2505	return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2506}
2507#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK		0x00000002
2508#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT		1
2509static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2510{
2511	return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2512}
2513#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID			0x00000004
2514#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE				0x00000008
2515#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2516#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
2517static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2518{
2519	return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2520}
2521#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2522#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
2523static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2524{
2525	return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2526}
2527#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE			0x00020000
2528#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP			0x00040000
2529#define A3XX_SP_FS_CTRL_REG0_OUTORDERED				0x00080000
2530#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2531#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT			20
2532static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2533{
2534	return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2535}
2536#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2537#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00400000
2538#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE			0x00800000
2539#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK			0xff000000
2540#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT			24
2541static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
2542{
2543	return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
2544}
2545
2546#define REG_A3XX_SP_FS_CTRL_REG1				0x000022e1
2547#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK			0x000003ff
2548#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2549static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2550{
2551	return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2552}
2553#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK		0x000ffc00
2554#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT		10
2555static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2556{
2557	return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2558}
2559#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x00f00000
2560#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		20
2561static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2562{
2563	return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2564}
2565#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK		0x7f000000
2566#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT		24
2567static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
2568{
2569	return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
2570}
2571
2572#define REG_A3XX_SP_FS_OBJ_OFFSET_REG				0x000022e2
2573#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK	0x0000ffff
2574#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT	0
2575static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2576{
2577	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2578}
2579#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2580#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2581static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2582{
2583	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2584}
2585#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2586#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2587static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2588{
2589	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2590}
2591
2592#define REG_A3XX_SP_FS_OBJ_START_REG				0x000022e3
2593
2594#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG			0x000022e4
2595#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK	0x000000ff
2596#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT	0
2597static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2598{
2599	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2600}
2601#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK	0x00ffff00
2602#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT	8
2603static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2604{
2605	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2606}
2607#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK	0xff000000
2608#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT	24
2609static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2610{
2611	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2612}
2613
2614#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG				0x000022e5
2615#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK		0x0000001f
2616#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT		0
2617static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2618{
2619	return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2620}
2621#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK	0xffffffe0
2622#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5
2623static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2624{
2625	return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2626}
2627
2628#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG				0x000022e6
2629
2630#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0			0x000022e8
2631
2632#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1			0x000022e9
2633
2634#define REG_A3XX_SP_FS_OUTPUT_REG				0x000022ec
2635#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK				0x00000003
2636#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
2637static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2638{
2639	return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
2640}
2641#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
2642#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
2643#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT		8
2644static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2645{
2646	return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2647}
2648
2649static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2650
2651static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2652#define A3XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
2653#define A3XX_SP_FS_MRT_REG_REGID__SHIFT				0
2654static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
2655{
2656	return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
2657}
2658#define A3XX_SP_FS_MRT_REG_HALF_PRECISION			0x00000100
2659#define A3XX_SP_FS_MRT_REG_SINT					0x00000400
2660#define A3XX_SP_FS_MRT_REG_UINT					0x00000800
2661
2662static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2663
2664static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2665#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK		0x0000003f
2666#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT		0
2667static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
2668{
2669	return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
2670}
2671
2672#define REG_A3XX_SP_FS_LENGTH_REG				0x000022ff
2673#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK		0xffffffff
2674#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT		0
2675static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2676{
2677	return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
2678}
2679
2680#define REG_A3XX_PA_SC_AA_CONFIG				0x00002301
2681
2682#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET				0x00002340
2683#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK		0x000000ff
2684#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT		0
2685static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2686{
2687	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2688}
2689#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK		0x0000ff00
2690#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT		8
2691static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2692{
2693	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2694}
2695#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK		0xffff0000
2696#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT		16
2697static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2698{
2699	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
2700}
2701
2702#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR		0x00002341
2703
2704#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET				0x00002342
2705#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK		0x000000ff
2706#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT		0
2707static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2708{
2709	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2710}
2711#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK		0x0000ff00
2712#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT		8
2713static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2714{
2715	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2716}
2717#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK		0xffff0000
2718#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT		16
2719static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2720{
2721	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
2722}
2723
2724#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR		0x00002343
2725
2726#define REG_A3XX_VBIF_CLKON					0x00003001
2727
2728#define REG_A3XX_VBIF_FIXED_SORT_EN				0x0000300c
2729
2730#define REG_A3XX_VBIF_FIXED_SORT_SEL0				0x0000300d
2731
2732#define REG_A3XX_VBIF_FIXED_SORT_SEL1				0x0000300e
2733
2734#define REG_A3XX_VBIF_ABIT_SORT					0x0000301c
2735
2736#define REG_A3XX_VBIF_ABIT_SORT_CONF				0x0000301d
2737
2738#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
2739
2740#define REG_A3XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
2741
2742#define REG_A3XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
2743
2744#define REG_A3XX_VBIF_IN_WR_LIM_CONF0				0x00003030
2745
2746#define REG_A3XX_VBIF_IN_WR_LIM_CONF1				0x00003031
2747
2748#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0				0x00003034
2749
2750#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0				0x00003035
2751
2752#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST				0x00003036
2753
2754#define REG_A3XX_VBIF_ARB_CTL					0x0000303c
2755
2756#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
2757
2758#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0			0x00003058
2759
2760#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN				0x0000305e
2761
2762#define REG_A3XX_VBIF_OUT_AXI_AOOO				0x0000305f
2763
2764#define REG_A3XX_VBIF_PERF_CNT_EN				0x00003070
2765#define A3XX_VBIF_PERF_CNT_EN_CNT0				0x00000001
2766#define A3XX_VBIF_PERF_CNT_EN_CNT1				0x00000002
2767#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0				0x00000004
2768#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1				0x00000008
2769#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2				0x00000010
2770
2771#define REG_A3XX_VBIF_PERF_CNT_CLR				0x00003071
2772#define A3XX_VBIF_PERF_CNT_CLR_CNT0				0x00000001
2773#define A3XX_VBIF_PERF_CNT_CLR_CNT1				0x00000002
2774#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0				0x00000004
2775#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1				0x00000008
2776#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2				0x00000010
2777
2778#define REG_A3XX_VBIF_PERF_CNT_SEL				0x00003072
2779
2780#define REG_A3XX_VBIF_PERF_CNT0_LO				0x00003073
2781
2782#define REG_A3XX_VBIF_PERF_CNT0_HI				0x00003074
2783
2784#define REG_A3XX_VBIF_PERF_CNT1_LO				0x00003075
2785
2786#define REG_A3XX_VBIF_PERF_CNT1_HI				0x00003076
2787
2788#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO				0x00003077
2789
2790#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI				0x00003078
2791
2792#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO				0x00003079
2793
2794#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI				0x0000307a
2795
2796#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO				0x0000307b
2797
2798#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI				0x0000307c
2799
2800#define REG_A3XX_VSC_BIN_SIZE					0x00000c01
2801#define A3XX_VSC_BIN_SIZE_WIDTH__MASK				0x0000001f
2802#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2803static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2804{
2805	return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
2806}
2807#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0
2808#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT				5
2809static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2810{
2811	return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
2812}
2813
2814#define REG_A3XX_VSC_SIZE_ADDRESS				0x00000c02
2815
2816static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2817
2818static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2819#define A3XX_VSC_PIPE_CONFIG_X__MASK				0x000003ff
2820#define A3XX_VSC_PIPE_CONFIG_X__SHIFT				0
2821static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
2822{
2823	return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
2824}
2825#define A3XX_VSC_PIPE_CONFIG_Y__MASK				0x000ffc00
2826#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT				10
2827static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
2828{
2829	return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
2830}
2831#define A3XX_VSC_PIPE_CONFIG_W__MASK				0x00f00000
2832#define A3XX_VSC_PIPE_CONFIG_W__SHIFT				20
2833static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
2834{
2835	return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
2836}
2837#define A3XX_VSC_PIPE_CONFIG_H__MASK				0x0f000000
2838#define A3XX_VSC_PIPE_CONFIG_H__SHIFT				24
2839static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
2840{
2841	return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
2842}
2843
2844static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
2845
2846static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
2847
2848#define REG_A3XX_VSC_BIN_CONTROL				0x00000c3c
2849#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE			0x00000001
2850
2851#define REG_A3XX_UNKNOWN_0C3D					0x00000c3d
2852
2853#define REG_A3XX_PC_PERFCOUNTER0_SELECT				0x00000c48
2854
2855#define REG_A3XX_PC_PERFCOUNTER1_SELECT				0x00000c49
2856
2857#define REG_A3XX_PC_PERFCOUNTER2_SELECT				0x00000c4a
2858
2859#define REG_A3XX_PC_PERFCOUNTER3_SELECT				0x00000c4b
2860
2861#define REG_A3XX_GRAS_TSE_DEBUG_ECO				0x00000c81
2862
2863#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT			0x00000c88
2864
2865#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT			0x00000c89
2866
2867#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT			0x00000c8a
2868
2869#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT			0x00000c8b
2870
2871static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2872
2873static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2874
2875static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
2876
2877static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
2878
2879static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
2880
2881#define REG_A3XX_RB_GMEM_BASE_ADDR				0x00000cc0
2882
2883#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR			0x00000cc1
2884
2885#define REG_A3XX_RB_PERFCOUNTER0_SELECT				0x00000cc6
2886
2887#define REG_A3XX_RB_PERFCOUNTER1_SELECT				0x00000cc7
2888
2889#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION			0x00000ce0
2890#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK		0x00003fff
2891#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT		0
2892static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
2893{
2894	return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
2895}
2896#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK		0x0fffc000
2897#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT		14
2898static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
2899{
2900	return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
2901}
2902
2903#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT			0x00000e00
2904
2905#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT			0x00000e01
2906
2907#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT			0x00000e02
2908
2909#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT			0x00000e03
2910
2911#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT			0x00000e04
2912
2913#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT			0x00000e05
2914
2915#define REG_A3XX_UNKNOWN_0E43					0x00000e43
2916
2917#define REG_A3XX_VFD_PERFCOUNTER0_SELECT			0x00000e44
2918
2919#define REG_A3XX_VFD_PERFCOUNTER1_SELECT			0x00000e45
2920
2921#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL				0x00000e61
2922
2923#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ				0x00000e62
2924
2925#define REG_A3XX_VPC_PERFCOUNTER0_SELECT			0x00000e64
2926
2927#define REG_A3XX_VPC_PERFCOUNTER1_SELECT			0x00000e65
2928
2929#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG			0x00000e82
2930
2931#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT			0x00000e84
2932
2933#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT			0x00000e85
2934
2935#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT			0x00000e86
2936
2937#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT			0x00000e87
2938
2939#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT			0x00000e88
2940
2941#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT			0x00000e89
2942
2943#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG			0x00000ea0
2944#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK		0x0fffffff
2945#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT		0
2946static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
2947{
2948	return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
2949}
2950
2951#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG			0x00000ea1
2952#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK		0x0fffffff
2953#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT		0
2954static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
2955{
2956	return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
2957}
2958#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK		0x30000000
2959#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT		28
2960static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
2961{
2962	return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
2963}
2964#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE		0x80000000
2965
2966#define REG_A3XX_UNKNOWN_0EA6					0x00000ea6
2967
2968#define REG_A3XX_SP_PERFCOUNTER0_SELECT				0x00000ec4
2969
2970#define REG_A3XX_SP_PERFCOUNTER1_SELECT				0x00000ec5
2971
2972#define REG_A3XX_SP_PERFCOUNTER2_SELECT				0x00000ec6
2973
2974#define REG_A3XX_SP_PERFCOUNTER3_SELECT				0x00000ec7
2975
2976#define REG_A3XX_SP_PERFCOUNTER4_SELECT				0x00000ec8
2977
2978#define REG_A3XX_SP_PERFCOUNTER5_SELECT				0x00000ec9
2979
2980#define REG_A3XX_SP_PERFCOUNTER6_SELECT				0x00000eca
2981
2982#define REG_A3XX_SP_PERFCOUNTER7_SELECT				0x00000ecb
2983
2984#define REG_A3XX_UNKNOWN_0EE0					0x00000ee0
2985
2986#define REG_A3XX_UNKNOWN_0F03					0x00000f03
2987
2988#define REG_A3XX_TP_PERFCOUNTER0_SELECT				0x00000f04
2989
2990#define REG_A3XX_TP_PERFCOUNTER1_SELECT				0x00000f05
2991
2992#define REG_A3XX_TP_PERFCOUNTER2_SELECT				0x00000f06
2993
2994#define REG_A3XX_TP_PERFCOUNTER3_SELECT				0x00000f07
2995
2996#define REG_A3XX_TP_PERFCOUNTER4_SELECT				0x00000f08
2997
2998#define REG_A3XX_TP_PERFCOUNTER5_SELECT				0x00000f09
2999
3000#define REG_A3XX_VGT_CL_INITIATOR				0x000021f0
3001
3002#define REG_A3XX_VGT_EVENT_INITIATOR				0x000021f9
3003
3004#define REG_A3XX_VGT_DRAW_INITIATOR				0x000021fc
3005#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
3006#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0
3007static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
3008{
3009	return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
3010}
3011#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
3012#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6
3013static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
3014{
3015	return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
3016}
3017#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600
3018#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9
3019static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
3020{
3021	return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
3022}
3023#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800
3024#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11
3025static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
3026{
3027	return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
3028}
3029#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000
3030#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000
3031#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000
3032#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK		0xff000000
3033#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT		24
3034static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
3035{
3036	return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
3037}
3038
3039#define REG_A3XX_VGT_IMMED_DATA					0x000021fd
3040
3041#define REG_A3XX_TEX_SAMP_0					0x00000000
3042#define A3XX_TEX_SAMP_0_CLAMPENABLE				0x00000001
3043#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR			0x00000002
3044#define A3XX_TEX_SAMP_0_XY_MAG__MASK				0x0000000c
3045#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT				2
3046static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
3047{
3048	return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
3049}
3050#define A3XX_TEX_SAMP_0_XY_MIN__MASK				0x00000030
3051#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT				4
3052static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
3053{
3054	return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
3055}
3056#define A3XX_TEX_SAMP_0_WRAP_S__MASK				0x000001c0
3057#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT				6
3058static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
3059{
3060	return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
3061}
3062#define A3XX_TEX_SAMP_0_WRAP_T__MASK				0x00000e00
3063#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT				9
3064static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
3065{
3066	return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
3067}
3068#define A3XX_TEX_SAMP_0_WRAP_R__MASK				0x00007000
3069#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT				12
3070static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
3071{
3072	return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
3073}
3074#define A3XX_TEX_SAMP_0_ANISO__MASK				0x00038000
3075#define A3XX_TEX_SAMP_0_ANISO__SHIFT				15
3076static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
3077{
3078	return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
3079}
3080#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK			0x00700000
3081#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT			20
3082static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
3083{
3084	return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
3085}
3086#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF			0x01000000
3087#define A3XX_TEX_SAMP_0_UNNORM_COORDS				0x80000000
3088
3089#define REG_A3XX_TEX_SAMP_1					0x00000001
3090#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK				0x000007ff
3091#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT				0
3092static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
3093{
3094	return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
3095}
3096#define A3XX_TEX_SAMP_1_MAX_LOD__MASK				0x003ff000
3097#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT				12
3098static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
3099{
3100	return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
3101}
3102#define A3XX_TEX_SAMP_1_MIN_LOD__MASK				0xffc00000
3103#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT				22
3104static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
3105{
3106	return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
3107}
3108
3109#define REG_A3XX_TEX_CONST_0					0x00000000
3110#define A3XX_TEX_CONST_0_TILED					0x00000001
3111#define A3XX_TEX_CONST_0_SRGB					0x00000004
3112#define A3XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
3113#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT				4
3114static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
3115{
3116	return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
3117}
3118#define A3XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
3119#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT				7
3120static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
3121{
3122	return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
3123}
3124#define A3XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
3125#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT				10
3126static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
3127{
3128	return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
3129}
3130#define A3XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
3131#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT				13
3132static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
3133{
3134	return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
3135}
3136#define A3XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
3137#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT				16
3138static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
3139{
3140	return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
3141}
3142#define A3XX_TEX_CONST_0_MSAATEX__MASK				0x00300000
3143#define A3XX_TEX_CONST_0_MSAATEX__SHIFT				20
3144static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
3145{
3146	return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
3147}
3148#define A3XX_TEX_CONST_0_FMT__MASK				0x1fc00000
3149#define A3XX_TEX_CONST_0_FMT__SHIFT				22
3150static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
3151{
3152	return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
3153}
3154#define A3XX_TEX_CONST_0_NOCONVERT				0x20000000
3155#define A3XX_TEX_CONST_0_TYPE__MASK				0xc0000000
3156#define A3XX_TEX_CONST_0_TYPE__SHIFT				30
3157static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
3158{
3159	return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
3160}
3161
3162#define REG_A3XX_TEX_CONST_1					0x00000001
3163#define A3XX_TEX_CONST_1_HEIGHT__MASK				0x00003fff
3164#define A3XX_TEX_CONST_1_HEIGHT__SHIFT				0
3165static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
3166{
3167	return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
3168}
3169#define A3XX_TEX_CONST_1_WIDTH__MASK				0x0fffc000
3170#define A3XX_TEX_CONST_1_WIDTH__SHIFT				14
3171static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
3172{
3173	return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
3174}
3175#define A3XX_TEX_CONST_1_FETCHSIZE__MASK			0xf0000000
3176#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT			28
3177static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
3178{
3179	return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
3180}
3181
3182#define REG_A3XX_TEX_CONST_2					0x00000002
3183#define A3XX_TEX_CONST_2_INDX__MASK				0x000001ff
3184#define A3XX_TEX_CONST_2_INDX__SHIFT				0
3185static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
3186{
3187	return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
3188}
3189#define A3XX_TEX_CONST_2_PITCH__MASK				0x3ffff000
3190#define A3XX_TEX_CONST_2_PITCH__SHIFT				12
3191static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
3192{
3193	return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
3194}
3195#define A3XX_TEX_CONST_2_SWAP__MASK				0xc0000000
3196#define A3XX_TEX_CONST_2_SWAP__SHIFT				30
3197static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
3198{
3199	return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
3200}
3201
3202#define REG_A3XX_TEX_CONST_3					0x00000003
3203#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x0001ffff
3204#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT			0
3205static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
3206{
3207	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
3208}
3209#define A3XX_TEX_CONST_3_DEPTH__MASK				0x0ffe0000
3210#define A3XX_TEX_CONST_3_DEPTH__SHIFT				17
3211static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
3212{
3213	return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
3214}
3215#define A3XX_TEX_CONST_3_LAYERSZ2__MASK				0xf0000000
3216#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT			28
3217static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
3218{
3219	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
3220}
3221
3222
3223#endif /* A3XX_XML */