1/*
   2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright © 2006-2009 Intel Corporation
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors:
  25 *	Eric Anholt <eric@anholt.net>
  26 *	Jesse Barnes <jesse.barnes@intel.com>
  27 */
  28
  29#include <linux/i2c.h>
  30#include <linux/slab.h>
  31#include <linux/delay.h>
  32#include <linux/hdmi.h>
  33#include <drm/drmP.h>
  34#include <drm/drm_atomic_helper.h>
  35#include <drm/drm_crtc.h>
  36#include <drm/drm_edid.h>
  37#include "intel_drv.h"
  38#include <drm/i915_drm.h>
  39#include "i915_drv.h"
  40
  41static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42{
  43	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44}
  45
  46static void
  47assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48{
  49	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50	struct drm_i915_private *dev_priv = dev->dev_private;
  51	uint32_t enabled_bits;
  52
  53	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56	     "HDMI port enabled, expecting disabled\n");
  57}
  58
  59struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60{
  61	struct intel_digital_port *intel_dig_port =
  62		container_of(encoder, struct intel_digital_port, base.base);
  63	return &intel_dig_port->hdmi;
  64}
  65
  66static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67{
  68	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
 
  69}
  70
  71static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72{
  73	switch (type) {
  74	case HDMI_INFOFRAME_TYPE_AVI:
  75		return VIDEO_DIP_SELECT_AVI;
  76	case HDMI_INFOFRAME_TYPE_SPD:
  77		return VIDEO_DIP_SELECT_SPD;
  78	case HDMI_INFOFRAME_TYPE_VENDOR:
  79		return VIDEO_DIP_SELECT_VENDOR;
  80	default:
  81		MISSING_CASE(type);
  82		return 0;
  83	}
  84}
  85
  86static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87{
  88	switch (type) {
  89	case HDMI_INFOFRAME_TYPE_AVI:
  90		return VIDEO_DIP_ENABLE_AVI;
  91	case HDMI_INFOFRAME_TYPE_SPD:
  92		return VIDEO_DIP_ENABLE_SPD;
  93	case HDMI_INFOFRAME_TYPE_VENDOR:
  94		return VIDEO_DIP_ENABLE_VENDOR;
  95	default:
  96		MISSING_CASE(type);
  97		return 0;
  98	}
  99}
 100
 101static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102{
 103	switch (type) {
 104	case HDMI_INFOFRAME_TYPE_AVI:
 105		return VIDEO_DIP_ENABLE_AVI_HSW;
 106	case HDMI_INFOFRAME_TYPE_SPD:
 107		return VIDEO_DIP_ENABLE_SPD_HSW;
 108	case HDMI_INFOFRAME_TYPE_VENDOR:
 109		return VIDEO_DIP_ENABLE_VS_HSW;
 110	default:
 111		MISSING_CASE(type);
 112		return 0;
 113	}
 114}
 115
 116static i915_reg_t
 117hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 118		 enum transcoder cpu_transcoder,
 119		 enum hdmi_infoframe_type type,
 120		 int i)
 121{
 122	switch (type) {
 123	case HDMI_INFOFRAME_TYPE_AVI:
 124		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 125	case HDMI_INFOFRAME_TYPE_SPD:
 126		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 127	case HDMI_INFOFRAME_TYPE_VENDOR:
 128		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 129	default:
 130		MISSING_CASE(type);
 131		return INVALID_MMIO_REG;
 132	}
 133}
 134
 135static void g4x_write_infoframe(struct drm_encoder *encoder,
 136				enum hdmi_infoframe_type type,
 137				const void *frame, ssize_t len)
 138{
 139	const uint32_t *data = frame;
 140	struct drm_device *dev = encoder->dev;
 141	struct drm_i915_private *dev_priv = dev->dev_private;
 142	u32 val = I915_READ(VIDEO_DIP_CTL);
 143	int i;
 144
 145	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 146
 147	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 148	val |= g4x_infoframe_index(type);
 149
 150	val &= ~g4x_infoframe_enable(type);
 151
 152	I915_WRITE(VIDEO_DIP_CTL, val);
 153
 154	mmiowb();
 155	for (i = 0; i < len; i += 4) {
 156		I915_WRITE(VIDEO_DIP_DATA, *data);
 157		data++;
 158	}
 159	/* Write every possible data byte to force correct ECC calculation. */
 160	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 161		I915_WRITE(VIDEO_DIP_DATA, 0);
 162	mmiowb();
 163
 164	val |= g4x_infoframe_enable(type);
 165	val &= ~VIDEO_DIP_FREQ_MASK;
 166	val |= VIDEO_DIP_FREQ_VSYNC;
 167
 168	I915_WRITE(VIDEO_DIP_CTL, val);
 169	POSTING_READ(VIDEO_DIP_CTL);
 170}
 171
 172static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 173				  const struct intel_crtc_state *pipe_config)
 174{
 175	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 176	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 177	u32 val = I915_READ(VIDEO_DIP_CTL);
 178
 179	if ((val & VIDEO_DIP_ENABLE) == 0)
 180		return false;
 181
 182	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 183		return false;
 184
 185	return val & (VIDEO_DIP_ENABLE_AVI |
 186		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 187}
 188
 189static void ibx_write_infoframe(struct drm_encoder *encoder,
 190				enum hdmi_infoframe_type type,
 191				const void *frame, ssize_t len)
 192{
 193	const uint32_t *data = frame;
 194	struct drm_device *dev = encoder->dev;
 195	struct drm_i915_private *dev_priv = dev->dev_private;
 196	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 197	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 198	u32 val = I915_READ(reg);
 199	int i;
 200
 201	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 202
 203	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 204	val |= g4x_infoframe_index(type);
 205
 206	val &= ~g4x_infoframe_enable(type);
 207
 208	I915_WRITE(reg, val);
 209
 210	mmiowb();
 211	for (i = 0; i < len; i += 4) {
 212		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 213		data++;
 214	}
 215	/* Write every possible data byte to force correct ECC calculation. */
 216	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 217		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 218	mmiowb();
 219
 220	val |= g4x_infoframe_enable(type);
 221	val &= ~VIDEO_DIP_FREQ_MASK;
 222	val |= VIDEO_DIP_FREQ_VSYNC;
 223
 224	I915_WRITE(reg, val);
 225	POSTING_READ(reg);
 226}
 227
 228static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 229				  const struct intel_crtc_state *pipe_config)
 230{
 231	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 232	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 233	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 234	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 235	u32 val = I915_READ(reg);
 236
 237	if ((val & VIDEO_DIP_ENABLE) == 0)
 238		return false;
 239
 240	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 241		return false;
 242
 243	return val & (VIDEO_DIP_ENABLE_AVI |
 244		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 245		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 246}
 247
 248static void cpt_write_infoframe(struct drm_encoder *encoder,
 249				enum hdmi_infoframe_type type,
 250				const void *frame, ssize_t len)
 251{
 252	const uint32_t *data = frame;
 253	struct drm_device *dev = encoder->dev;
 254	struct drm_i915_private *dev_priv = dev->dev_private;
 255	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 257	u32 val = I915_READ(reg);
 258	int i;
 259
 260	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 261
 262	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 263	val |= g4x_infoframe_index(type);
 
 
 
 
 
 
 
 264
 265	/* The DIP control register spec says that we need to update the AVI
 266	 * infoframe without clearing its enable bit */
 267	if (type != HDMI_INFOFRAME_TYPE_AVI)
 268		val &= ~g4x_infoframe_enable(type);
 269
 270	I915_WRITE(reg, val);
 271
 272	mmiowb();
 273	for (i = 0; i < len; i += 4) {
 274		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 275		data++;
 276	}
 277	/* Write every possible data byte to force correct ECC calculation. */
 278	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 279		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 280	mmiowb();
 281
 282	val |= g4x_infoframe_enable(type);
 283	val &= ~VIDEO_DIP_FREQ_MASK;
 284	val |= VIDEO_DIP_FREQ_VSYNC;
 285
 286	I915_WRITE(reg, val);
 287	POSTING_READ(reg);
 288}
 289
 290static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 291				  const struct intel_crtc_state *pipe_config)
 292{
 293	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 294	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 295	u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 296
 297	if ((val & VIDEO_DIP_ENABLE) == 0)
 298		return false;
 299
 300	return val & (VIDEO_DIP_ENABLE_AVI |
 301		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 302		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 303}
 304
 305static void vlv_write_infoframe(struct drm_encoder *encoder,
 306				enum hdmi_infoframe_type type,
 307				const void *frame, ssize_t len)
 308{
 309	const uint32_t *data = frame;
 310	struct drm_device *dev = encoder->dev;
 311	struct drm_i915_private *dev_priv = dev->dev_private;
 312	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 313	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 314	u32 val = I915_READ(reg);
 315	int i;
 
 316
 317	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 318
 319	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 320	val |= g4x_infoframe_index(type);
 321
 322	val &= ~g4x_infoframe_enable(type);
 323
 324	I915_WRITE(reg, val);
 325
 326	mmiowb();
 327	for (i = 0; i < len; i += 4) {
 328		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 329		data++;
 330	}
 331	/* Write every possible data byte to force correct ECC calculation. */
 332	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 333		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 334	mmiowb();
 335
 336	val |= g4x_infoframe_enable(type);
 337	val &= ~VIDEO_DIP_FREQ_MASK;
 338	val |= VIDEO_DIP_FREQ_VSYNC;
 339
 340	I915_WRITE(reg, val);
 341	POSTING_READ(reg);
 342}
 343
 344static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 345				  const struct intel_crtc_state *pipe_config)
 346{
 347	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 348	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 349	enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 350	u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 351
 352	if ((val & VIDEO_DIP_ENABLE) == 0)
 353		return false;
 354
 355	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 356		return false;
 357
 358	return val & (VIDEO_DIP_ENABLE_AVI |
 359		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 360		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 361}
 362
 363static void hsw_write_infoframe(struct drm_encoder *encoder,
 364				enum hdmi_infoframe_type type,
 365				const void *frame, ssize_t len)
 366{
 367	const uint32_t *data = frame;
 368	struct drm_device *dev = encoder->dev;
 369	struct drm_i915_private *dev_priv = dev->dev_private;
 370	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 371	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
 372	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 373	i915_reg_t data_reg;
 374	int i;
 375	u32 val = I915_READ(ctl_reg);
 376
 377	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 378
 379	val &= ~hsw_infoframe_enable(type);
 380	I915_WRITE(ctl_reg, val);
 381
 382	mmiowb();
 383	for (i = 0; i < len; i += 4) {
 384		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 385					    type, i >> 2), *data);
 386		data++;
 387	}
 388	/* Write every possible data byte to force correct ECC calculation. */
 389	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 390		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 391					    type, i >> 2), 0);
 392	mmiowb();
 393
 394	val |= hsw_infoframe_enable(type);
 395	I915_WRITE(ctl_reg, val);
 396	POSTING_READ(ctl_reg);
 397}
 398
 399static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 400				  const struct intel_crtc_state *pipe_config)
 401{
 402	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 403	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 404
 405	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 406		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 407		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 408}
 409
 410/*
 411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 414 * used for both technologies.
 415 *
 416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 417 * DW1:       DB3       | DB2 | DB1 | DB0
 418 * DW2:       DB7       | DB6 | DB5 | DB4
 419 * DW3: ...
 420 *
 421 * (HB is Header Byte, DB is Data Byte)
 422 *
 423 * The hdmi pack() functions don't know about that hardware specific hole so we
 424 * trick them by giving an offset into the buffer and moving back the header
 425 * bytes by one.
 426 */
 427static void intel_write_infoframe(struct drm_encoder *encoder,
 428				  union hdmi_infoframe *frame)
 429{
 430	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 431	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 432	ssize_t len;
 433
 434	/* see comment above for the reason for this offset */
 435	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 436	if (len < 0)
 437		return;
 438
 439	/* Insert the 'hole' (see big comment above) at position 3 */
 440	buffer[0] = buffer[1];
 441	buffer[1] = buffer[2];
 442	buffer[2] = buffer[3];
 443	buffer[3] = 0;
 444	len++;
 445
 446	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 447}
 448
 449static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 450					 const struct drm_display_mode *adjusted_mode)
 451{
 452	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 453	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 454	union hdmi_infoframe frame;
 455	int ret;
 456
 457	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 458						       adjusted_mode);
 459	if (ret < 0) {
 460		DRM_ERROR("couldn't fill AVI infoframe\n");
 461		return;
 462	}
 463
 464	if (intel_hdmi->rgb_quant_range_selectable) {
 465		if (intel_crtc->config->limited_color_range)
 466			frame.avi.quantization_range =
 467				HDMI_QUANTIZATION_RANGE_LIMITED;
 468		else
 469			frame.avi.quantization_range =
 470				HDMI_QUANTIZATION_RANGE_FULL;
 471	}
 472
 473	intel_write_infoframe(encoder, &frame);
 474}
 475
 476static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 477{
 478	union hdmi_infoframe frame;
 479	int ret;
 480
 481	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 482	if (ret < 0) {
 483		DRM_ERROR("couldn't fill SPD infoframe\n");
 484		return;
 485	}
 486
 487	frame.spd.sdi = HDMI_SPD_SDI_PC;
 488
 489	intel_write_infoframe(encoder, &frame);
 490}
 491
 492static void
 493intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 494			      const struct drm_display_mode *adjusted_mode)
 495{
 496	union hdmi_infoframe frame;
 497	int ret;
 498
 499	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 500							  adjusted_mode);
 501	if (ret < 0)
 502		return;
 503
 504	intel_write_infoframe(encoder, &frame);
 505}
 506
 507static void g4x_set_infoframes(struct drm_encoder *encoder,
 508			       bool enable,
 509			       const struct drm_display_mode *adjusted_mode)
 510{
 511	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 512	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 513	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 514	i915_reg_t reg = VIDEO_DIP_CTL;
 515	u32 val = I915_READ(reg);
 516	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 517
 518	assert_hdmi_port_disabled(intel_hdmi);
 519
 520	/* If the registers were not initialized yet, they might be zeroes,
 521	 * which means we're selecting the AVI DIP and we're setting its
 522	 * frequency to once. This seems to really confuse the HW and make
 523	 * things stop working (the register spec says the AVI always needs to
 524	 * be sent every VSync). So here we avoid writing to the register more
 525	 * than we need and also explicitly select the AVI DIP and explicitly
 526	 * set its frequency to every VSync. Avoiding to write it twice seems to
 527	 * be enough to solve the problem, but being defensive shouldn't hurt us
 528	 * either. */
 529	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 530
 531	if (!enable) {
 532		if (!(val & VIDEO_DIP_ENABLE))
 533			return;
 534		if (port != (val & VIDEO_DIP_PORT_MASK)) {
 535			DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 536				      (val & VIDEO_DIP_PORT_MASK) >> 29);
 537			return;
 538		}
 539		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 540			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 541		I915_WRITE(reg, val);
 542		POSTING_READ(reg);
 543		return;
 544	}
 545
 546	if (port != (val & VIDEO_DIP_PORT_MASK)) {
 547		if (val & VIDEO_DIP_ENABLE) {
 548			DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 549				      (val & VIDEO_DIP_PORT_MASK) >> 29);
 550			return;
 551		}
 552		val &= ~VIDEO_DIP_PORT_MASK;
 553		val |= port;
 554	}
 555
 556	val |= VIDEO_DIP_ENABLE;
 557	val &= ~(VIDEO_DIP_ENABLE_AVI |
 558		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 559
 560	I915_WRITE(reg, val);
 561	POSTING_READ(reg);
 562
 563	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 564	intel_hdmi_set_spd_infoframe(encoder);
 565	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 566}
 567
 568static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 569{
 570	struct drm_device *dev = encoder->dev;
 571	struct drm_connector *connector;
 572
 573	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 574
 575	/*
 576	 * HDMI cloning is only supported on g4x which doesn't
 577	 * support deep color or GCP infoframes anyway so no
 578	 * need to worry about multiple HDMI sinks here.
 579	 */
 580	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 581		if (connector->encoder == encoder)
 582			return connector->display_info.bpc > 8;
 583
 584	return false;
 585}
 586
 587/*
 588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 589 *
 590 * From HDMI specification 1.4a:
 591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 595 *   phase of 0
 596 */
 597static bool gcp_default_phase_possible(int pipe_bpp,
 598				       const struct drm_display_mode *mode)
 599{
 600	unsigned int pixels_per_group;
 601
 602	switch (pipe_bpp) {
 603	case 30:
 604		/* 4 pixels in 5 clocks */
 605		pixels_per_group = 4;
 606		break;
 607	case 36:
 608		/* 2 pixels in 3 clocks */
 609		pixels_per_group = 2;
 610		break;
 611	case 48:
 612		/* 1 pixel in 2 clocks */
 613		pixels_per_group = 1;
 614		break;
 615	default:
 616		/* phase information not relevant for 8bpc */
 617		return false;
 618	}
 619
 620	return mode->crtc_hdisplay % pixels_per_group == 0 &&
 621		mode->crtc_htotal % pixels_per_group == 0 &&
 622		mode->crtc_hblank_start % pixels_per_group == 0 &&
 623		mode->crtc_hblank_end % pixels_per_group == 0 &&
 624		mode->crtc_hsync_start % pixels_per_group == 0 &&
 625		mode->crtc_hsync_end % pixels_per_group == 0 &&
 626		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 627		 mode->crtc_htotal/2 % pixels_per_group == 0);
 628}
 629
 630static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 631{
 632	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 633	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 634	i915_reg_t reg;
 635	u32 val = 0;
 636
 637	if (HAS_DDI(dev_priv))
 638		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 639	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 640		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 641	else if (HAS_PCH_SPLIT(dev_priv->dev))
 642		reg = TVIDEO_DIP_GCP(crtc->pipe);
 643	else
 644		return false;
 645
 646	/* Indicate color depth whenever the sink supports deep color */
 647	if (hdmi_sink_is_deep_color(encoder))
 648		val |= GCP_COLOR_INDICATION;
 649
 650	/* Enable default_phase whenever the display mode is suitably aligned */
 651	if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 652				       &crtc->config->base.adjusted_mode))
 653		val |= GCP_DEFAULT_PHASE_ENABLE;
 654
 655	I915_WRITE(reg, val);
 656
 657	return val != 0;
 658}
 659
 660static void ibx_set_infoframes(struct drm_encoder *encoder,
 661			       bool enable,
 662			       const struct drm_display_mode *adjusted_mode)
 663{
 664	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 665	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 666	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 667	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 668	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 669	u32 val = I915_READ(reg);
 670	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 671
 672	assert_hdmi_port_disabled(intel_hdmi);
 673
 674	/* See the big comment in g4x_set_infoframes() */
 675	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 676
 677	if (!enable) {
 678		if (!(val & VIDEO_DIP_ENABLE))
 679			return;
 680		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 681			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 682			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 683		I915_WRITE(reg, val);
 684		POSTING_READ(reg);
 685		return;
 686	}
 687
 688	if (port != (val & VIDEO_DIP_PORT_MASK)) {
 689		WARN(val & VIDEO_DIP_ENABLE,
 690		     "DIP already enabled on port %c\n",
 691		     (val & VIDEO_DIP_PORT_MASK) >> 29);
 692		val &= ~VIDEO_DIP_PORT_MASK;
 693		val |= port;
 694	}
 695
 696	val |= VIDEO_DIP_ENABLE;
 697	val &= ~(VIDEO_DIP_ENABLE_AVI |
 698		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 699		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 700
 701	if (intel_hdmi_set_gcp_infoframe(encoder))
 702		val |= VIDEO_DIP_ENABLE_GCP;
 703
 704	I915_WRITE(reg, val);
 705	POSTING_READ(reg);
 706
 707	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 708	intel_hdmi_set_spd_infoframe(encoder);
 709	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 710}
 711
 712static void cpt_set_infoframes(struct drm_encoder *encoder,
 713			       bool enable,
 714			       const struct drm_display_mode *adjusted_mode)
 715{
 716	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 717	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 718	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 719	i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 720	u32 val = I915_READ(reg);
 721
 722	assert_hdmi_port_disabled(intel_hdmi);
 723
 724	/* See the big comment in g4x_set_infoframes() */
 725	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 726
 727	if (!enable) {
 728		if (!(val & VIDEO_DIP_ENABLE))
 729			return;
 730		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 731			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 732			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 733		I915_WRITE(reg, val);
 734		POSTING_READ(reg);
 735		return;
 736	}
 737
 738	/* Set both together, unset both together: see the spec. */
 739	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 740	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 741		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 742
 743	if (intel_hdmi_set_gcp_infoframe(encoder))
 744		val |= VIDEO_DIP_ENABLE_GCP;
 745
 746	I915_WRITE(reg, val);
 747	POSTING_READ(reg);
 748
 749	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 750	intel_hdmi_set_spd_infoframe(encoder);
 751	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 752}
 753
 754static void vlv_set_infoframes(struct drm_encoder *encoder,
 755			       bool enable,
 756			       const struct drm_display_mode *adjusted_mode)
 757{
 758	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 759	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 760	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 761	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 762	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 763	u32 val = I915_READ(reg);
 764	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 765
 766	assert_hdmi_port_disabled(intel_hdmi);
 767
 768	/* See the big comment in g4x_set_infoframes() */
 769	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 770
 771	if (!enable) {
 772		if (!(val & VIDEO_DIP_ENABLE))
 773			return;
 774		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 775			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 776			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 777		I915_WRITE(reg, val);
 778		POSTING_READ(reg);
 779		return;
 780	}
 781
 782	if (port != (val & VIDEO_DIP_PORT_MASK)) {
 783		WARN(val & VIDEO_DIP_ENABLE,
 784		     "DIP already enabled on port %c\n",
 785		     (val & VIDEO_DIP_PORT_MASK) >> 29);
 786		val &= ~VIDEO_DIP_PORT_MASK;
 787		val |= port;
 788	}
 789
 790	val |= VIDEO_DIP_ENABLE;
 791	val &= ~(VIDEO_DIP_ENABLE_AVI |
 792		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 793		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 794
 795	if (intel_hdmi_set_gcp_infoframe(encoder))
 796		val |= VIDEO_DIP_ENABLE_GCP;
 797
 798	I915_WRITE(reg, val);
 799	POSTING_READ(reg);
 800
 801	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 802	intel_hdmi_set_spd_infoframe(encoder);
 803	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 804}
 805
 806static void hsw_set_infoframes(struct drm_encoder *encoder,
 807			       bool enable,
 808			       const struct drm_display_mode *adjusted_mode)
 809{
 810	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 811	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 812	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 813	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 814	u32 val = I915_READ(reg);
 815
 816	assert_hdmi_port_disabled(intel_hdmi);
 817
 818	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 819		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 820		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 821
 822	if (!enable) {
 823		I915_WRITE(reg, val);
 824		POSTING_READ(reg);
 825		return;
 826	}
 827
 828	if (intel_hdmi_set_gcp_infoframe(encoder))
 829		val |= VIDEO_DIP_ENABLE_GCP_HSW;
 830
 831	I915_WRITE(reg, val);
 832	POSTING_READ(reg);
 833
 834	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 835	intel_hdmi_set_spd_infoframe(encoder);
 836	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 837}
 838
 839static void intel_hdmi_prepare(struct intel_encoder *encoder)
 840{
 841	struct drm_device *dev = encoder->base.dev;
 842	struct drm_i915_private *dev_priv = dev->dev_private;
 843	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 844	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 845	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 846	u32 hdmi_val;
 847
 848	hdmi_val = SDVO_ENCODING_HDMI;
 849	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
 850		hdmi_val |= HDMI_COLOR_RANGE_16_235;
 851	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 852		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 853	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 854		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 855
 856	if (crtc->config->pipe_bpp > 24)
 857		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 858	else
 859		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 860
 861	if (crtc->config->has_hdmi_sink)
 862		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 863
 864	if (HAS_PCH_CPT(dev))
 865		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 866	else if (IS_CHERRYVIEW(dev))
 867		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 868	else
 869		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 870
 871	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 872	POSTING_READ(intel_hdmi->hdmi_reg);
 873}
 874
 875static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 876				    enum pipe *pipe)
 877{
 878	struct drm_device *dev = encoder->base.dev;
 879	struct drm_i915_private *dev_priv = dev->dev_private;
 880	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 881	enum intel_display_power_domain power_domain;
 882	u32 tmp;
 883	bool ret;
 884
 885	power_domain = intel_display_port_power_domain(encoder);
 886	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 887		return false;
 888
 889	ret = false;
 890
 891	tmp = I915_READ(intel_hdmi->hdmi_reg);
 892
 893	if (!(tmp & SDVO_ENABLE))
 894		goto out;
 895
 896	if (HAS_PCH_CPT(dev))
 897		*pipe = PORT_TO_PIPE_CPT(tmp);
 898	else if (IS_CHERRYVIEW(dev))
 899		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 900	else
 901		*pipe = PORT_TO_PIPE(tmp);
 902
 903	ret = true;
 904
 905out:
 906	intel_display_power_put(dev_priv, power_domain);
 907
 908	return ret;
 909}
 910
 911static void intel_hdmi_get_config(struct intel_encoder *encoder,
 912				  struct intel_crtc_state *pipe_config)
 913{
 914	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 915	struct drm_device *dev = encoder->base.dev;
 916	struct drm_i915_private *dev_priv = dev->dev_private;
 917	u32 tmp, flags = 0;
 918	int dotclock;
 919
 920	tmp = I915_READ(intel_hdmi->hdmi_reg);
 921
 922	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 923		flags |= DRM_MODE_FLAG_PHSYNC;
 924	else
 925		flags |= DRM_MODE_FLAG_NHSYNC;
 926
 927	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 928		flags |= DRM_MODE_FLAG_PVSYNC;
 929	else
 930		flags |= DRM_MODE_FLAG_NVSYNC;
 931
 932	if (tmp & HDMI_MODE_SELECT_HDMI)
 933		pipe_config->has_hdmi_sink = true;
 934
 935	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
 936		pipe_config->has_infoframe = true;
 937
 938	if (tmp & SDVO_AUDIO_ENABLE)
 939		pipe_config->has_audio = true;
 940
 941	if (!HAS_PCH_SPLIT(dev) &&
 942	    tmp & HDMI_COLOR_RANGE_16_235)
 943		pipe_config->limited_color_range = true;
 944
 945	pipe_config->base.adjusted_mode.flags |= flags;
 946
 947	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 948		dotclock = pipe_config->port_clock * 2 / 3;
 949	else
 950		dotclock = pipe_config->port_clock;
 951
 952	if (pipe_config->pixel_multiplier)
 953		dotclock /= pipe_config->pixel_multiplier;
 954
 955	if (HAS_PCH_SPLIT(dev_priv->dev))
 956		ironlake_check_encoder_dotclock(pipe_config, dotclock);
 957
 958	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 959}
 960
 961static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
 962{
 963	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 964
 965	WARN_ON(!crtc->config->has_hdmi_sink);
 966	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 967			 pipe_name(crtc->pipe));
 968	intel_audio_codec_enable(encoder);
 969}
 970
 971static void g4x_enable_hdmi(struct intel_encoder *encoder)
 972{
 973	struct drm_device *dev = encoder->base.dev;
 974	struct drm_i915_private *dev_priv = dev->dev_private;
 975	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 976	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 977	u32 temp;
 978
 979	temp = I915_READ(intel_hdmi->hdmi_reg);
 980
 981	temp |= SDVO_ENABLE;
 982	if (crtc->config->has_audio)
 983		temp |= SDVO_AUDIO_ENABLE;
 984
 985	I915_WRITE(intel_hdmi->hdmi_reg, temp);
 986	POSTING_READ(intel_hdmi->hdmi_reg);
 
 987
 988	if (crtc->config->has_audio)
 989		intel_enable_hdmi_audio(encoder);
 990}
 991
 992static void ibx_enable_hdmi(struct intel_encoder *encoder)
 993{
 994	struct drm_device *dev = encoder->base.dev;
 995	struct drm_i915_private *dev_priv = dev->dev_private;
 996	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 997	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 998	u32 temp;
 999
1000	temp = I915_READ(intel_hdmi->hdmi_reg);
1001
1002	temp |= SDVO_ENABLE;
1003	if (crtc->config->has_audio)
1004		temp |= SDVO_AUDIO_ENABLE;
1005
1006	/*
1007	 * HW workaround, need to write this twice for issue
1008	 * that may result in first write getting masked.
1009	 */
1010	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1011	POSTING_READ(intel_hdmi->hdmi_reg);
1012	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1013	POSTING_READ(intel_hdmi->hdmi_reg);
1014
1015	/*
1016	 * HW workaround, need to toggle enable bit off and on
1017	 * for 12bpc with pixel repeat.
1018	 *
1019	 * FIXME: BSpec says this should be done at the end of
1020	 * of the modeset sequence, so not sure if this isn't too soon.
1021	 */
1022	if (crtc->config->pipe_bpp > 24 &&
1023	    crtc->config->pixel_multiplier > 1) {
1024		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1025		POSTING_READ(intel_hdmi->hdmi_reg);
1026
1027		/*
1028		 * HW workaround, need to write this twice for issue
1029		 * that may result in first write getting masked.
1030		 */
1031		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1032		POSTING_READ(intel_hdmi->hdmi_reg);
1033		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1034		POSTING_READ(intel_hdmi->hdmi_reg);
1035	}
1036
1037	if (crtc->config->has_audio)
1038		intel_enable_hdmi_audio(encoder);
1039}
1040
1041static void cpt_enable_hdmi(struct intel_encoder *encoder)
1042{
1043	struct drm_device *dev = encoder->base.dev;
1044	struct drm_i915_private *dev_priv = dev->dev_private;
1045	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1046	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1047	enum pipe pipe = crtc->pipe;
1048	u32 temp;
1049
1050	temp = I915_READ(intel_hdmi->hdmi_reg);
1051
1052	temp |= SDVO_ENABLE;
1053	if (crtc->config->has_audio)
1054		temp |= SDVO_AUDIO_ENABLE;
1055
1056	/*
1057	 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1058	 *
1059	 * The procedure for 12bpc is as follows:
1060	 * 1. disable HDMI clock gating
1061	 * 2. enable HDMI with 8bpc
1062	 * 3. enable HDMI with 12bpc
1063	 * 4. enable HDMI clock gating
1064	 */
1065
1066	if (crtc->config->pipe_bpp > 24) {
1067		I915_WRITE(TRANS_CHICKEN1(pipe),
1068			   I915_READ(TRANS_CHICKEN1(pipe)) |
1069			   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1070
1071		temp &= ~SDVO_COLOR_FORMAT_MASK;
1072		temp |= SDVO_COLOR_FORMAT_8bpc;
1073	}
1074
1075	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1076	POSTING_READ(intel_hdmi->hdmi_reg);
1077
1078	if (crtc->config->pipe_bpp > 24) {
1079		temp &= ~SDVO_COLOR_FORMAT_MASK;
1080		temp |= HDMI_COLOR_FORMAT_12bpc;
1081
1082		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1083		POSTING_READ(intel_hdmi->hdmi_reg);
1084
1085		I915_WRITE(TRANS_CHICKEN1(pipe),
1086			   I915_READ(TRANS_CHICKEN1(pipe)) &
1087			   ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1088	}
1089
1090	if (crtc->config->has_audio)
1091		intel_enable_hdmi_audio(encoder);
1092}
1093
1094static void vlv_enable_hdmi(struct intel_encoder *encoder)
1095{
1096}
1097
1098static void intel_disable_hdmi(struct intel_encoder *encoder)
1099{
1100	struct drm_device *dev = encoder->base.dev;
1101	struct drm_i915_private *dev_priv = dev->dev_private;
1102	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1103	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1104	u32 temp;
1105
1106	temp = I915_READ(intel_hdmi->hdmi_reg);
1107
1108	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1109	I915_WRITE(intel_hdmi->hdmi_reg, temp);
1110	POSTING_READ(intel_hdmi->hdmi_reg);
1111
1112	/*
1113	 * HW workaround for IBX, we need to move the port
1114	 * to transcoder A after disabling it to allow the
1115	 * matching DP port to be enabled on transcoder A.
1116	 */
1117	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1118		/*
1119		 * We get CPU/PCH FIFO underruns on the other pipe when
1120		 * doing the workaround. Sweep them under the rug.
1121		 */
1122		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1123		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1124
1125		temp &= ~SDVO_PIPE_B_SELECT;
1126		temp |= SDVO_ENABLE;
1127		/*
1128		 * HW workaround, need to write this twice for issue
1129		 * that may result in first write getting masked.
1130		 */
1131		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1132		POSTING_READ(intel_hdmi->hdmi_reg);
1133		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1134		POSTING_READ(intel_hdmi->hdmi_reg);
1135
 
1136		temp &= ~SDVO_ENABLE;
1137		I915_WRITE(intel_hdmi->hdmi_reg, temp);
1138		POSTING_READ(intel_hdmi->hdmi_reg);
1139
1140		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1141		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1142		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1143	}
1144
1145	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1146}
1147
1148static void g4x_disable_hdmi(struct intel_encoder *encoder)
1149{
1150	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1151
1152	if (crtc->config->has_audio)
1153		intel_audio_codec_disable(encoder);
1154
1155	intel_disable_hdmi(encoder);
1156}
1157
1158static void pch_disable_hdmi(struct intel_encoder *encoder)
1159{
1160	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1161
1162	if (crtc->config->has_audio)
1163		intel_audio_codec_disable(encoder);
1164}
1165
1166static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1167{
1168	intel_disable_hdmi(encoder);
1169}
1170
1171static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1172{
1173	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1174
1175	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1176		return 165000;
1177	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1178		return 300000;
1179	else
1180		return 225000;
 
1181}
1182
1183static enum drm_mode_status
1184hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1185		      int clock, bool respect_dvi_limit)
1186{
1187	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1188
1189	if (clock < 25000)
1190		return MODE_CLOCK_LOW;
1191	if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1192		return MODE_CLOCK_HIGH;
1193
1194	/* BXT DPLL can't generate 223-240 MHz */
1195	if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1196		return MODE_CLOCK_RANGE;
1197
1198	/* CHV DPLL can't generate 216-240 MHz */
1199	if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1200		return MODE_CLOCK_RANGE;
1201
1202	return MODE_OK;
1203}
1204
1205static enum drm_mode_status
1206intel_hdmi_mode_valid(struct drm_connector *connector,
1207		      struct drm_display_mode *mode)
1208{
1209	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1210	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1211	enum drm_mode_status status;
1212	int clock;
1213	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1214
1215	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1216		return MODE_NO_DBLESCAN;
1217
1218	clock = mode->clock;
1219
1220	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1221		clock *= 2;
1222
1223	if (clock > max_dotclk)
1224		return MODE_CLOCK_HIGH;
1225
1226	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1227		clock *= 2;
1228
1229	/* check if we can do 8bpc */
1230	status = hdmi_port_clock_valid(hdmi, clock, true);
1231
1232	/* if we can't do 8bpc we may still be able to do 12bpc */
1233	if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1234		status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1235
1236	return status;
1237}
1238
1239static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1240{
1241	struct drm_device *dev = crtc_state->base.crtc->dev;
1242	struct drm_atomic_state *state;
1243	struct intel_encoder *encoder;
1244	struct drm_connector *connector;
1245	struct drm_connector_state *connector_state;
1246	int count = 0, count_hdmi = 0;
1247	int i;
1248
1249	if (HAS_GMCH_DISPLAY(dev))
1250		return false;
1251
1252	state = crtc_state->base.state;
1253
1254	for_each_connector_in_state(state, connector, connector_state, i) {
1255		if (connector_state->crtc != crtc_state->base.crtc)
1256			continue;
1257
1258		encoder = to_intel_encoder(connector_state->best_encoder);
1259
1260		count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1261		count++;
1262	}
1263
1264	/*
1265	 * HDMI 12bpc affects the clocks, so it's only possible
1266	 * when not cloning with other encoder types.
1267	 */
1268	return count_hdmi > 0 && count_hdmi == count;
1269}
1270
1271bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1272			       struct intel_crtc_state *pipe_config)
 
1273{
1274	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1275	struct drm_device *dev = encoder->base.dev;
1276	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1277	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1278	int clock_12bpc = clock_8bpc * 3 / 2;
1279	int desired_bpp;
1280
1281	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1282
1283	if (pipe_config->has_hdmi_sink)
1284		pipe_config->has_infoframe = true;
1285
1286	if (intel_hdmi->color_range_auto) {
1287		/* See CEA-861-E - 5.1 Default Encoding Parameters */
1288		pipe_config->limited_color_range =
1289			pipe_config->has_hdmi_sink &&
1290			drm_match_cea_mode(adjusted_mode) > 1;
1291	} else {
1292		pipe_config->limited_color_range =
1293			intel_hdmi->limited_color_range;
1294	}
1295
1296	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1297		pipe_config->pixel_multiplier = 2;
1298		clock_8bpc *= 2;
1299		clock_12bpc *= 2;
1300	}
1301
1302	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1303		pipe_config->has_pch_encoder = true;
1304
1305	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1306		pipe_config->has_audio = true;
1307
1308	/*
1309	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1310	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1311	 * outputs. We also need to check that the higher clock still fits
1312	 * within limits.
1313	 */
1314	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1315	    hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1316	    hdmi_12bpc_possible(pipe_config)) {
1317		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1318		desired_bpp = 12*3;
1319
1320		/* Need to adjust the port link by 1.5x for 12bpc. */
1321		pipe_config->port_clock = clock_12bpc;
1322	} else {
1323		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1324		desired_bpp = 8*3;
1325
1326		pipe_config->port_clock = clock_8bpc;
1327	}
1328
1329	if (!pipe_config->bw_constrained) {
1330		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1331		pipe_config->pipe_bpp = desired_bpp;
1332	}
1333
1334	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1335				  false) != MODE_OK) {
1336		DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1337		return false;
1338	}
1339
1340	/* Set user selected PAR to incoming mode's member */
1341	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1342
1343	return true;
1344}
1345
1346static void
1347intel_hdmi_unset_edid(struct drm_connector *connector)
1348{
1349	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 
 
 
1350
1351	intel_hdmi->has_hdmi_sink = false;
1352	intel_hdmi->has_audio = false;
1353	intel_hdmi->rgb_quant_range_selectable = false;
1354
1355	kfree(to_intel_connector(connector)->detect_edid);
1356	to_intel_connector(connector)->detect_edid = NULL;
1357}
1358
1359static bool
1360intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1361{
1362	struct drm_i915_private *dev_priv = to_i915(connector->dev);
1363	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1364	struct edid *edid = NULL;
1365	bool connected = false;
1366
1367	if (force) {
1368		intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1369
1370		edid = drm_get_edid(connector,
1371				    intel_gmbus_get_adapter(dev_priv,
1372				    intel_hdmi->ddc_bus));
1373
1374		intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1375	}
1376
1377	to_intel_connector(connector)->detect_edid = edid;
1378	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1379		intel_hdmi->rgb_quant_range_selectable =
1380			drm_rgb_quant_range_selectable(edid);
1381
1382		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1383		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1384			intel_hdmi->has_audio =
1385				intel_hdmi->force_audio == HDMI_AUDIO_ON;
1386
1387		if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1388			intel_hdmi->has_hdmi_sink =
1389				drm_detect_hdmi_monitor(edid);
1390
1391		connected = true;
1392	}
1393
1394	return connected;
1395}
1396
1397static enum drm_connector_status
1398intel_hdmi_detect(struct drm_connector *connector, bool force)
1399{
1400	enum drm_connector_status status;
1401	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1402	struct drm_i915_private *dev_priv = to_i915(connector->dev);
1403	bool live_status = false;
1404	unsigned int try;
1405
1406	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1407		      connector->base.id, connector->name);
1408
1409	intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1410
1411	for (try = 0; !live_status && try < 9; try++) {
1412		if (try)
1413			msleep(10);
1414		live_status = intel_digital_port_connected(dev_priv,
1415				hdmi_to_dig_port(intel_hdmi));
1416	}
1417
1418	if (!live_status) {
1419		DRM_DEBUG_KMS("HDMI live status down\n");
1420		/*
1421		 * Live status register is not reliable on all intel platforms.
1422		 * So consider live_status only for certain platforms, for
1423		 * others, read EDID to determine presence of sink.
1424		 */
1425		if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1426			live_status = true;
1427	}
1428
1429	intel_hdmi_unset_edid(connector);
1430
1431	if (intel_hdmi_set_edid(connector, live_status)) {
1432		struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1433
1434		hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1435		status = connector_status_connected;
1436	} else
1437		status = connector_status_disconnected;
1438
1439	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1440
1441	return status;
1442}
1443
1444static void
1445intel_hdmi_force(struct drm_connector *connector)
1446{
1447	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1448
1449	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1450		      connector->base.id, connector->name);
1451
1452	intel_hdmi_unset_edid(connector);
1453
1454	if (connector->status != connector_status_connected)
1455		return;
1456
1457	intel_hdmi_set_edid(connector, true);
1458	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1459}
1460
1461static int intel_hdmi_get_modes(struct drm_connector *connector)
1462{
1463	struct edid *edid;
 
1464
1465	edid = to_intel_connector(connector)->detect_edid;
1466	if (edid == NULL)
1467		return 0;
1468
1469	return intel_connector_update_modes(connector, edid);
 
1470}
1471
1472static bool
1473intel_hdmi_detect_audio(struct drm_connector *connector)
1474{
1475	bool has_audio = false;
 
1476	struct edid *edid;
 
 
 
 
 
 
 
1477
1478	edid = to_intel_connector(connector)->detect_edid;
1479	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1480		has_audio = drm_detect_monitor_audio(edid);
1481
1482	return has_audio;
1483}
1484
1485static int
1486intel_hdmi_set_property(struct drm_connector *connector,
1487			struct drm_property *property,
1488			uint64_t val)
1489{
1490	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1491	struct intel_digital_port *intel_dig_port =
1492		hdmi_to_dig_port(intel_hdmi);
1493	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1494	int ret;
1495
1496	ret = drm_object_property_set_value(&connector->base, property, val);
1497	if (ret)
1498		return ret;
1499
1500	if (property == dev_priv->force_audio_property) {
1501		enum hdmi_force_audio i = val;
1502		bool has_audio;
1503
1504		if (i == intel_hdmi->force_audio)
1505			return 0;
1506
1507		intel_hdmi->force_audio = i;
1508
1509		if (i == HDMI_AUDIO_AUTO)
1510			has_audio = intel_hdmi_detect_audio(connector);
1511		else
1512			has_audio = (i == HDMI_AUDIO_ON);
1513
1514		if (i == HDMI_AUDIO_OFF_DVI)
1515			intel_hdmi->has_hdmi_sink = 0;
1516
1517		intel_hdmi->has_audio = has_audio;
1518		goto done;
1519	}
1520
1521	if (property == dev_priv->broadcast_rgb_property) {
1522		bool old_auto = intel_hdmi->color_range_auto;
1523		bool old_range = intel_hdmi->limited_color_range;
1524
1525		switch (val) {
1526		case INTEL_BROADCAST_RGB_AUTO:
1527			intel_hdmi->color_range_auto = true;
1528			break;
1529		case INTEL_BROADCAST_RGB_FULL:
1530			intel_hdmi->color_range_auto = false;
1531			intel_hdmi->limited_color_range = false;
1532			break;
1533		case INTEL_BROADCAST_RGB_LIMITED:
1534			intel_hdmi->color_range_auto = false;
1535			intel_hdmi->limited_color_range = true;
1536			break;
1537		default:
1538			return -EINVAL;
1539		}
1540
1541		if (old_auto == intel_hdmi->color_range_auto &&
1542		    old_range == intel_hdmi->limited_color_range)
1543			return 0;
1544
1545		goto done;
1546	}
1547
1548	if (property == connector->dev->mode_config.aspect_ratio_property) {
1549		switch (val) {
1550		case DRM_MODE_PICTURE_ASPECT_NONE:
1551			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1552			break;
1553		case DRM_MODE_PICTURE_ASPECT_4_3:
1554			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1555			break;
1556		case DRM_MODE_PICTURE_ASPECT_16_9:
1557			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1558			break;
1559		default:
1560			return -EINVAL;
1561		}
1562		goto done;
1563	}
1564
1565	return -EINVAL;
1566
1567done:
1568	if (intel_dig_port->base.base.crtc)
1569		intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1570
1571	return 0;
1572}
1573
1574static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1575{
1576	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1577	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1578	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1579
1580	intel_hdmi_prepare(encoder);
1581
1582	intel_hdmi->set_infoframes(&encoder->base,
1583				   intel_crtc->config->has_hdmi_sink,
1584				   adjusted_mode);
1585}
1586
1587static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1588{
1589	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1590	struct intel_hdmi *intel_hdmi = &dport->hdmi;
1591	struct drm_device *dev = encoder->base.dev;
1592	struct drm_i915_private *dev_priv = dev->dev_private;
1593	struct intel_crtc *intel_crtc =
1594		to_intel_crtc(encoder->base.crtc);
1595	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1596	enum dpio_channel port = vlv_dport_to_channel(dport);
1597	int pipe = intel_crtc->pipe;
1598	u32 val;
1599
1600	/* Enable clock channels for this port */
1601	mutex_lock(&dev_priv->sb_lock);
1602	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1603	val = 0;
1604	if (pipe)
1605		val |= (1<<21);
1606	else
1607		val &= ~(1<<21);
1608	val |= 0x001000c4;
1609	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1610
1611	/* HDMI 1.0V-2dB */
1612	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1613	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1614	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1615	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1616	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1617	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1618	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1619	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1620
1621	/* Program lane clock */
1622	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1623	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1624	mutex_unlock(&dev_priv->sb_lock);
1625
1626	intel_hdmi->set_infoframes(&encoder->base,
1627				   intel_crtc->config->has_hdmi_sink,
1628				   adjusted_mode);
1629
1630	g4x_enable_hdmi(encoder);
1631
1632	vlv_wait_port_ready(dev_priv, dport, 0x0);
1633}
1634
1635static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1636{
1637	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1638	struct drm_device *dev = encoder->base.dev;
1639	struct drm_i915_private *dev_priv = dev->dev_private;
1640	struct intel_crtc *intel_crtc =
1641		to_intel_crtc(encoder->base.crtc);
1642	enum dpio_channel port = vlv_dport_to_channel(dport);
1643	int pipe = intel_crtc->pipe;
1644
1645	intel_hdmi_prepare(encoder);
1646
1647	/* Program Tx lane resets to default */
1648	mutex_lock(&dev_priv->sb_lock);
1649	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1650			 DPIO_PCS_TX_LANE2_RESET |
1651			 DPIO_PCS_TX_LANE1_RESET);
1652	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1653			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1654			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1655			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1656			 DPIO_PCS_CLK_SOFT_RESET);
1657
1658	/* Fix up inter-pair skew failure */
1659	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1660	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1661	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1662
1663	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1664	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1665	mutex_unlock(&dev_priv->sb_lock);
1666}
1667
1668static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1669				     bool reset)
1670{
1671	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1672	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1673	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1674	enum pipe pipe = crtc->pipe;
1675	uint32_t val;
1676
1677	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1678	if (reset)
1679		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1680	else
1681		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1682	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1683
1684	if (crtc->config->lane_count > 2) {
1685		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1686		if (reset)
1687			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1688		else
1689			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1690		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1691	}
1692
1693	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1694	val |= CHV_PCS_REQ_SOFTRESET_EN;
1695	if (reset)
1696		val &= ~DPIO_PCS_CLK_SOFT_RESET;
1697	else
1698		val |= DPIO_PCS_CLK_SOFT_RESET;
1699	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1700
1701	if (crtc->config->lane_count > 2) {
1702		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1703		val |= CHV_PCS_REQ_SOFTRESET_EN;
1704		if (reset)
1705			val &= ~DPIO_PCS_CLK_SOFT_RESET;
1706		else
1707			val |= DPIO_PCS_CLK_SOFT_RESET;
1708		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1709	}
1710}
1711
1712static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1713{
1714	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1715	struct drm_device *dev = encoder->base.dev;
1716	struct drm_i915_private *dev_priv = dev->dev_private;
1717	struct intel_crtc *intel_crtc =
1718		to_intel_crtc(encoder->base.crtc);
1719	enum dpio_channel ch = vlv_dport_to_channel(dport);
1720	enum pipe pipe = intel_crtc->pipe;
1721	u32 val;
1722
1723	intel_hdmi_prepare(encoder);
1724
1725	/*
1726	 * Must trick the second common lane into life.
1727	 * Otherwise we can't even access the PLL.
1728	 */
1729	if (ch == DPIO_CH0 && pipe == PIPE_B)
1730		dport->release_cl2_override =
1731			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1732
1733	chv_phy_powergate_lanes(encoder, true, 0x0);
1734
1735	mutex_lock(&dev_priv->sb_lock);
1736
1737	/* Assert data lane reset */
1738	chv_data_lane_soft_reset(encoder, true);
1739
1740	/* program left/right clock distribution */
1741	if (pipe != PIPE_B) {
1742		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1743		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1744		if (ch == DPIO_CH0)
1745			val |= CHV_BUFLEFTENA1_FORCE;
1746		if (ch == DPIO_CH1)
1747			val |= CHV_BUFRIGHTENA1_FORCE;
1748		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1749	} else {
1750		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1751		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1752		if (ch == DPIO_CH0)
1753			val |= CHV_BUFLEFTENA2_FORCE;
1754		if (ch == DPIO_CH1)
1755			val |= CHV_BUFRIGHTENA2_FORCE;
1756		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1757	}
1758
1759	/* program clock channel usage */
1760	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1761	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1762	if (pipe != PIPE_B)
1763		val &= ~CHV_PCS_USEDCLKCHANNEL;
1764	else
1765		val |= CHV_PCS_USEDCLKCHANNEL;
1766	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1767
1768	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1769	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1770	if (pipe != PIPE_B)
1771		val &= ~CHV_PCS_USEDCLKCHANNEL;
1772	else
1773		val |= CHV_PCS_USEDCLKCHANNEL;
1774	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1775
1776	/*
1777	 * This a a bit weird since generally CL
1778	 * matches the pipe, but here we need to
1779	 * pick the CL based on the port.
1780	 */
1781	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1782	if (pipe != PIPE_B)
1783		val &= ~CHV_CMN_USEDCLKCHANNEL;
1784	else
1785		val |= CHV_CMN_USEDCLKCHANNEL;
1786	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1787
1788	mutex_unlock(&dev_priv->sb_lock);
1789}
1790
1791static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1792{
1793	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1794	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1795	u32 val;
1796
1797	mutex_lock(&dev_priv->sb_lock);
1798
1799	/* disable left/right clock distribution */
1800	if (pipe != PIPE_B) {
1801		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1802		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1803		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1804	} else {
1805		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1806		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1807		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1808	}
1809
1810	mutex_unlock(&dev_priv->sb_lock);
1811
1812	/*
1813	 * Leave the power down bit cleared for at least one
1814	 * lane so that chv_powergate_phy_ch() will power
1815	 * on something when the channel is otherwise unused.
1816	 * When the port is off and the override is removed
1817	 * the lanes power down anyway, so otherwise it doesn't
1818	 * really matter what the state of power down bits is
1819	 * after this.
1820	 */
1821	chv_phy_powergate_lanes(encoder, false, 0x0);
1822}
1823
1824static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1825{
1826	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1827	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1828	struct intel_crtc *intel_crtc =
1829		to_intel_crtc(encoder->base.crtc);
1830	enum dpio_channel port = vlv_dport_to_channel(dport);
1831	int pipe = intel_crtc->pipe;
1832
1833	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
1834	mutex_lock(&dev_priv->sb_lock);
1835	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1836	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1837	mutex_unlock(&dev_priv->sb_lock);
1838}
1839
1840static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1841{
1842	struct drm_device *dev = encoder->base.dev;
1843	struct drm_i915_private *dev_priv = dev->dev_private;
1844
1845	mutex_lock(&dev_priv->sb_lock);
1846
1847	/* Assert data lane reset */
1848	chv_data_lane_soft_reset(encoder, true);
1849
1850	mutex_unlock(&dev_priv->sb_lock);
1851}
1852
1853static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1854{
1855	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1856	struct intel_hdmi *intel_hdmi = &dport->hdmi;
1857	struct drm_device *dev = encoder->base.dev;
1858	struct drm_i915_private *dev_priv = dev->dev_private;
1859	struct intel_crtc *intel_crtc =
1860		to_intel_crtc(encoder->base.crtc);
1861	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1862	enum dpio_channel ch = vlv_dport_to_channel(dport);
1863	int pipe = intel_crtc->pipe;
1864	int data, i, stagger;
1865	u32 val;
1866
1867	mutex_lock(&dev_priv->sb_lock);
1868
1869	/* allow hardware to manage TX FIFO reset source */
1870	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1871	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1872	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1873
1874	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1875	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1876	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1877
1878	/* Program Tx latency optimal setting */
1879	for (i = 0; i < 4; i++) {
1880		/* Set the upar bit */
1881		data = (i == 1) ? 0x0 : 0x1;
1882		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1883				data << DPIO_UPAR_SHIFT);
1884	}
1885
1886	/* Data lane stagger programming */
1887	if (intel_crtc->config->port_clock > 270000)
1888		stagger = 0x18;
1889	else if (intel_crtc->config->port_clock > 135000)
1890		stagger = 0xd;
1891	else if (intel_crtc->config->port_clock > 67500)
1892		stagger = 0x7;
1893	else if (intel_crtc->config->port_clock > 33750)
1894		stagger = 0x4;
1895	else
1896		stagger = 0x2;
1897
1898	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1899	val |= DPIO_TX2_STAGGER_MASK(0x1f);
1900	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1901
1902	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1903	val |= DPIO_TX2_STAGGER_MASK(0x1f);
1904	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1905
1906	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1907		       DPIO_LANESTAGGER_STRAP(stagger) |
1908		       DPIO_LANESTAGGER_STRAP_OVRD |
1909		       DPIO_TX1_STAGGER_MASK(0x1f) |
1910		       DPIO_TX1_STAGGER_MULT(6) |
1911		       DPIO_TX2_STAGGER_MULT(0));
1912
1913	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1914		       DPIO_LANESTAGGER_STRAP(stagger) |
1915		       DPIO_LANESTAGGER_STRAP_OVRD |
1916		       DPIO_TX1_STAGGER_MASK(0x1f) |
1917		       DPIO_TX1_STAGGER_MULT(7) |
1918		       DPIO_TX2_STAGGER_MULT(5));
1919
1920	/* Deassert data lane reset */
1921	chv_data_lane_soft_reset(encoder, false);
1922
1923	/* Clear calc init */
1924	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1925	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1926	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1927	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1928	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1929
1930	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1931	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1932	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1933	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1934	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1935
1936	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1937	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1938	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1939	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1940
1941	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1942	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1943	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1944	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1945
1946	/* FIXME: Program the support xxx V-dB */
1947	/* Use 800mV-0dB */
1948	for (i = 0; i < 4; i++) {
1949		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1950		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1951		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1952		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1953	}
1954
1955	for (i = 0; i < 4; i++) {
1956		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1957
1958		val &= ~DPIO_SWING_MARGIN000_MASK;
1959		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1960
1961		/*
1962		 * Supposedly this value shouldn't matter when unique transition
1963		 * scale is disabled, but in fact it does matter. Let's just
1964		 * always program the same value and hope it's OK.
1965		 */
1966		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1967		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1968
1969		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1970	}
1971
1972	/*
1973	 * The document said it needs to set bit 27 for ch0 and bit 26
1974	 * for ch1. Might be a typo in the doc.
1975	 * For now, for this unique transition scale selection, set bit
1976	 * 27 for ch0 and ch1.
1977	 */
1978	for (i = 0; i < 4; i++) {
1979		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1980		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1981		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1982	}
1983
1984	/* Start swing calculation */
1985	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1986	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1987	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1988
1989	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1990	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1991	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1992
1993	mutex_unlock(&dev_priv->sb_lock);
1994
1995	intel_hdmi->set_infoframes(&encoder->base,
1996				   intel_crtc->config->has_hdmi_sink,
1997				   adjusted_mode);
1998
1999	g4x_enable_hdmi(encoder);
2000
2001	vlv_wait_port_ready(dev_priv, dport, 0x0);
2002
2003	/* Second common lane will stay alive on its own now */
2004	if (dport->release_cl2_override) {
2005		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2006		dport->release_cl2_override = false;
2007	}
2008}
2009
2010static void intel_hdmi_destroy(struct drm_connector *connector)
2011{
2012	kfree(to_intel_connector(connector)->detect_edid);
2013	drm_connector_cleanup(connector);
2014	kfree(connector);
2015}
2016
 
 
 
 
 
 
 
 
2017static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2018	.dpms = drm_atomic_helper_connector_dpms,
2019	.detect = intel_hdmi_detect,
2020	.force = intel_hdmi_force,
2021	.fill_modes = drm_helper_probe_single_connector_modes,
2022	.set_property = intel_hdmi_set_property,
2023	.atomic_get_property = intel_connector_atomic_get_property,
2024	.destroy = intel_hdmi_destroy,
2025	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2026	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2027};
2028
2029static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2030	.get_modes = intel_hdmi_get_modes,
2031	.mode_valid = intel_hdmi_mode_valid,
2032	.best_encoder = intel_best_encoder,
2033};
2034
2035static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2036	.destroy = intel_encoder_destroy,
2037};
2038
2039static void
2040intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2041{
2042	intel_attach_force_audio_property(connector);
2043	intel_attach_broadcast_rgb_property(connector);
2044	intel_hdmi->color_range_auto = true;
2045	intel_attach_aspect_ratio_property(connector);
2046	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2047}
2048
2049void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2050			       struct intel_connector *intel_connector)
2051{
2052	struct drm_connector *connector = &intel_connector->base;
2053	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2054	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2055	struct drm_device *dev = intel_encoder->base.dev;
2056	struct drm_i915_private *dev_priv = dev->dev_private;
2057	enum port port = intel_dig_port->port;
2058	uint8_t alternate_ddc_pin;
 
 
 
 
 
 
2059
2060	if (WARN(intel_dig_port->max_lanes < 4,
2061		 "Not enough lanes (%d) for HDMI on port %c\n",
2062		 intel_dig_port->max_lanes, port_name(port)))
2063		return;
 
 
 
 
 
2064
 
2065	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2066			   DRM_MODE_CONNECTOR_HDMIA);
2067	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2068
2069	connector->interlace_allowed = 1;
 
 
 
2070	connector->doublescan_allowed = 0;
2071	connector->stereo_allowed = 1;
2072
2073	switch (port) {
2074	case PORT_B:
2075		if (IS_BROXTON(dev_priv))
2076			intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2077		else
2078			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2079		/*
2080		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2081		 * interrupts to check the external panel connection.
2082		 */
2083		if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2084			intel_encoder->hpd_pin = HPD_PORT_A;
2085		else
2086			intel_encoder->hpd_pin = HPD_PORT_B;
2087		break;
2088	case PORT_C:
2089		if (IS_BROXTON(dev_priv))
2090			intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2091		else
2092			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2093		intel_encoder->hpd_pin = HPD_PORT_C;
2094		break;
2095	case PORT_D:
2096		if (WARN_ON(IS_BROXTON(dev_priv)))
2097			intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2098		else if (IS_CHERRYVIEW(dev_priv))
2099			intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2100		else
2101			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2102		intel_encoder->hpd_pin = HPD_PORT_D;
2103		break;
2104	case PORT_E:
2105		/* On SKL PORT E doesn't have seperate GMBUS pin
2106		 *  We rely on VBT to set a proper alternate GMBUS pin. */
2107		alternate_ddc_pin =
2108			dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2109		switch (alternate_ddc_pin) {
2110		case DDC_PIN_B:
2111			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2112			break;
2113		case DDC_PIN_C:
2114			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2115			break;
2116		case DDC_PIN_D:
2117			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2118			break;
2119		default:
2120			MISSING_CASE(alternate_ddc_pin);
2121		}
2122		intel_encoder->hpd_pin = HPD_PORT_E;
2123		break;
2124	case PORT_A:
2125		intel_encoder->hpd_pin = HPD_PORT_A;
2126		/* Internal port only for eDP. */
2127	default:
2128		BUG();
2129	}
2130
2131	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2132		intel_hdmi->write_infoframe = vlv_write_infoframe;
2133		intel_hdmi->set_infoframes = vlv_set_infoframes;
2134		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2135	} else if (IS_G4X(dev)) {
2136		intel_hdmi->write_infoframe = g4x_write_infoframe;
2137		intel_hdmi->set_infoframes = g4x_set_infoframes;
2138		intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2139	} else if (HAS_DDI(dev)) {
2140		intel_hdmi->write_infoframe = hsw_write_infoframe;
2141		intel_hdmi->set_infoframes = hsw_set_infoframes;
2142		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2143	} else if (HAS_PCH_IBX(dev)) {
2144		intel_hdmi->write_infoframe = ibx_write_infoframe;
2145		intel_hdmi->set_infoframes = ibx_set_infoframes;
2146		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2147	} else {
2148		intel_hdmi->write_infoframe = cpt_write_infoframe;
2149		intel_hdmi->set_infoframes = cpt_set_infoframes;
2150		intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2151	}
2152
2153	if (HAS_DDI(dev))
2154		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2155	else
2156		intel_connector->get_hw_state = intel_connector_get_hw_state;
2157	intel_connector->unregister = intel_connector_unregister;
 
2158
2159	intel_hdmi_add_properties(intel_hdmi, connector);
2160
2161	intel_connector_attach_encoder(intel_connector, intel_encoder);
2162	drm_connector_register(connector);
2163	intel_hdmi->attached_connector = intel_connector;
2164
2165	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2166	 * 0xd.  Failure to do so will result in spurious interrupts being
2167	 * generated on the port when a cable is not attached.
2168	 */
2169	if (IS_G4X(dev) && !IS_GM45(dev)) {
2170		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2171		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2172	}
2173}
2174
2175void intel_hdmi_init(struct drm_device *dev,
2176		     i915_reg_t hdmi_reg, enum port port)
2177{
2178	struct intel_digital_port *intel_dig_port;
2179	struct intel_encoder *intel_encoder;
2180	struct intel_connector *intel_connector;
2181
2182	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2183	if (!intel_dig_port)
2184		return;
2185
2186	intel_connector = intel_connector_alloc();
2187	if (!intel_connector) {
2188		kfree(intel_dig_port);
2189		return;
2190	}
2191
2192	intel_encoder = &intel_dig_port->base;
2193
2194	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2195			 DRM_MODE_ENCODER_TMDS, NULL);
2196
2197	intel_encoder->compute_config = intel_hdmi_compute_config;
2198	if (HAS_PCH_SPLIT(dev)) {
2199		intel_encoder->disable = pch_disable_hdmi;
2200		intel_encoder->post_disable = pch_post_disable_hdmi;
2201	} else {
2202		intel_encoder->disable = g4x_disable_hdmi;
2203	}
2204	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2205	intel_encoder->get_config = intel_hdmi_get_config;
2206	if (IS_CHERRYVIEW(dev)) {
2207		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2208		intel_encoder->pre_enable = chv_hdmi_pre_enable;
2209		intel_encoder->enable = vlv_enable_hdmi;
2210		intel_encoder->post_disable = chv_hdmi_post_disable;
2211		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2212	} else if (IS_VALLEYVIEW(dev)) {
2213		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2214		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2215		intel_encoder->enable = vlv_enable_hdmi;
2216		intel_encoder->post_disable = vlv_hdmi_post_disable;
2217	} else {
2218		intel_encoder->pre_enable = intel_hdmi_pre_enable;
2219		if (HAS_PCH_CPT(dev))
2220			intel_encoder->enable = cpt_enable_hdmi;
2221		else if (HAS_PCH_IBX(dev))
2222			intel_encoder->enable = ibx_enable_hdmi;
2223		else
2224			intel_encoder->enable = g4x_enable_hdmi;
2225	}
2226
2227	intel_encoder->type = INTEL_OUTPUT_HDMI;
2228	if (IS_CHERRYVIEW(dev)) {
2229		if (port == PORT_D)
2230			intel_encoder->crtc_mask = 1 << 2;
2231		else
2232			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2233	} else {
2234		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2235	}
2236	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2237	/*
2238	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2239	 * to work on real hardware. And since g4x can send infoframes to
2240	 * only one port anyway, nothing is lost by allowing it.
2241	 */
2242	if (IS_G4X(dev))
2243		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2244
2245	intel_dig_port->port = port;
2246	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2247	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2248	intel_dig_port->max_lanes = 4;
2249
2250	intel_hdmi_init_connector(intel_dig_port, intel_connector);
2251}