Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm_atomic_helper.h>
28#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h>
30#include <drm/i915_drm.h>
31#include <drm/drm_panel.h>
32#include <drm/drm_mipi_dsi.h>
33#include <linux/slab.h>
34#include <linux/gpio/consumer.h>
35#include "i915_drv.h"
36#include "intel_drv.h"
37#include "intel_dsi.h"
38
39static const struct {
40 u16 panel_id;
41 struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
42} intel_dsi_drivers[] = {
43 {
44 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
45 .init = vbt_panel_init,
46 },
47};
48
49static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
50{
51 struct drm_encoder *encoder = &intel_dsi->base.base;
52 struct drm_device *dev = encoder->dev;
53 struct drm_i915_private *dev_priv = dev->dev_private;
54 u32 mask;
55
56 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
57 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
58
59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
60 DRM_ERROR("DPI FIFOs are not empty\n");
61}
62
63static void write_data(struct drm_i915_private *dev_priv,
64 i915_reg_t reg,
65 const u8 *data, u32 len)
66{
67 u32 i, j;
68
69 for (i = 0; i < len; i += 4) {
70 u32 val = 0;
71
72 for (j = 0; j < min_t(u32, len - i, 4); j++)
73 val |= *data++ << 8 * j;
74
75 I915_WRITE(reg, val);
76 }
77}
78
79static void read_data(struct drm_i915_private *dev_priv,
80 i915_reg_t reg,
81 u8 *data, u32 len)
82{
83 u32 i, j;
84
85 for (i = 0; i < len; i += 4) {
86 u32 val = I915_READ(reg);
87
88 for (j = 0; j < min_t(u32, len - i, 4); j++)
89 *data++ = val >> 8 * j;
90 }
91}
92
93static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
94 const struct mipi_dsi_msg *msg)
95{
96 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
97 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
98 struct drm_i915_private *dev_priv = dev->dev_private;
99 enum port port = intel_dsi_host->port;
100 struct mipi_dsi_packet packet;
101 ssize_t ret;
102 const u8 *header, *data;
103 i915_reg_t data_reg, ctrl_reg;
104 u32 data_mask, ctrl_mask;
105
106 ret = mipi_dsi_create_packet(&packet, msg);
107 if (ret < 0)
108 return ret;
109
110 header = packet.header;
111 data = packet.payload;
112
113 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
114 data_reg = MIPI_LP_GEN_DATA(port);
115 data_mask = LP_DATA_FIFO_FULL;
116 ctrl_reg = MIPI_LP_GEN_CTRL(port);
117 ctrl_mask = LP_CTRL_FIFO_FULL;
118 } else {
119 data_reg = MIPI_HS_GEN_DATA(port);
120 data_mask = HS_DATA_FIFO_FULL;
121 ctrl_reg = MIPI_HS_GEN_CTRL(port);
122 ctrl_mask = HS_CTRL_FIFO_FULL;
123 }
124
125 /* note: this is never true for reads */
126 if (packet.payload_length) {
127
128 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
129 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
130
131 write_data(dev_priv, data_reg, packet.payload,
132 packet.payload_length);
133 }
134
135 if (msg->rx_len) {
136 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
137 }
138
139 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
140 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
141 }
142
143 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
144
145 /* ->rx_len is set only for reads */
146 if (msg->rx_len) {
147 data_mask = GEN_READ_DATA_AVAIL;
148 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
149 DRM_ERROR("Timeout waiting for read data.\n");
150
151 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
152 }
153
154 /* XXX: fix for reads and writes */
155 return 4 + packet.payload_length;
156}
157
158static int intel_dsi_host_attach(struct mipi_dsi_host *host,
159 struct mipi_dsi_device *dsi)
160{
161 return 0;
162}
163
164static int intel_dsi_host_detach(struct mipi_dsi_host *host,
165 struct mipi_dsi_device *dsi)
166{
167 return 0;
168}
169
170static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
171 .attach = intel_dsi_host_attach,
172 .detach = intel_dsi_host_detach,
173 .transfer = intel_dsi_host_transfer,
174};
175
176static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
177 enum port port)
178{
179 struct intel_dsi_host *host;
180 struct mipi_dsi_device *device;
181
182 host = kzalloc(sizeof(*host), GFP_KERNEL);
183 if (!host)
184 return NULL;
185
186 host->base.ops = &intel_dsi_host_ops;
187 host->intel_dsi = intel_dsi;
188 host->port = port;
189
190 /*
191 * We should call mipi_dsi_host_register(&host->base) here, but we don't
192 * have a host->dev, and we don't have OF stuff either. So just use the
193 * dsi framework as a library and hope for the best. Create the dsi
194 * devices by ourselves here too. Need to be careful though, because we
195 * don't initialize any of the driver model devices here.
196 */
197 device = kzalloc(sizeof(*device), GFP_KERNEL);
198 if (!device) {
199 kfree(host);
200 return NULL;
201 }
202
203 device->host = &host->base;
204 host->device = device;
205
206 return host;
207}
208
209/*
210 * send a video mode command
211 *
212 * XXX: commands with data in MIPI_DPI_DATA?
213 */
214static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
215 enum port port)
216{
217 struct drm_encoder *encoder = &intel_dsi->base.base;
218 struct drm_device *dev = encoder->dev;
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 u32 mask;
221
222 /* XXX: pipe, hs */
223 if (hs)
224 cmd &= ~DPI_LP_MODE;
225 else
226 cmd |= DPI_LP_MODE;
227
228 /* clear bit */
229 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
230
231 /* XXX: old code skips write if control unchanged */
232 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
233 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
234
235 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
236
237 mask = SPL_PKT_SENT_INTERRUPT;
238 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
239 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
240
241 return 0;
242}
243
244static void band_gap_reset(struct drm_i915_private *dev_priv)
245{
246 mutex_lock(&dev_priv->sb_lock);
247
248 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
249 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
250 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
251 udelay(150);
252 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
253 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
254
255 mutex_unlock(&dev_priv->sb_lock);
256}
257
258static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
259{
260 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
261}
262
263static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
264{
265 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
266}
267
268static bool intel_dsi_compute_config(struct intel_encoder *encoder,
269 struct intel_crtc_state *pipe_config)
270{
271 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
272 base);
273 struct intel_connector *intel_connector = intel_dsi->attached_connector;
274 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
275 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
276
277 DRM_DEBUG_KMS("\n");
278
279 pipe_config->has_dsi_encoder = true;
280
281 if (fixed_mode)
282 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
283
284 /* DSI uses short packets for sync events, so clear mode flags for DSI */
285 adjusted_mode->flags = 0;
286
287 return true;
288}
289
290static void bxt_dsi_device_ready(struct intel_encoder *encoder)
291{
292 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
293 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
294 enum port port;
295 u32 val;
296
297 DRM_DEBUG_KMS("\n");
298
299 /* Exit Low power state in 4 steps*/
300 for_each_dsi_port(port, intel_dsi->ports) {
301
302 /* 1. Enable MIPI PHY transparent latch */
303 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
304 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
305 usleep_range(2000, 2500);
306
307 /* 2. Enter ULPS */
308 val = I915_READ(MIPI_DEVICE_READY(port));
309 val &= ~ULPS_STATE_MASK;
310 val |= (ULPS_STATE_ENTER | DEVICE_READY);
311 I915_WRITE(MIPI_DEVICE_READY(port), val);
312 usleep_range(2, 3);
313
314 /* 3. Exit ULPS */
315 val = I915_READ(MIPI_DEVICE_READY(port));
316 val &= ~ULPS_STATE_MASK;
317 val |= (ULPS_STATE_EXIT | DEVICE_READY);
318 I915_WRITE(MIPI_DEVICE_READY(port), val);
319 usleep_range(1000, 1500);
320
321 /* Clear ULPS and set device ready */
322 val = I915_READ(MIPI_DEVICE_READY(port));
323 val &= ~ULPS_STATE_MASK;
324 val |= DEVICE_READY;
325 I915_WRITE(MIPI_DEVICE_READY(port), val);
326 }
327}
328
329static void vlv_dsi_device_ready(struct intel_encoder *encoder)
330{
331 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
333 enum port port;
334 u32 val;
335
336 DRM_DEBUG_KMS("\n");
337
338 mutex_lock(&dev_priv->sb_lock);
339 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
340 * needed everytime after power gate */
341 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
342 mutex_unlock(&dev_priv->sb_lock);
343
344 /* bandgap reset is needed after everytime we do power gate */
345 band_gap_reset(dev_priv);
346
347 for_each_dsi_port(port, intel_dsi->ports) {
348
349 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
350 usleep_range(2500, 3000);
351
352 /* Enable MIPI PHY transparent latch
353 * Common bit for both MIPI Port A & MIPI Port C
354 * No similar bit in MIPI Port C reg
355 */
356 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
357 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
358 usleep_range(1000, 1500);
359
360 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
361 usleep_range(2500, 3000);
362
363 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
364 usleep_range(2500, 3000);
365 }
366}
367
368static void intel_dsi_device_ready(struct intel_encoder *encoder)
369{
370 struct drm_device *dev = encoder->base.dev;
371
372 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
373 vlv_dsi_device_ready(encoder);
374 else if (IS_BROXTON(dev))
375 bxt_dsi_device_ready(encoder);
376}
377
378static void intel_dsi_port_enable(struct intel_encoder *encoder)
379{
380 struct drm_device *dev = encoder->base.dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
383 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
384 enum port port;
385
386 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
387 u32 temp;
388
389 temp = I915_READ(VLV_CHICKEN_3);
390 temp &= ~PIXEL_OVERLAP_CNT_MASK |
391 intel_dsi->pixel_overlap <<
392 PIXEL_OVERLAP_CNT_SHIFT;
393 I915_WRITE(VLV_CHICKEN_3, temp);
394 }
395
396 for_each_dsi_port(port, intel_dsi->ports) {
397 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
398 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
399 u32 temp;
400
401 temp = I915_READ(port_ctrl);
402
403 temp &= ~LANE_CONFIGURATION_MASK;
404 temp &= ~DUAL_LINK_MODE_MASK;
405
406 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
407 temp |= (intel_dsi->dual_link - 1)
408 << DUAL_LINK_MODE_SHIFT;
409 temp |= intel_crtc->pipe ?
410 LANE_CONFIGURATION_DUAL_LINK_B :
411 LANE_CONFIGURATION_DUAL_LINK_A;
412 }
413 /* assert ip_tg_enable signal */
414 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
415 POSTING_READ(port_ctrl);
416 }
417}
418
419static void intel_dsi_port_disable(struct intel_encoder *encoder)
420{
421 struct drm_device *dev = encoder->base.dev;
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
424 enum port port;
425
426 for_each_dsi_port(port, intel_dsi->ports) {
427 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
428 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
429 u32 temp;
430
431 /* de-assert ip_tg_enable signal */
432 temp = I915_READ(port_ctrl);
433 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
434 POSTING_READ(port_ctrl);
435 }
436}
437
438static void intel_dsi_enable(struct intel_encoder *encoder)
439{
440 struct drm_device *dev = encoder->base.dev;
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
443 enum port port;
444
445 DRM_DEBUG_KMS("\n");
446
447 if (is_cmd_mode(intel_dsi)) {
448 for_each_dsi_port(port, intel_dsi->ports)
449 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
450 } else {
451 msleep(20); /* XXX */
452 for_each_dsi_port(port, intel_dsi->ports)
453 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
454 msleep(100);
455
456 drm_panel_enable(intel_dsi->panel);
457
458 for_each_dsi_port(port, intel_dsi->ports)
459 wait_for_dsi_fifo_empty(intel_dsi, port);
460
461 intel_dsi_port_enable(encoder);
462 }
463
464 intel_panel_enable_backlight(intel_dsi->attached_connector);
465}
466
467static void intel_dsi_prepare(struct intel_encoder *intel_encoder);
468
469static void intel_dsi_pre_enable(struct intel_encoder *encoder)
470{
471 struct drm_device *dev = encoder->base.dev;
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
474 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
475 enum pipe pipe = intel_crtc->pipe;
476 enum port port;
477 u32 tmp;
478
479 DRM_DEBUG_KMS("\n");
480
481 intel_enable_dsi_pll(encoder);
482 intel_dsi_prepare(encoder);
483
484 /* Panel Enable over CRC PMIC */
485 if (intel_dsi->gpio_panel)
486 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
487
488 msleep(intel_dsi->panel_on_delay);
489
490 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
491 /*
492 * Disable DPOunit clock gating, can stall pipe
493 * and we need DPLL REFA always enabled
494 */
495 tmp = I915_READ(DPLL(pipe));
496 tmp |= DPLL_REF_CLK_ENABLE_VLV;
497 I915_WRITE(DPLL(pipe), tmp);
498
499 /* update the hw state for DPLL */
500 intel_crtc->config->dpll_hw_state.dpll =
501 DPLL_INTEGRATED_REF_CLK_VLV |
502 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
503
504 tmp = I915_READ(DSPCLK_GATE_D);
505 tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
506 I915_WRITE(DSPCLK_GATE_D, tmp);
507 }
508
509 /* put device in ready state */
510 intel_dsi_device_ready(encoder);
511
512 drm_panel_prepare(intel_dsi->panel);
513
514 for_each_dsi_port(port, intel_dsi->ports)
515 wait_for_dsi_fifo_empty(intel_dsi, port);
516
517 /* Enable port in pre-enable phase itself because as per hw team
518 * recommendation, port should be enabled befor plane & pipe */
519 intel_dsi_enable(encoder);
520}
521
522static void intel_dsi_enable_nop(struct intel_encoder *encoder)
523{
524 DRM_DEBUG_KMS("\n");
525
526 /* for DSI port enable has to be done before pipe
527 * and plane enable, so port enable is done in
528 * pre_enable phase itself unlike other encoders
529 */
530}
531
532static void intel_dsi_pre_disable(struct intel_encoder *encoder)
533{
534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
535 enum port port;
536
537 DRM_DEBUG_KMS("\n");
538
539 intel_panel_disable_backlight(intel_dsi->attached_connector);
540
541 if (is_vid_mode(intel_dsi)) {
542 /* Send Shutdown command to the panel in LP mode */
543 for_each_dsi_port(port, intel_dsi->ports)
544 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
545 msleep(10);
546 }
547}
548
549static void intel_dsi_disable(struct intel_encoder *encoder)
550{
551 struct drm_device *dev = encoder->base.dev;
552 struct drm_i915_private *dev_priv = dev->dev_private;
553 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
554 enum port port;
555 u32 temp;
556
557 DRM_DEBUG_KMS("\n");
558
559 if (is_vid_mode(intel_dsi)) {
560 for_each_dsi_port(port, intel_dsi->ports)
561 wait_for_dsi_fifo_empty(intel_dsi, port);
562
563 intel_dsi_port_disable(encoder);
564 msleep(2);
565 }
566
567 for_each_dsi_port(port, intel_dsi->ports) {
568 /* Panel commands can be sent when clock is in LP11 */
569 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
570
571 intel_dsi_reset_clocks(encoder, port);
572 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
573
574 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
575 temp &= ~VID_MODE_FORMAT_MASK;
576 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
577
578 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
579 }
580 /* if disable packets are sent before sending shutdown packet then in
581 * some next enable sequence send turn on packet error is observed */
582 drm_panel_disable(intel_dsi->panel);
583
584 for_each_dsi_port(port, intel_dsi->ports)
585 wait_for_dsi_fifo_empty(intel_dsi, port);
586}
587
588static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
589{
590 struct drm_device *dev = encoder->base.dev;
591 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
592 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
593 enum port port;
594
595 DRM_DEBUG_KMS("\n");
596 for_each_dsi_port(port, intel_dsi->ports) {
597 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
598 i915_reg_t port_ctrl = IS_BROXTON(dev) ?
599 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
600 u32 val;
601
602 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
603 ULPS_STATE_ENTER);
604 usleep_range(2000, 2500);
605
606 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
607 ULPS_STATE_EXIT);
608 usleep_range(2000, 2500);
609
610 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
611 ULPS_STATE_ENTER);
612 usleep_range(2000, 2500);
613
614 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
615 * only. MIPI Port C has no similar bit for checking
616 */
617 if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
618 == 0x00000), 30))
619 DRM_ERROR("DSI LP not going Low\n");
620
621 /* Disable MIPI PHY transparent latch */
622 val = I915_READ(port_ctrl);
623 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
624 usleep_range(1000, 1500);
625
626 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
627 usleep_range(2000, 2500);
628 }
629
630 intel_disable_dsi_pll(encoder);
631}
632
633static void intel_dsi_post_disable(struct intel_encoder *encoder)
634{
635 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
636 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
637
638 DRM_DEBUG_KMS("\n");
639
640 intel_dsi_disable(encoder);
641
642 intel_dsi_clear_device_ready(encoder);
643
644 if (!IS_BROXTON(dev_priv)) {
645 u32 val;
646
647 val = I915_READ(DSPCLK_GATE_D);
648 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
649 I915_WRITE(DSPCLK_GATE_D, val);
650 }
651
652 drm_panel_unprepare(intel_dsi->panel);
653
654 msleep(intel_dsi->panel_off_delay);
655 msleep(intel_dsi->panel_pwr_cycle_delay);
656
657 /* Panel Disable over CRC PMIC */
658 if (intel_dsi->gpio_panel)
659 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
660}
661
662static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
663 enum pipe *pipe)
664{
665 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
666 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
667 struct drm_device *dev = encoder->base.dev;
668 enum intel_display_power_domain power_domain;
669 enum port port;
670 bool ret;
671
672 DRM_DEBUG_KMS("\n");
673
674 power_domain = intel_display_port_power_domain(encoder);
675 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
676 return false;
677
678 ret = false;
679
680 /* XXX: this only works for one DSI output */
681 for_each_dsi_port(port, intel_dsi->ports) {
682 i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
683 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
684 u32 dpi_enabled, func;
685
686 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
687 dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
688
689 /* Due to some hardware limitations on BYT, MIPI Port C DPI
690 * Enable bit does not get set. To check whether DSI Port C
691 * was enabled in BIOS, check the Pipe B enable bit
692 */
693 if (IS_VALLEYVIEW(dev) && port == PORT_C)
694 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
695 PIPECONF_ENABLE;
696
697 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
698 if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
699 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
700 ret = true;
701
702 goto out;
703 }
704 }
705 }
706out:
707 intel_display_power_put(dev_priv, power_domain);
708
709 return ret;
710}
711
712static void intel_dsi_get_config(struct intel_encoder *encoder,
713 struct intel_crtc_state *pipe_config)
714{
715 u32 pclk;
716 DRM_DEBUG_KMS("\n");
717
718 pipe_config->has_dsi_encoder = true;
719
720 /*
721 * DPLL_MD is not used in case of DSI, reading will get some default value
722 * set dpll_md = 0
723 */
724 pipe_config->dpll_hw_state.dpll_md = 0;
725
726 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp);
727 if (!pclk)
728 return;
729
730 pipe_config->base.adjusted_mode.crtc_clock = pclk;
731 pipe_config->port_clock = pclk;
732}
733
734static enum drm_mode_status
735intel_dsi_mode_valid(struct drm_connector *connector,
736 struct drm_display_mode *mode)
737{
738 struct intel_connector *intel_connector = to_intel_connector(connector);
739 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
740 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
741
742 DRM_DEBUG_KMS("\n");
743
744 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
745 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
746 return MODE_NO_DBLESCAN;
747 }
748
749 if (fixed_mode) {
750 if (mode->hdisplay > fixed_mode->hdisplay)
751 return MODE_PANEL;
752 if (mode->vdisplay > fixed_mode->vdisplay)
753 return MODE_PANEL;
754 if (fixed_mode->clock > max_dotclk)
755 return MODE_CLOCK_HIGH;
756 }
757
758 return MODE_OK;
759}
760
761/* return txclkesc cycles in terms of divider and duration in us */
762static u16 txclkesc(u32 divider, unsigned int us)
763{
764 switch (divider) {
765 case ESCAPE_CLOCK_DIVIDER_1:
766 default:
767 return 20 * us;
768 case ESCAPE_CLOCK_DIVIDER_2:
769 return 10 * us;
770 case ESCAPE_CLOCK_DIVIDER_4:
771 return 5 * us;
772 }
773}
774
775/* return pixels in terms of txbyteclkhs */
776static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
777 u16 burst_mode_ratio)
778{
779 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
780 8 * 100), lane_count);
781}
782
783static void set_dsi_timings(struct drm_encoder *encoder,
784 const struct drm_display_mode *adjusted_mode)
785{
786 struct drm_device *dev = encoder->dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
789 enum port port;
790 unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
791 unsigned int lane_count = intel_dsi->lane_count;
792
793 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
794
795 hactive = adjusted_mode->crtc_hdisplay;
796 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
797 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
798 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
799
800 if (intel_dsi->dual_link) {
801 hactive /= 2;
802 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
803 hactive += intel_dsi->pixel_overlap;
804 hfp /= 2;
805 hsync /= 2;
806 hbp /= 2;
807 }
808
809 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
810 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
811 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
812
813 /* horizontal values are in terms of high speed byte clock */
814 hactive = txbyteclkhs(hactive, bpp, lane_count,
815 intel_dsi->burst_mode_ratio);
816 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
817 hsync = txbyteclkhs(hsync, bpp, lane_count,
818 intel_dsi->burst_mode_ratio);
819 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
820
821 for_each_dsi_port(port, intel_dsi->ports) {
822 if (IS_BROXTON(dev)) {
823 /*
824 * Program hdisplay and vdisplay on MIPI transcoder.
825 * This is different from calculated hactive and
826 * vactive, as they are calculated per channel basis,
827 * whereas these values should be based on resolution.
828 */
829 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
830 adjusted_mode->crtc_hdisplay);
831 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
832 adjusted_mode->crtc_vdisplay);
833 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
834 adjusted_mode->crtc_vtotal);
835 }
836
837 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
838 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
839
840 /* meaningful for video mode non-burst sync pulse mode only,
841 * can be zero for non-burst sync events and burst modes */
842 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
843 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
844
845 /* vertical values are in terms of lines */
846 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
847 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
848 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
849 }
850}
851
852static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
853{
854 struct drm_encoder *encoder = &intel_encoder->base;
855 struct drm_device *dev = encoder->dev;
856 struct drm_i915_private *dev_priv = dev->dev_private;
857 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
858 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
859 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
860 enum port port;
861 unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
862 u32 val, tmp;
863 u16 mode_hdisplay;
864
865 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
866
867 mode_hdisplay = adjusted_mode->crtc_hdisplay;
868
869 if (intel_dsi->dual_link) {
870 mode_hdisplay /= 2;
871 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
872 mode_hdisplay += intel_dsi->pixel_overlap;
873 }
874
875 for_each_dsi_port(port, intel_dsi->ports) {
876 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
877 /*
878 * escape clock divider, 20MHz, shared for A and C.
879 * device ready must be off when doing this! txclkesc?
880 */
881 tmp = I915_READ(MIPI_CTRL(PORT_A));
882 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
883 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
884 ESCAPE_CLOCK_DIVIDER_1);
885
886 /* read request priority is per pipe */
887 tmp = I915_READ(MIPI_CTRL(port));
888 tmp &= ~READ_REQUEST_PRIORITY_MASK;
889 I915_WRITE(MIPI_CTRL(port), tmp |
890 READ_REQUEST_PRIORITY_HIGH);
891 } else if (IS_BROXTON(dev)) {
892 enum pipe pipe = intel_crtc->pipe;
893
894 tmp = I915_READ(MIPI_CTRL(port));
895 tmp &= ~BXT_PIPE_SELECT_MASK;
896
897 tmp |= BXT_PIPE_SELECT(pipe);
898 I915_WRITE(MIPI_CTRL(port), tmp);
899 }
900
901 /* XXX: why here, why like this? handling in irq handler?! */
902 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
903 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
904
905 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
906
907 I915_WRITE(MIPI_DPI_RESOLUTION(port),
908 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
909 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
910 }
911
912 set_dsi_timings(encoder, adjusted_mode);
913
914 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
915 if (is_cmd_mode(intel_dsi)) {
916 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
917 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
918 } else {
919 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
920
921 /* XXX: cross-check bpp vs. pixel format? */
922 val |= intel_dsi->pixel_format;
923 }
924
925 tmp = 0;
926 if (intel_dsi->eotp_pkt == 0)
927 tmp |= EOT_DISABLE;
928 if (intel_dsi->clock_stop)
929 tmp |= CLOCKSTOP;
930
931 for_each_dsi_port(port, intel_dsi->ports) {
932 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
933
934 /* timeouts for recovery. one frame IIUC. if counter expires,
935 * EOT and stop state. */
936
937 /*
938 * In burst mode, value greater than one DPI line Time in byte
939 * clock (txbyteclkhs) To timeout this timer 1+ of the above
940 * said value is recommended.
941 *
942 * In non-burst mode, Value greater than one DPI frame time in
943 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
944 * said value is recommended.
945 *
946 * In DBI only mode, value greater than one DBI frame time in
947 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
948 * said value is recommended.
949 */
950
951 if (is_vid_mode(intel_dsi) &&
952 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
953 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
954 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
955 intel_dsi->lane_count,
956 intel_dsi->burst_mode_ratio) + 1);
957 } else {
958 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
959 txbyteclkhs(adjusted_mode->crtc_vtotal *
960 adjusted_mode->crtc_htotal,
961 bpp, intel_dsi->lane_count,
962 intel_dsi->burst_mode_ratio) + 1);
963 }
964 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
965 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
966 intel_dsi->turn_arnd_val);
967 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
968 intel_dsi->rst_timer_val);
969
970 /* dphy stuff */
971
972 /* in terms of low power clock */
973 I915_WRITE(MIPI_INIT_COUNT(port),
974 txclkesc(intel_dsi->escape_clk_div, 100));
975
976 if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
977 /*
978 * BXT spec says write MIPI_INIT_COUNT for
979 * both the ports, even if only one is
980 * getting used. So write the other port
981 * if not in dual link mode.
982 */
983 I915_WRITE(MIPI_INIT_COUNT(port ==
984 PORT_A ? PORT_C : PORT_A),
985 intel_dsi->init_count);
986 }
987
988 /* recovery disables */
989 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
990
991 /* in terms of low power clock */
992 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
993
994 /* in terms of txbyteclkhs. actual high to low switch +
995 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
996 *
997 * XXX: write MIPI_STOP_STATE_STALL?
998 */
999 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1000 intel_dsi->hs_to_lp_count);
1001
1002 /* XXX: low power clock equivalence in terms of byte clock.
1003 * the number of byte clocks occupied in one low power clock.
1004 * based on txbyteclkhs and txclkesc.
1005 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1006 * ) / 105.???
1007 */
1008 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1009
1010 /* the bw essential for transmitting 16 long packets containing
1011 * 252 bytes meant for dcs write memory command is programmed in
1012 * this register in terms of byte clocks. based on dsi transfer
1013 * rate and the number of lanes configured the time taken to
1014 * transmit 16 long packets in a dsi stream varies. */
1015 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1016
1017 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1018 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1019 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1020
1021 if (is_vid_mode(intel_dsi))
1022 /* Some panels might have resolution which is not a
1023 * multiple of 64 like 1366 x 768. Enable RANDOM
1024 * resolution support for such panels by default */
1025 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1026 intel_dsi->video_frmt_cfg_bits |
1027 intel_dsi->video_mode_format |
1028 IP_TG_CONFIG |
1029 RANDOM_DPI_DISPLAY_RESOLUTION);
1030 }
1031}
1032
1033static enum drm_connector_status
1034intel_dsi_detect(struct drm_connector *connector, bool force)
1035{
1036 return connector_status_connected;
1037}
1038
1039static int intel_dsi_get_modes(struct drm_connector *connector)
1040{
1041 struct intel_connector *intel_connector = to_intel_connector(connector);
1042 struct drm_display_mode *mode;
1043
1044 DRM_DEBUG_KMS("\n");
1045
1046 if (!intel_connector->panel.fixed_mode) {
1047 DRM_DEBUG_KMS("no fixed mode\n");
1048 return 0;
1049 }
1050
1051 mode = drm_mode_duplicate(connector->dev,
1052 intel_connector->panel.fixed_mode);
1053 if (!mode) {
1054 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1055 return 0;
1056 }
1057
1058 drm_mode_probed_add(connector, mode);
1059 return 1;
1060}
1061
1062static void intel_dsi_connector_destroy(struct drm_connector *connector)
1063{
1064 struct intel_connector *intel_connector = to_intel_connector(connector);
1065
1066 DRM_DEBUG_KMS("\n");
1067 intel_panel_fini(&intel_connector->panel);
1068 drm_connector_cleanup(connector);
1069 kfree(connector);
1070}
1071
1072static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1073{
1074 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1075
1076 if (intel_dsi->panel) {
1077 drm_panel_detach(intel_dsi->panel);
1078 /* XXX: Logically this call belongs in the panel driver. */
1079 drm_panel_remove(intel_dsi->panel);
1080 }
1081
1082 /* dispose of the gpios */
1083 if (intel_dsi->gpio_panel)
1084 gpiod_put(intel_dsi->gpio_panel);
1085
1086 intel_encoder_destroy(encoder);
1087}
1088
1089static const struct drm_encoder_funcs intel_dsi_funcs = {
1090 .destroy = intel_dsi_encoder_destroy,
1091};
1092
1093static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1094 .get_modes = intel_dsi_get_modes,
1095 .mode_valid = intel_dsi_mode_valid,
1096 .best_encoder = intel_best_encoder,
1097};
1098
1099static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1100 .dpms = drm_atomic_helper_connector_dpms,
1101 .detect = intel_dsi_detect,
1102 .destroy = intel_dsi_connector_destroy,
1103 .fill_modes = drm_helper_probe_single_connector_modes,
1104 .atomic_get_property = intel_connector_atomic_get_property,
1105 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1106 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1107};
1108
1109void intel_dsi_init(struct drm_device *dev)
1110{
1111 struct intel_dsi *intel_dsi;
1112 struct intel_encoder *intel_encoder;
1113 struct drm_encoder *encoder;
1114 struct intel_connector *intel_connector;
1115 struct drm_connector *connector;
1116 struct drm_display_mode *scan, *fixed_mode = NULL;
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 enum port port;
1119 unsigned int i;
1120
1121 DRM_DEBUG_KMS("\n");
1122
1123 /* There is no detection method for MIPI so rely on VBT */
1124 if (!dev_priv->vbt.has_mipi)
1125 return;
1126
1127 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1128 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1129 } else {
1130 DRM_ERROR("Unsupported Mipi device to reg base");
1131 return;
1132 }
1133
1134 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1135 if (!intel_dsi)
1136 return;
1137
1138 intel_connector = intel_connector_alloc();
1139 if (!intel_connector) {
1140 kfree(intel_dsi);
1141 return;
1142 }
1143
1144 intel_encoder = &intel_dsi->base;
1145 encoder = &intel_encoder->base;
1146 intel_dsi->attached_connector = intel_connector;
1147
1148 connector = &intel_connector->base;
1149
1150 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1151 NULL);
1152
1153 intel_encoder->compute_config = intel_dsi_compute_config;
1154 intel_encoder->pre_enable = intel_dsi_pre_enable;
1155 intel_encoder->enable = intel_dsi_enable_nop;
1156 intel_encoder->disable = intel_dsi_pre_disable;
1157 intel_encoder->post_disable = intel_dsi_post_disable;
1158 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1159 intel_encoder->get_config = intel_dsi_get_config;
1160
1161 intel_connector->get_hw_state = intel_connector_get_hw_state;
1162 intel_connector->unregister = intel_connector_unregister;
1163
1164 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1165 if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1166 intel_encoder->crtc_mask = (1 << PIPE_A);
1167 intel_dsi->ports = (1 << PORT_A);
1168 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1169 intel_encoder->crtc_mask = (1 << PIPE_B);
1170 intel_dsi->ports = (1 << PORT_C);
1171 }
1172
1173 if (dev_priv->vbt.dsi.config->dual_link)
1174 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1175
1176 /* Create a DSI host (and a device) for each port. */
1177 for_each_dsi_port(port, intel_dsi->ports) {
1178 struct intel_dsi_host *host;
1179
1180 host = intel_dsi_host_init(intel_dsi, port);
1181 if (!host)
1182 goto err;
1183
1184 intel_dsi->dsi_hosts[port] = host;
1185 }
1186
1187 for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1188 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1189 intel_dsi_drivers[i].panel_id);
1190 if (intel_dsi->panel)
1191 break;
1192 }
1193
1194 if (!intel_dsi->panel) {
1195 DRM_DEBUG_KMS("no device found\n");
1196 goto err;
1197 }
1198
1199 /*
1200 * In case of BYT with CRC PMIC, we need to use GPIO for
1201 * Panel control.
1202 */
1203 if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1204 intel_dsi->gpio_panel =
1205 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1206
1207 if (IS_ERR(intel_dsi->gpio_panel)) {
1208 DRM_ERROR("Failed to own gpio for panel control\n");
1209 intel_dsi->gpio_panel = NULL;
1210 }
1211 }
1212
1213 intel_encoder->type = INTEL_OUTPUT_DSI;
1214 intel_encoder->cloneable = 0;
1215 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1216 DRM_MODE_CONNECTOR_DSI);
1217
1218 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1219
1220 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1221 connector->interlace_allowed = false;
1222 connector->doublescan_allowed = false;
1223
1224 intel_connector_attach_encoder(intel_connector, intel_encoder);
1225
1226 drm_connector_register(connector);
1227
1228 drm_panel_attach(intel_dsi->panel, connector);
1229
1230 mutex_lock(&dev->mode_config.mutex);
1231 drm_panel_get_modes(intel_dsi->panel);
1232 list_for_each_entry(scan, &connector->probed_modes, head) {
1233 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1234 fixed_mode = drm_mode_duplicate(dev, scan);
1235 break;
1236 }
1237 }
1238 mutex_unlock(&dev->mode_config.mutex);
1239
1240 if (!fixed_mode) {
1241 DRM_DEBUG_KMS("no fixed mode\n");
1242 goto err;
1243 }
1244
1245 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1246 intel_panel_setup_backlight(connector, INVALID_PIPE);
1247
1248 return;
1249
1250err:
1251 drm_encoder_cleanup(&intel_encoder->base);
1252 kfree(intel_dsi);
1253 kfree(intel_connector);
1254}