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1/*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 * QDI65x0:
29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html
31 *
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
35 *
36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
38 *
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
43 *
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
46 *
47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported.
49 *
50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B
55 *
56 * For now use autospeed and pio_mask as above with the W83759A. This may
57 * change.
58 *
59 */
60
61#include <linux/async.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/pci.h>
65#include <linux/init.h>
66#include <linux/blkdev.h>
67#include <linux/delay.h>
68#include <scsi/scsi_host.h>
69#include <linux/ata.h>
70#include <linux/libata.h>
71#include <linux/platform_device.h>
72
73#define DRV_NAME "pata_legacy"
74#define DRV_VERSION "0.6.5"
75
76#define NR_HOST 6
77
78static int all;
79module_param(all, int, 0444);
80MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
81
82enum controller {
83 BIOS = 0,
84 SNOOP = 1,
85 PDC20230 = 2,
86 HT6560A = 3,
87 HT6560B = 4,
88 OPTI611A = 5,
89 OPTI46X = 6,
90 QDI6500 = 7,
91 QDI6580 = 8,
92 QDI6580DP = 9, /* Dual channel mode is different */
93 W83759A = 10,
94
95 UNKNOWN = -1
96};
97
98struct legacy_data {
99 unsigned long timing;
100 u8 clock[2];
101 u8 last;
102 int fast;
103 enum controller type;
104 struct platform_device *platform_dev;
105};
106
107struct legacy_probe {
108 unsigned char *name;
109 unsigned long port;
110 unsigned int irq;
111 unsigned int slot;
112 enum controller type;
113 unsigned long private;
114};
115
116struct legacy_controller {
117 const char *name;
118 struct ata_port_operations *ops;
119 unsigned int pio_mask;
120 unsigned int flags;
121 unsigned int pflags;
122 int (*setup)(struct platform_device *, struct legacy_probe *probe,
123 struct legacy_data *data);
124};
125
126static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
127
128static struct legacy_probe probe_list[NR_HOST];
129static struct legacy_data legacy_data[NR_HOST];
130static struct ata_host *legacy_host[NR_HOST];
131static int nr_legacy_host;
132
133
134static int probe_all; /* Set to check all ISA port ranges */
135static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
138static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
139static int autospeed; /* Chip present which snoops speed changes */
140static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
141static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
142
143/* Set to probe QDI controllers */
144#ifdef CONFIG_PATA_QDI_MODULE
145static int qdi = 1;
146#else
147static int qdi;
148#endif
149
150#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
151static int winbond = 1; /* Set to probe Winbond controllers,
152 give I/O port if non standard */
153#else
154static int winbond; /* Set to probe Winbond controllers,
155 give I/O port if non standard */
156#endif
157
158/**
159 * legacy_probe_add - Add interface to probe list
160 * @port: Controller port
161 * @irq: IRQ number
162 * @type: Controller type
163 * @private: Controller specific info
164 *
165 * Add an entry into the probe list for ATA controllers. This is used
166 * to add the default ISA slots and then to build up the table
167 * further according to other ISA/VLB/Weird device scans
168 *
169 * An I/O port list is used to keep ordering stable and sane, as we
170 * don't have any good way to talk about ordering otherwise
171 */
172
173static int legacy_probe_add(unsigned long port, unsigned int irq,
174 enum controller type, unsigned long private)
175{
176 struct legacy_probe *lp = &probe_list[0];
177 int i;
178 struct legacy_probe *free = NULL;
179
180 for (i = 0; i < NR_HOST; i++) {
181 if (lp->port == 0 && free == NULL)
182 free = lp;
183 /* Matching port, or the correct slot for ordering */
184 if (lp->port == port || legacy_port[i] == port) {
185 free = lp;
186 break;
187 }
188 lp++;
189 }
190 if (free == NULL) {
191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
192 return -1;
193 }
194 /* Fill in the entry for later probing */
195 free->port = port;
196 free->irq = irq;
197 free->type = type;
198 free->private = private;
199 return 0;
200}
201
202
203/**
204 * legacy_set_mode - mode setting
205 * @link: IDE link
206 * @unused: Device that failed when error is returned
207 *
208 * Use a non standard set_mode function. We don't want to be tuned.
209 *
210 * The BIOS configured everything. Our job is not to fiddle. Just use
211 * whatever PIO the hardware is using and leave it at that. When we
212 * get some kind of nice user driven API for control then we can
213 * expand on this as per hdparm in the base kernel.
214 */
215
216static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
217{
218 struct ata_device *dev;
219
220 ata_for_each_dev(dev, link, ENABLED) {
221 ata_dev_info(dev, "configured for PIO\n");
222 dev->pio_mode = XFER_PIO_0;
223 dev->xfer_mode = XFER_PIO_0;
224 dev->xfer_shift = ATA_SHIFT_PIO;
225 dev->flags |= ATA_DFLAG_PIO;
226 }
227 return 0;
228}
229
230static struct scsi_host_template legacy_sht = {
231 ATA_PIO_SHT(DRV_NAME),
232};
233
234static const struct ata_port_operations legacy_base_port_ops = {
235 .inherits = &ata_sff_port_ops,
236 .cable_detect = ata_cable_40wire,
237};
238
239/*
240 * These ops are used if the user indicates the hardware
241 * snoops the commands to decide on the mode and handles the
242 * mode selection "magically" itself. Several legacy controllers
243 * do this. The mode range can be set if it is not 0x1F by setting
244 * pio_mask as well.
245 */
246
247static struct ata_port_operations simple_port_ops = {
248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer_noirq,
250};
251
252static struct ata_port_operations legacy_port_ops = {
253 .inherits = &legacy_base_port_ops,
254 .sff_data_xfer = ata_sff_data_xfer_noirq,
255 .set_mode = legacy_set_mode,
256};
257
258/*
259 * Promise 20230C and 20620 support
260 *
261 * This controller supports PIO0 to PIO2. We set PIO timings
262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
263 * support is weird being DMA to controller and PIO'd to the host
264 * and not supported.
265 */
266
267static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
268{
269 int tries = 5;
270 int pio = adev->pio_mode - XFER_PIO_0;
271 u8 rt;
272 unsigned long flags;
273
274 /* Safe as UP only. Force I/Os to occur together */
275
276 local_irq_save(flags);
277
278 /* Unlock the control interface */
279 do {
280 inb(0x1F5);
281 outb(inb(0x1F2) | 0x80, 0x1F2);
282 inb(0x1F2);
283 inb(0x3F6);
284 inb(0x3F6);
285 inb(0x1F2);
286 inb(0x1F2);
287 }
288 while ((inb(0x1F2) & 0x80) && --tries);
289
290 local_irq_restore(flags);
291
292 outb(inb(0x1F4) & 0x07, 0x1F4);
293
294 rt = inb(0x1F3);
295 rt &= 0x07 << (3 * adev->devno);
296 if (pio)
297 rt |= (1 + 3 * pio) << (3 * adev->devno);
298
299 udelay(100);
300 outb(inb(0x1F2) | 0x01, 0x1F2);
301 udelay(100);
302 inb(0x1F5);
303
304}
305
306static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
307 unsigned char *buf, unsigned int buflen, int rw)
308{
309 int slop = buflen & 3;
310 struct ata_port *ap = dev->link->ap;
311
312 /* 32bit I/O capable *and* we need to write a whole number of dwords */
313 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
314 && (ap->pflags & ATA_PFLAG_PIO32)) {
315 unsigned long flags;
316
317 local_irq_save(flags);
318
319 /* Perform the 32bit I/O synchronization sequence */
320 ioread8(ap->ioaddr.nsect_addr);
321 ioread8(ap->ioaddr.nsect_addr);
322 ioread8(ap->ioaddr.nsect_addr);
323
324 /* Now the data */
325 if (rw == READ)
326 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
327 else
328 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
329
330 if (unlikely(slop)) {
331 __le32 pad;
332 if (rw == READ) {
333 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
334 memcpy(buf + buflen - slop, &pad, slop);
335 } else {
336 memcpy(&pad, buf + buflen - slop, slop);
337 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
338 }
339 buflen += 4 - slop;
340 }
341 local_irq_restore(flags);
342 } else
343 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
344
345 return buflen;
346}
347
348static struct ata_port_operations pdc20230_port_ops = {
349 .inherits = &legacy_base_port_ops,
350 .set_piomode = pdc20230_set_piomode,
351 .sff_data_xfer = pdc_data_xfer_vlb,
352};
353
354/*
355 * Holtek 6560A support
356 *
357 * This controller supports PIO0 to PIO2 (no IORDY even though higher
358 * timings can be loaded).
359 */
360
361static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
362{
363 u8 active, recover;
364 struct ata_timing t;
365
366 /* Get the timing data in cycles. For now play safe at 50Mhz */
367 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
368
369 active = clamp_val(t.active, 2, 15);
370 recover = clamp_val(t.recover, 4, 15);
371
372 inb(0x3E6);
373 inb(0x3E6);
374 inb(0x3E6);
375 inb(0x3E6);
376
377 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
378 ioread8(ap->ioaddr.status_addr);
379}
380
381static struct ata_port_operations ht6560a_port_ops = {
382 .inherits = &legacy_base_port_ops,
383 .set_piomode = ht6560a_set_piomode,
384};
385
386/*
387 * Holtek 6560B support
388 *
389 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
390 * setting unless we see an ATAPI device in which case we force it off.
391 *
392 * FIXME: need to implement 2nd channel support.
393 */
394
395static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
396{
397 u8 active, recover;
398 struct ata_timing t;
399
400 /* Get the timing data in cycles. For now play safe at 50Mhz */
401 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
402
403 active = clamp_val(t.active, 2, 15);
404 recover = clamp_val(t.recover, 2, 16) & 0x0F;
405
406 inb(0x3E6);
407 inb(0x3E6);
408 inb(0x3E6);
409 inb(0x3E6);
410
411 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
412
413 if (adev->class != ATA_DEV_ATA) {
414 u8 rconf = inb(0x3E6);
415 if (rconf & 0x24) {
416 rconf &= ~0x24;
417 outb(rconf, 0x3E6);
418 }
419 }
420 ioread8(ap->ioaddr.status_addr);
421}
422
423static struct ata_port_operations ht6560b_port_ops = {
424 .inherits = &legacy_base_port_ops,
425 .set_piomode = ht6560b_set_piomode,
426};
427
428/*
429 * Opti core chipset helpers
430 */
431
432/**
433 * opti_syscfg - read OPTI chipset configuration
434 * @reg: Configuration register to read
435 *
436 * Returns the value of an OPTI system board configuration register.
437 */
438
439static u8 opti_syscfg(u8 reg)
440{
441 unsigned long flags;
442 u8 r;
443
444 /* Uniprocessor chipset and must force cycles adjancent */
445 local_irq_save(flags);
446 outb(reg, 0x22);
447 r = inb(0x24);
448 local_irq_restore(flags);
449 return r;
450}
451
452/*
453 * Opti 82C611A
454 *
455 * This controller supports PIO0 to PIO3.
456 */
457
458static void opti82c611a_set_piomode(struct ata_port *ap,
459 struct ata_device *adev)
460{
461 u8 active, recover, setup;
462 struct ata_timing t;
463 struct ata_device *pair = ata_dev_pair(adev);
464 int clock;
465 int khz[4] = { 50000, 40000, 33000, 25000 };
466 u8 rc;
467
468 /* Enter configuration mode */
469 ioread16(ap->ioaddr.error_addr);
470 ioread16(ap->ioaddr.error_addr);
471 iowrite8(3, ap->ioaddr.nsect_addr);
472
473 /* Read VLB clock strapping */
474 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
475
476 /* Get the timing data in cycles */
477 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
478
479 /* Setup timing is shared */
480 if (pair) {
481 struct ata_timing tp;
482 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
483
484 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
485 }
486
487 active = clamp_val(t.active, 2, 17) - 2;
488 recover = clamp_val(t.recover, 1, 16) - 1;
489 setup = clamp_val(t.setup, 1, 4) - 1;
490
491 /* Select the right timing bank for write timing */
492 rc = ioread8(ap->ioaddr.lbal_addr);
493 rc &= 0x7F;
494 rc |= (adev->devno << 7);
495 iowrite8(rc, ap->ioaddr.lbal_addr);
496
497 /* Write the timings */
498 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
499
500 /* Select the right bank for read timings, also
501 load the shared timings for address */
502 rc = ioread8(ap->ioaddr.device_addr);
503 rc &= 0xC0;
504 rc |= adev->devno; /* Index select */
505 rc |= (setup << 4) | 0x04;
506 iowrite8(rc, ap->ioaddr.device_addr);
507
508 /* Load the read timings */
509 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
510
511 /* Ensure the timing register mode is right */
512 rc = ioread8(ap->ioaddr.lbal_addr);
513 rc &= 0x73;
514 rc |= 0x84;
515 iowrite8(rc, ap->ioaddr.lbal_addr);
516
517 /* Exit command mode */
518 iowrite8(0x83, ap->ioaddr.nsect_addr);
519}
520
521
522static struct ata_port_operations opti82c611a_port_ops = {
523 .inherits = &legacy_base_port_ops,
524 .set_piomode = opti82c611a_set_piomode,
525};
526
527/*
528 * Opti 82C465MV
529 *
530 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
531 * version is dual channel but doesn't have a lot of unique registers.
532 */
533
534static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
535{
536 u8 active, recover, setup;
537 struct ata_timing t;
538 struct ata_device *pair = ata_dev_pair(adev);
539 int clock;
540 int khz[4] = { 50000, 40000, 33000, 25000 };
541 u8 rc;
542 u8 sysclk;
543
544 /* Get the clock */
545 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
546
547 /* Enter configuration mode */
548 ioread16(ap->ioaddr.error_addr);
549 ioread16(ap->ioaddr.error_addr);
550 iowrite8(3, ap->ioaddr.nsect_addr);
551
552 /* Read VLB clock strapping */
553 clock = 1000000000 / khz[sysclk];
554
555 /* Get the timing data in cycles */
556 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
557
558 /* Setup timing is shared */
559 if (pair) {
560 struct ata_timing tp;
561 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
562
563 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
564 }
565
566 active = clamp_val(t.active, 2, 17) - 2;
567 recover = clamp_val(t.recover, 1, 16) - 1;
568 setup = clamp_val(t.setup, 1, 4) - 1;
569
570 /* Select the right timing bank for write timing */
571 rc = ioread8(ap->ioaddr.lbal_addr);
572 rc &= 0x7F;
573 rc |= (adev->devno << 7);
574 iowrite8(rc, ap->ioaddr.lbal_addr);
575
576 /* Write the timings */
577 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
578
579 /* Select the right bank for read timings, also
580 load the shared timings for address */
581 rc = ioread8(ap->ioaddr.device_addr);
582 rc &= 0xC0;
583 rc |= adev->devno; /* Index select */
584 rc |= (setup << 4) | 0x04;
585 iowrite8(rc, ap->ioaddr.device_addr);
586
587 /* Load the read timings */
588 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
589
590 /* Ensure the timing register mode is right */
591 rc = ioread8(ap->ioaddr.lbal_addr);
592 rc &= 0x73;
593 rc |= 0x84;
594 iowrite8(rc, ap->ioaddr.lbal_addr);
595
596 /* Exit command mode */
597 iowrite8(0x83, ap->ioaddr.nsect_addr);
598
599 /* We need to know this for quad device on the MVB */
600 ap->host->private_data = ap;
601}
602
603/**
604 * opt82c465mv_qc_issue - command issue
605 * @qc: command pending
606 *
607 * Called when the libata layer is about to issue a command. We wrap
608 * this interface so that we can load the correct ATA timings. The
609 * MVB has a single set of timing registers and these are shared
610 * across channels. As there are two registers we really ought to
611 * track the last two used values as a sort of register window. For
612 * now we just reload on a channel switch. On the single channel
613 * setup this condition never fires so we do nothing extra.
614 *
615 * FIXME: dual channel needs ->serialize support
616 */
617
618static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
619{
620 struct ata_port *ap = qc->ap;
621 struct ata_device *adev = qc->dev;
622
623 /* If timings are set and for the wrong channel (2nd test is
624 due to a libata shortcoming and will eventually go I hope) */
625 if (ap->host->private_data != ap->host
626 && ap->host->private_data != NULL)
627 opti82c46x_set_piomode(ap, adev);
628
629 return ata_sff_qc_issue(qc);
630}
631
632static struct ata_port_operations opti82c46x_port_ops = {
633 .inherits = &legacy_base_port_ops,
634 .set_piomode = opti82c46x_set_piomode,
635 .qc_issue = opti82c46x_qc_issue,
636};
637
638/**
639 * qdi65x0_set_piomode - PIO setup for QDI65x0
640 * @ap: Port
641 * @adev: Device
642 *
643 * In single channel mode the 6580 has one clock per device and we can
644 * avoid the requirement to clock switch. We also have to load the timing
645 * into the right clock according to whether we are master or slave.
646 *
647 * In dual channel mode the 6580 has one clock per channel and we have
648 * to software clockswitch in qc_issue.
649 */
650
651static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
652{
653 struct ata_timing t;
654 struct legacy_data *ld_qdi = ap->host->private_data;
655 int active, recovery;
656 u8 timing;
657
658 /* Get the timing data in cycles */
659 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
660
661 if (ld_qdi->fast) {
662 active = 8 - clamp_val(t.active, 1, 8);
663 recovery = 18 - clamp_val(t.recover, 3, 18);
664 } else {
665 active = 9 - clamp_val(t.active, 2, 9);
666 recovery = 15 - clamp_val(t.recover, 0, 15);
667 }
668 timing = (recovery << 4) | active | 0x08;
669 ld_qdi->clock[adev->devno] = timing;
670
671 if (ld_qdi->type == QDI6580)
672 outb(timing, ld_qdi->timing + 2 * adev->devno);
673 else
674 outb(timing, ld_qdi->timing + 2 * ap->port_no);
675
676 /* Clear the FIFO */
677 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
678 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
679}
680
681/**
682 * qdi_qc_issue - command issue
683 * @qc: command pending
684 *
685 * Called when the libata layer is about to issue a command. We wrap
686 * this interface so that we can load the correct ATA timings.
687 */
688
689static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
690{
691 struct ata_port *ap = qc->ap;
692 struct ata_device *adev = qc->dev;
693 struct legacy_data *ld_qdi = ap->host->private_data;
694
695 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
696 if (adev->pio_mode) {
697 ld_qdi->last = ld_qdi->clock[adev->devno];
698 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
699 2 * ap->port_no);
700 }
701 }
702 return ata_sff_qc_issue(qc);
703}
704
705static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
706 unsigned int buflen, int rw)
707{
708 struct ata_port *ap = adev->link->ap;
709 int slop = buflen & 3;
710
711 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
712 && (ap->pflags & ATA_PFLAG_PIO32)) {
713 if (rw == WRITE)
714 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
715 else
716 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
717
718 if (unlikely(slop)) {
719 __le32 pad;
720 if (rw == WRITE) {
721 memcpy(&pad, buf + buflen - slop, slop);
722 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
723 } else {
724 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
725 memcpy(buf + buflen - slop, &pad, slop);
726 }
727 }
728 return (buflen + 3) & ~3;
729 } else
730 return ata_sff_data_xfer(adev, buf, buflen, rw);
731}
732
733static int qdi_port(struct platform_device *dev,
734 struct legacy_probe *lp, struct legacy_data *ld)
735{
736 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
737 return -EBUSY;
738 ld->timing = lp->private;
739 return 0;
740}
741
742static struct ata_port_operations qdi6500_port_ops = {
743 .inherits = &legacy_base_port_ops,
744 .set_piomode = qdi65x0_set_piomode,
745 .qc_issue = qdi_qc_issue,
746 .sff_data_xfer = vlb32_data_xfer,
747};
748
749static struct ata_port_operations qdi6580_port_ops = {
750 .inherits = &legacy_base_port_ops,
751 .set_piomode = qdi65x0_set_piomode,
752 .sff_data_xfer = vlb32_data_xfer,
753};
754
755static struct ata_port_operations qdi6580dp_port_ops = {
756 .inherits = &legacy_base_port_ops,
757 .set_piomode = qdi65x0_set_piomode,
758 .qc_issue = qdi_qc_issue,
759 .sff_data_xfer = vlb32_data_xfer,
760};
761
762static DEFINE_SPINLOCK(winbond_lock);
763
764static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
765{
766 unsigned long flags;
767 spin_lock_irqsave(&winbond_lock, flags);
768 outb(reg, port + 0x01);
769 outb(val, port + 0x02);
770 spin_unlock_irqrestore(&winbond_lock, flags);
771}
772
773static u8 winbond_readcfg(unsigned long port, u8 reg)
774{
775 u8 val;
776
777 unsigned long flags;
778 spin_lock_irqsave(&winbond_lock, flags);
779 outb(reg, port + 0x01);
780 val = inb(port + 0x02);
781 spin_unlock_irqrestore(&winbond_lock, flags);
782
783 return val;
784}
785
786static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
787{
788 struct ata_timing t;
789 struct legacy_data *ld_winbond = ap->host->private_data;
790 int active, recovery;
791 u8 reg;
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
793
794 reg = winbond_readcfg(ld_winbond->timing, 0x81);
795
796 /* Get the timing data in cycles */
797 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
798 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
799 else
800 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
801
802 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
803 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
804 timing = (active << 4) | recovery;
805 winbond_writecfg(ld_winbond->timing, timing, reg);
806
807 /* Load the setup timing */
808
809 reg = 0x35;
810 if (adev->class != ATA_DEV_ATA)
811 reg |= 0x08; /* FIFO off */
812 if (!ata_pio_need_iordy(adev))
813 reg |= 0x02; /* IORDY off */
814 reg |= (clamp_val(t.setup, 0, 3) << 6);
815 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
816}
817
818static int winbond_port(struct platform_device *dev,
819 struct legacy_probe *lp, struct legacy_data *ld)
820{
821 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
822 return -EBUSY;
823 ld->timing = lp->private;
824 return 0;
825}
826
827static struct ata_port_operations winbond_port_ops = {
828 .inherits = &legacy_base_port_ops,
829 .set_piomode = winbond_set_piomode,
830 .sff_data_xfer = vlb32_data_xfer,
831};
832
833static struct legacy_controller controllers[] = {
834 {"BIOS", &legacy_port_ops, ATA_PIO4,
835 ATA_FLAG_NO_IORDY, 0, NULL },
836 {"Snooping", &simple_port_ops, ATA_PIO4,
837 0, 0, NULL },
838 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
839 ATA_FLAG_NO_IORDY,
840 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
841 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
842 ATA_FLAG_NO_IORDY, 0, NULL },
843 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
844 ATA_FLAG_NO_IORDY, 0, NULL },
845 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
846 0, 0, NULL },
847 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
848 0, 0, NULL },
849 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
850 ATA_FLAG_NO_IORDY,
851 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
852 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
853 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
854 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
855 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
856 {"W83759A", &winbond_port_ops, ATA_PIO4,
857 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
858 winbond_port }
859};
860
861/**
862 * probe_chip_type - Discover controller
863 * @probe: Probe entry to check
864 *
865 * Probe an ATA port and identify the type of controller. We don't
866 * check if the controller appears to be driveless at this point.
867 */
868
869static __init int probe_chip_type(struct legacy_probe *probe)
870{
871 int mask = 1 << probe->slot;
872
873 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
874 u8 reg = winbond_readcfg(winbond, 0x81);
875 reg |= 0x80; /* jumpered mode off */
876 winbond_writecfg(winbond, 0x81, reg);
877 reg = winbond_readcfg(winbond, 0x83);
878 reg |= 0xF0; /* local control */
879 winbond_writecfg(winbond, 0x83, reg);
880 reg = winbond_readcfg(winbond, 0x85);
881 reg |= 0xF0; /* programmable timing */
882 winbond_writecfg(winbond, 0x85, reg);
883
884 reg = winbond_readcfg(winbond, 0x81);
885
886 if (reg & mask)
887 return W83759A;
888 }
889 if (probe->port == 0x1F0) {
890 unsigned long flags;
891 local_irq_save(flags);
892 /* Probes */
893 outb(inb(0x1F2) | 0x80, 0x1F2);
894 inb(0x1F5);
895 inb(0x1F2);
896 inb(0x3F6);
897 inb(0x3F6);
898 inb(0x1F2);
899 inb(0x1F2);
900
901 if ((inb(0x1F2) & 0x80) == 0) {
902 /* PDC20230c or 20630 ? */
903 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
904 " detected.\n");
905 udelay(100);
906 inb(0x1F5);
907 local_irq_restore(flags);
908 return PDC20230;
909 } else {
910 outb(0x55, 0x1F2);
911 inb(0x1F2);
912 inb(0x1F2);
913 if (inb(0x1F2) == 0x00)
914 printk(KERN_INFO "PDC20230-B VLB ATA "
915 "controller detected.\n");
916 local_irq_restore(flags);
917 return BIOS;
918 }
919 }
920
921 if (ht6560a & mask)
922 return HT6560A;
923 if (ht6560b & mask)
924 return HT6560B;
925 if (opti82c611a & mask)
926 return OPTI611A;
927 if (opti82c46x & mask)
928 return OPTI46X;
929 if (autospeed & mask)
930 return SNOOP;
931 return BIOS;
932}
933
934
935/**
936 * legacy_init_one - attach a legacy interface
937 * @pl: probe record
938 *
939 * Register an ISA bus IDE interface. Such interfaces are PIO and we
940 * assume do not support IRQ sharing.
941 */
942
943static __init int legacy_init_one(struct legacy_probe *probe)
944{
945 struct legacy_controller *controller = &controllers[probe->type];
946 int pio_modes = controller->pio_mask;
947 unsigned long io = probe->port;
948 u32 mask = (1 << probe->slot);
949 struct ata_port_operations *ops = controller->ops;
950 struct legacy_data *ld = &legacy_data[probe->slot];
951 struct ata_host *host = NULL;
952 struct ata_port *ap;
953 struct platform_device *pdev;
954 struct ata_device *dev;
955 void __iomem *io_addr, *ctrl_addr;
956 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
957 int ret;
958
959 iordy |= controller->flags;
960
961 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
962 if (IS_ERR(pdev))
963 return PTR_ERR(pdev);
964
965 ret = -EBUSY;
966 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
967 devm_request_region(&pdev->dev, io + 0x0206, 1,
968 "pata_legacy") == NULL)
969 goto fail;
970
971 ret = -ENOMEM;
972 io_addr = devm_ioport_map(&pdev->dev, io, 8);
973 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
974 if (!io_addr || !ctrl_addr)
975 goto fail;
976 ld->type = probe->type;
977 if (controller->setup)
978 if (controller->setup(pdev, probe, ld) < 0)
979 goto fail;
980 host = ata_host_alloc(&pdev->dev, 1);
981 if (!host)
982 goto fail;
983 ap = host->ports[0];
984
985 ap->ops = ops;
986 ap->pio_mask = pio_modes;
987 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
988 ap->pflags |= controller->pflags;
989 ap->ioaddr.cmd_addr = io_addr;
990 ap->ioaddr.altstatus_addr = ctrl_addr;
991 ap->ioaddr.ctl_addr = ctrl_addr;
992 ata_sff_std_ports(&ap->ioaddr);
993 ap->host->private_data = ld;
994
995 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
996
997 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
998 &legacy_sht);
999 if (ret)
1000 goto fail;
1001 async_synchronize_full();
1002 ld->platform_dev = pdev;
1003
1004 /* Nothing found means we drop the port as its probably not there */
1005
1006 ret = -ENODEV;
1007 ata_for_each_dev(dev, &ap->link, ALL) {
1008 if (!ata_dev_absent(dev)) {
1009 legacy_host[probe->slot] = host;
1010 ld->platform_dev = pdev;
1011 return 0;
1012 }
1013 }
1014 ata_host_detach(host);
1015fail:
1016 platform_device_unregister(pdev);
1017 return ret;
1018}
1019
1020/**
1021 * legacy_check_special_cases - ATA special cases
1022 * @p: PCI device to check
1023 * @master: set this if we find an ATA master
1024 * @master: set this if we find an ATA secondary
1025 *
1026 * A small number of vendors implemented early PCI ATA interfaces
1027 * on bridge logic without the ATA interface being PCI visible.
1028 * Where we have a matching PCI driver we must skip the relevant
1029 * device here. If we don't know about it then the legacy driver
1030 * is the right driver anyway.
1031 */
1032
1033static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1034 int *secondary)
1035{
1036 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1037 if (p->vendor == 0x1078 && p->device == 0x0000) {
1038 *primary = *secondary = 1;
1039 return;
1040 }
1041 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1042 if (p->vendor == 0x1078 && p->device == 0x0002) {
1043 *primary = *secondary = 1;
1044 return;
1045 }
1046 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1047 if (p->vendor == 0x8086 && p->device == 0x1234) {
1048 u16 r;
1049 pci_read_config_word(p, 0x6C, &r);
1050 if (r & 0x8000) {
1051 /* ATA port enabled */
1052 if (r & 0x4000)
1053 *secondary = 1;
1054 else
1055 *primary = 1;
1056 }
1057 return;
1058 }
1059}
1060
1061static __init void probe_opti_vlb(void)
1062{
1063 /* If an OPTI 82C46X is present find out where the channels are */
1064 static const char *optis[4] = {
1065 "3/463MV", "5MV",
1066 "5MVA", "5MVB"
1067 };
1068 u8 chans = 1;
1069 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1070
1071 opti82c46x = 3; /* Assume master and slave first */
1072 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1073 optis[ctrl]);
1074 if (ctrl == 3)
1075 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1076 ctrl = opti_syscfg(0xAC);
1077 /* Check enabled and this port is the 465MV port. On the
1078 MVB we may have two channels */
1079 if (ctrl & 8) {
1080 if (chans == 2) {
1081 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1082 legacy_probe_add(0x170, 15, OPTI46X, 0);
1083 }
1084 if (ctrl & 4)
1085 legacy_probe_add(0x170, 15, OPTI46X, 0);
1086 else
1087 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1088 } else
1089 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1090}
1091
1092static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1093{
1094 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1095 /* Check card type */
1096 if ((r & 0xF0) == 0xC0) {
1097 /* QD6500: single channel */
1098 if (r & 8)
1099 /* Disabled ? */
1100 return;
1101 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1102 QDI6500, port);
1103 }
1104 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1105 /* QD6580: dual channel */
1106 if (!request_region(port + 2 , 2, "pata_qdi")) {
1107 release_region(port, 2);
1108 return;
1109 }
1110 res = inb(port + 3);
1111 /* Single channel mode ? */
1112 if (res & 1)
1113 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1114 QDI6580, port);
1115 else { /* Dual channel mode */
1116 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1117 /* port + 0x02, r & 0x04 */
1118 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1119 }
1120 release_region(port + 2, 2);
1121 }
1122}
1123
1124static __init void probe_qdi_vlb(void)
1125{
1126 unsigned long flags;
1127 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1128 int i;
1129
1130 /*
1131 * Check each possible QD65xx base address
1132 */
1133
1134 for (i = 0; i < 2; i++) {
1135 unsigned long port = qd_port[i];
1136 u8 r, res;
1137
1138
1139 if (request_region(port, 2, "pata_qdi")) {
1140 /* Check for a card */
1141 local_irq_save(flags);
1142 /* I have no h/w that needs this delay but it
1143 is present in the historic code */
1144 r = inb(port);
1145 udelay(1);
1146 outb(0x19, port);
1147 udelay(1);
1148 res = inb(port);
1149 udelay(1);
1150 outb(r, port);
1151 udelay(1);
1152 local_irq_restore(flags);
1153
1154 /* Fail */
1155 if (res == 0x19) {
1156 release_region(port, 2);
1157 continue;
1158 }
1159 /* Passes the presence test */
1160 r = inb(port + 1);
1161 udelay(1);
1162 /* Check port agrees with port set */
1163 if ((r & 2) >> 1 == i)
1164 qdi65_identify_port(r, res, port);
1165 release_region(port, 2);
1166 }
1167 }
1168}
1169
1170/**
1171 * legacy_init - attach legacy interfaces
1172 *
1173 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1174 * Right now we do not scan the ide0 and ide1 address but should do so
1175 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1176 * If you fix that note there are special cases to consider like VLB
1177 * drivers and CS5510/20.
1178 */
1179
1180static __init int legacy_init(void)
1181{
1182 int i;
1183 int ct = 0;
1184 int primary = 0;
1185 int secondary = 0;
1186 int pci_present = 0;
1187 struct legacy_probe *pl = &probe_list[0];
1188 int slot = 0;
1189
1190 struct pci_dev *p = NULL;
1191
1192 for_each_pci_dev(p) {
1193 int r;
1194 /* Check for any overlap of the system ATA mappings. Native
1195 mode controllers stuck on these addresses or some devices
1196 in 'raid' mode won't be found by the storage class test */
1197 for (r = 0; r < 6; r++) {
1198 if (pci_resource_start(p, r) == 0x1f0)
1199 primary = 1;
1200 if (pci_resource_start(p, r) == 0x170)
1201 secondary = 1;
1202 }
1203 /* Check for special cases */
1204 legacy_check_special_cases(p, &primary, &secondary);
1205
1206 /* If PCI bus is present then don't probe for tertiary
1207 legacy ports */
1208 pci_present = 1;
1209 }
1210
1211 if (winbond == 1)
1212 winbond = 0x130; /* Default port, alt is 1B0 */
1213
1214 if (primary == 0 || all)
1215 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1216 if (secondary == 0 || all)
1217 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1218
1219 if (probe_all || !pci_present) {
1220 /* ISA/VLB extra ports */
1221 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1222 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1223 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1224 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1225 }
1226
1227 if (opti82c46x)
1228 probe_opti_vlb();
1229 if (qdi)
1230 probe_qdi_vlb();
1231
1232 for (i = 0; i < NR_HOST; i++, pl++) {
1233 if (pl->port == 0)
1234 continue;
1235 if (pl->type == UNKNOWN)
1236 pl->type = probe_chip_type(pl);
1237 pl->slot = slot++;
1238 if (legacy_init_one(pl) == 0)
1239 ct++;
1240 }
1241 if (ct != 0)
1242 return 0;
1243 return -ENODEV;
1244}
1245
1246static __exit void legacy_exit(void)
1247{
1248 int i;
1249
1250 for (i = 0; i < nr_legacy_host; i++) {
1251 struct legacy_data *ld = &legacy_data[i];
1252 ata_host_detach(legacy_host[i]);
1253 platform_device_unregister(ld->platform_dev);
1254 }
1255}
1256
1257MODULE_AUTHOR("Alan Cox");
1258MODULE_DESCRIPTION("low-level driver for legacy ATA");
1259MODULE_LICENSE("GPL");
1260MODULE_VERSION(DRV_VERSION);
1261MODULE_ALIAS("pata_qdi");
1262MODULE_ALIAS("pata_winbond");
1263
1264module_param(probe_all, int, 0);
1265module_param(autospeed, int, 0);
1266module_param(ht6560a, int, 0);
1267module_param(ht6560b, int, 0);
1268module_param(opti82c611a, int, 0);
1269module_param(opti82c46x, int, 0);
1270module_param(qdi, int, 0);
1271module_param(winbond, int, 0);
1272module_param(pio_mask, int, 0);
1273module_param(iordy_mask, int, 0);
1274
1275module_init(legacy_init);
1276module_exit(legacy_exit);
1/*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 * QDI65x0:
29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html
31 *
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
35 *
36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
38 *
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
43 *
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
46 *
47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported.
49 *
50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B
55 *
56 * For now use autospeed and pio_mask as above with the W83759A. This may
57 * change.
58 *
59 */
60
61#include <linux/async.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/pci.h>
65#include <linux/init.h>
66#include <linux/blkdev.h>
67#include <linux/delay.h>
68#include <scsi/scsi_host.h>
69#include <linux/ata.h>
70#include <linux/libata.h>
71#include <linux/platform_device.h>
72
73#define DRV_NAME "pata_legacy"
74#define DRV_VERSION "0.6.5"
75
76#define NR_HOST 6
77
78static int all;
79module_param(all, int, 0444);
80MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
81
82struct legacy_data {
83 unsigned long timing;
84 u8 clock[2];
85 u8 last;
86 int fast;
87 struct platform_device *platform_dev;
88
89};
90
91enum controller {
92 BIOS = 0,
93 SNOOP = 1,
94 PDC20230 = 2,
95 HT6560A = 3,
96 HT6560B = 4,
97 OPTI611A = 5,
98 OPTI46X = 6,
99 QDI6500 = 7,
100 QDI6580 = 8,
101 QDI6580DP = 9, /* Dual channel mode is different */
102 W83759A = 10,
103
104 UNKNOWN = -1
105};
106
107
108struct legacy_probe {
109 unsigned char *name;
110 unsigned long port;
111 unsigned int irq;
112 unsigned int slot;
113 enum controller type;
114 unsigned long private;
115};
116
117struct legacy_controller {
118 const char *name;
119 struct ata_port_operations *ops;
120 unsigned int pio_mask;
121 unsigned int flags;
122 unsigned int pflags;
123 int (*setup)(struct platform_device *, struct legacy_probe *probe,
124 struct legacy_data *data);
125};
126
127static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
128
129static struct legacy_probe probe_list[NR_HOST];
130static struct legacy_data legacy_data[NR_HOST];
131static struct ata_host *legacy_host[NR_HOST];
132static int nr_legacy_host;
133
134
135static int probe_all; /* Set to check all ISA port ranges */
136static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
137static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
138static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
139static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
140static int qdi; /* Set to probe QDI controllers */
141static int autospeed; /* Chip present which snoops speed changes */
142static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
143static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
144
145#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
146static int winbond = 1; /* Set to probe Winbond controllers,
147 give I/O port if non standard */
148#else
149static int winbond; /* Set to probe Winbond controllers,
150 give I/O port if non standard */
151#endif
152
153/**
154 * legacy_probe_add - Add interface to probe list
155 * @port: Controller port
156 * @irq: IRQ number
157 * @type: Controller type
158 * @private: Controller specific info
159 *
160 * Add an entry into the probe list for ATA controllers. This is used
161 * to add the default ISA slots and then to build up the table
162 * further according to other ISA/VLB/Weird device scans
163 *
164 * An I/O port list is used to keep ordering stable and sane, as we
165 * don't have any good way to talk about ordering otherwise
166 */
167
168static int legacy_probe_add(unsigned long port, unsigned int irq,
169 enum controller type, unsigned long private)
170{
171 struct legacy_probe *lp = &probe_list[0];
172 int i;
173 struct legacy_probe *free = NULL;
174
175 for (i = 0; i < NR_HOST; i++) {
176 if (lp->port == 0 && free == NULL)
177 free = lp;
178 /* Matching port, or the correct slot for ordering */
179 if (lp->port == port || legacy_port[i] == port) {
180 free = lp;
181 break;
182 }
183 lp++;
184 }
185 if (free == NULL) {
186 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
187 return -1;
188 }
189 /* Fill in the entry for later probing */
190 free->port = port;
191 free->irq = irq;
192 free->type = type;
193 free->private = private;
194 return 0;
195}
196
197
198/**
199 * legacy_set_mode - mode setting
200 * @link: IDE link
201 * @unused: Device that failed when error is returned
202 *
203 * Use a non standard set_mode function. We don't want to be tuned.
204 *
205 * The BIOS configured everything. Our job is not to fiddle. Just use
206 * whatever PIO the hardware is using and leave it at that. When we
207 * get some kind of nice user driven API for control then we can
208 * expand on this as per hdparm in the base kernel.
209 */
210
211static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
212{
213 struct ata_device *dev;
214
215 ata_for_each_dev(dev, link, ENABLED) {
216 ata_dev_info(dev, "configured for PIO\n");
217 dev->pio_mode = XFER_PIO_0;
218 dev->xfer_mode = XFER_PIO_0;
219 dev->xfer_shift = ATA_SHIFT_PIO;
220 dev->flags |= ATA_DFLAG_PIO;
221 }
222 return 0;
223}
224
225static struct scsi_host_template legacy_sht = {
226 ATA_PIO_SHT(DRV_NAME),
227};
228
229static const struct ata_port_operations legacy_base_port_ops = {
230 .inherits = &ata_sff_port_ops,
231 .cable_detect = ata_cable_40wire,
232};
233
234/*
235 * These ops are used if the user indicates the hardware
236 * snoops the commands to decide on the mode and handles the
237 * mode selection "magically" itself. Several legacy controllers
238 * do this. The mode range can be set if it is not 0x1F by setting
239 * pio_mask as well.
240 */
241
242static struct ata_port_operations simple_port_ops = {
243 .inherits = &legacy_base_port_ops,
244 .sff_data_xfer = ata_sff_data_xfer_noirq,
245};
246
247static struct ata_port_operations legacy_port_ops = {
248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer_noirq,
250 .set_mode = legacy_set_mode,
251};
252
253/*
254 * Promise 20230C and 20620 support
255 *
256 * This controller supports PIO0 to PIO2. We set PIO timings
257 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
258 * support is weird being DMA to controller and PIO'd to the host
259 * and not supported.
260 */
261
262static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
263{
264 int tries = 5;
265 int pio = adev->pio_mode - XFER_PIO_0;
266 u8 rt;
267 unsigned long flags;
268
269 /* Safe as UP only. Force I/Os to occur together */
270
271 local_irq_save(flags);
272
273 /* Unlock the control interface */
274 do {
275 inb(0x1F5);
276 outb(inb(0x1F2) | 0x80, 0x1F2);
277 inb(0x1F2);
278 inb(0x3F6);
279 inb(0x3F6);
280 inb(0x1F2);
281 inb(0x1F2);
282 }
283 while ((inb(0x1F2) & 0x80) && --tries);
284
285 local_irq_restore(flags);
286
287 outb(inb(0x1F4) & 0x07, 0x1F4);
288
289 rt = inb(0x1F3);
290 rt &= 0x07 << (3 * adev->devno);
291 if (pio)
292 rt |= (1 + 3 * pio) << (3 * adev->devno);
293
294 udelay(100);
295 outb(inb(0x1F2) | 0x01, 0x1F2);
296 udelay(100);
297 inb(0x1F5);
298
299}
300
301static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
302 unsigned char *buf, unsigned int buflen, int rw)
303{
304 int slop = buflen & 3;
305 struct ata_port *ap = dev->link->ap;
306
307 /* 32bit I/O capable *and* we need to write a whole number of dwords */
308 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
309 && (ap->pflags & ATA_PFLAG_PIO32)) {
310 unsigned long flags;
311
312 local_irq_save(flags);
313
314 /* Perform the 32bit I/O synchronization sequence */
315 ioread8(ap->ioaddr.nsect_addr);
316 ioread8(ap->ioaddr.nsect_addr);
317 ioread8(ap->ioaddr.nsect_addr);
318
319 /* Now the data */
320 if (rw == READ)
321 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
322 else
323 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
324
325 if (unlikely(slop)) {
326 __le32 pad;
327 if (rw == READ) {
328 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
329 memcpy(buf + buflen - slop, &pad, slop);
330 } else {
331 memcpy(&pad, buf + buflen - slop, slop);
332 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
333 }
334 buflen += 4 - slop;
335 }
336 local_irq_restore(flags);
337 } else
338 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
339
340 return buflen;
341}
342
343static struct ata_port_operations pdc20230_port_ops = {
344 .inherits = &legacy_base_port_ops,
345 .set_piomode = pdc20230_set_piomode,
346 .sff_data_xfer = pdc_data_xfer_vlb,
347};
348
349/*
350 * Holtek 6560A support
351 *
352 * This controller supports PIO0 to PIO2 (no IORDY even though higher
353 * timings can be loaded).
354 */
355
356static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
357{
358 u8 active, recover;
359 struct ata_timing t;
360
361 /* Get the timing data in cycles. For now play safe at 50Mhz */
362 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
363
364 active = clamp_val(t.active, 2, 15);
365 recover = clamp_val(t.recover, 4, 15);
366
367 inb(0x3E6);
368 inb(0x3E6);
369 inb(0x3E6);
370 inb(0x3E6);
371
372 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
373 ioread8(ap->ioaddr.status_addr);
374}
375
376static struct ata_port_operations ht6560a_port_ops = {
377 .inherits = &legacy_base_port_ops,
378 .set_piomode = ht6560a_set_piomode,
379};
380
381/*
382 * Holtek 6560B support
383 *
384 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
385 * setting unless we see an ATAPI device in which case we force it off.
386 *
387 * FIXME: need to implement 2nd channel support.
388 */
389
390static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
391{
392 u8 active, recover;
393 struct ata_timing t;
394
395 /* Get the timing data in cycles. For now play safe at 50Mhz */
396 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
397
398 active = clamp_val(t.active, 2, 15);
399 recover = clamp_val(t.recover, 2, 16);
400 recover &= 0x15;
401
402 inb(0x3E6);
403 inb(0x3E6);
404 inb(0x3E6);
405 inb(0x3E6);
406
407 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
408
409 if (adev->class != ATA_DEV_ATA) {
410 u8 rconf = inb(0x3E6);
411 if (rconf & 0x24) {
412 rconf &= ~0x24;
413 outb(rconf, 0x3E6);
414 }
415 }
416 ioread8(ap->ioaddr.status_addr);
417}
418
419static struct ata_port_operations ht6560b_port_ops = {
420 .inherits = &legacy_base_port_ops,
421 .set_piomode = ht6560b_set_piomode,
422};
423
424/*
425 * Opti core chipset helpers
426 */
427
428/**
429 * opti_syscfg - read OPTI chipset configuration
430 * @reg: Configuration register to read
431 *
432 * Returns the value of an OPTI system board configuration register.
433 */
434
435static u8 opti_syscfg(u8 reg)
436{
437 unsigned long flags;
438 u8 r;
439
440 /* Uniprocessor chipset and must force cycles adjancent */
441 local_irq_save(flags);
442 outb(reg, 0x22);
443 r = inb(0x24);
444 local_irq_restore(flags);
445 return r;
446}
447
448/*
449 * Opti 82C611A
450 *
451 * This controller supports PIO0 to PIO3.
452 */
453
454static void opti82c611a_set_piomode(struct ata_port *ap,
455 struct ata_device *adev)
456{
457 u8 active, recover, setup;
458 struct ata_timing t;
459 struct ata_device *pair = ata_dev_pair(adev);
460 int clock;
461 int khz[4] = { 50000, 40000, 33000, 25000 };
462 u8 rc;
463
464 /* Enter configuration mode */
465 ioread16(ap->ioaddr.error_addr);
466 ioread16(ap->ioaddr.error_addr);
467 iowrite8(3, ap->ioaddr.nsect_addr);
468
469 /* Read VLB clock strapping */
470 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
471
472 /* Get the timing data in cycles */
473 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
474
475 /* Setup timing is shared */
476 if (pair) {
477 struct ata_timing tp;
478 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
479
480 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
481 }
482
483 active = clamp_val(t.active, 2, 17) - 2;
484 recover = clamp_val(t.recover, 1, 16) - 1;
485 setup = clamp_val(t.setup, 1, 4) - 1;
486
487 /* Select the right timing bank for write timing */
488 rc = ioread8(ap->ioaddr.lbal_addr);
489 rc &= 0x7F;
490 rc |= (adev->devno << 7);
491 iowrite8(rc, ap->ioaddr.lbal_addr);
492
493 /* Write the timings */
494 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
495
496 /* Select the right bank for read timings, also
497 load the shared timings for address */
498 rc = ioread8(ap->ioaddr.device_addr);
499 rc &= 0xC0;
500 rc |= adev->devno; /* Index select */
501 rc |= (setup << 4) | 0x04;
502 iowrite8(rc, ap->ioaddr.device_addr);
503
504 /* Load the read timings */
505 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
506
507 /* Ensure the timing register mode is right */
508 rc = ioread8(ap->ioaddr.lbal_addr);
509 rc &= 0x73;
510 rc |= 0x84;
511 iowrite8(rc, ap->ioaddr.lbal_addr);
512
513 /* Exit command mode */
514 iowrite8(0x83, ap->ioaddr.nsect_addr);
515}
516
517
518static struct ata_port_operations opti82c611a_port_ops = {
519 .inherits = &legacy_base_port_ops,
520 .set_piomode = opti82c611a_set_piomode,
521};
522
523/*
524 * Opti 82C465MV
525 *
526 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
527 * version is dual channel but doesn't have a lot of unique registers.
528 */
529
530static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
531{
532 u8 active, recover, setup;
533 struct ata_timing t;
534 struct ata_device *pair = ata_dev_pair(adev);
535 int clock;
536 int khz[4] = { 50000, 40000, 33000, 25000 };
537 u8 rc;
538 u8 sysclk;
539
540 /* Get the clock */
541 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
542
543 /* Enter configuration mode */
544 ioread16(ap->ioaddr.error_addr);
545 ioread16(ap->ioaddr.error_addr);
546 iowrite8(3, ap->ioaddr.nsect_addr);
547
548 /* Read VLB clock strapping */
549 clock = 1000000000 / khz[sysclk];
550
551 /* Get the timing data in cycles */
552 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
553
554 /* Setup timing is shared */
555 if (pair) {
556 struct ata_timing tp;
557 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
558
559 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
560 }
561
562 active = clamp_val(t.active, 2, 17) - 2;
563 recover = clamp_val(t.recover, 1, 16) - 1;
564 setup = clamp_val(t.setup, 1, 4) - 1;
565
566 /* Select the right timing bank for write timing */
567 rc = ioread8(ap->ioaddr.lbal_addr);
568 rc &= 0x7F;
569 rc |= (adev->devno << 7);
570 iowrite8(rc, ap->ioaddr.lbal_addr);
571
572 /* Write the timings */
573 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
574
575 /* Select the right bank for read timings, also
576 load the shared timings for address */
577 rc = ioread8(ap->ioaddr.device_addr);
578 rc &= 0xC0;
579 rc |= adev->devno; /* Index select */
580 rc |= (setup << 4) | 0x04;
581 iowrite8(rc, ap->ioaddr.device_addr);
582
583 /* Load the read timings */
584 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
585
586 /* Ensure the timing register mode is right */
587 rc = ioread8(ap->ioaddr.lbal_addr);
588 rc &= 0x73;
589 rc |= 0x84;
590 iowrite8(rc, ap->ioaddr.lbal_addr);
591
592 /* Exit command mode */
593 iowrite8(0x83, ap->ioaddr.nsect_addr);
594
595 /* We need to know this for quad device on the MVB */
596 ap->host->private_data = ap;
597}
598
599/**
600 * opt82c465mv_qc_issue - command issue
601 * @qc: command pending
602 *
603 * Called when the libata layer is about to issue a command. We wrap
604 * this interface so that we can load the correct ATA timings. The
605 * MVB has a single set of timing registers and these are shared
606 * across channels. As there are two registers we really ought to
607 * track the last two used values as a sort of register window. For
608 * now we just reload on a channel switch. On the single channel
609 * setup this condition never fires so we do nothing extra.
610 *
611 * FIXME: dual channel needs ->serialize support
612 */
613
614static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
615{
616 struct ata_port *ap = qc->ap;
617 struct ata_device *adev = qc->dev;
618
619 /* If timings are set and for the wrong channel (2nd test is
620 due to a libata shortcoming and will eventually go I hope) */
621 if (ap->host->private_data != ap->host
622 && ap->host->private_data != NULL)
623 opti82c46x_set_piomode(ap, adev);
624
625 return ata_sff_qc_issue(qc);
626}
627
628static struct ata_port_operations opti82c46x_port_ops = {
629 .inherits = &legacy_base_port_ops,
630 .set_piomode = opti82c46x_set_piomode,
631 .qc_issue = opti82c46x_qc_issue,
632};
633
634static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
635{
636 struct ata_timing t;
637 struct legacy_data *ld_qdi = ap->host->private_data;
638 int active, recovery;
639 u8 timing;
640
641 /* Get the timing data in cycles */
642 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
643
644 if (ld_qdi->fast) {
645 active = 8 - clamp_val(t.active, 1, 8);
646 recovery = 18 - clamp_val(t.recover, 3, 18);
647 } else {
648 active = 9 - clamp_val(t.active, 2, 9);
649 recovery = 15 - clamp_val(t.recover, 0, 15);
650 }
651 timing = (recovery << 4) | active | 0x08;
652
653 ld_qdi->clock[adev->devno] = timing;
654
655 outb(timing, ld_qdi->timing);
656}
657
658/**
659 * qdi6580dp_set_piomode - PIO setup for dual channel
660 * @ap: Port
661 * @adev: Device
662 *
663 * In dual channel mode the 6580 has one clock per channel and we have
664 * to software clockswitch in qc_issue.
665 */
666
667static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
668{
669 struct ata_timing t;
670 struct legacy_data *ld_qdi = ap->host->private_data;
671 int active, recovery;
672 u8 timing;
673
674 /* Get the timing data in cycles */
675 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
676
677 if (ld_qdi->fast) {
678 active = 8 - clamp_val(t.active, 1, 8);
679 recovery = 18 - clamp_val(t.recover, 3, 18);
680 } else {
681 active = 9 - clamp_val(t.active, 2, 9);
682 recovery = 15 - clamp_val(t.recover, 0, 15);
683 }
684 timing = (recovery << 4) | active | 0x08;
685
686 ld_qdi->clock[adev->devno] = timing;
687
688 outb(timing, ld_qdi->timing + 2 * ap->port_no);
689 /* Clear the FIFO */
690 if (adev->class != ATA_DEV_ATA)
691 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
692}
693
694/**
695 * qdi6580_set_piomode - PIO setup for single channel
696 * @ap: Port
697 * @adev: Device
698 *
699 * In single channel mode the 6580 has one clock per device and we can
700 * avoid the requirement to clock switch. We also have to load the timing
701 * into the right clock according to whether we are master or slave.
702 */
703
704static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
705{
706 struct ata_timing t;
707 struct legacy_data *ld_qdi = ap->host->private_data;
708 int active, recovery;
709 u8 timing;
710
711 /* Get the timing data in cycles */
712 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
713
714 if (ld_qdi->fast) {
715 active = 8 - clamp_val(t.active, 1, 8);
716 recovery = 18 - clamp_val(t.recover, 3, 18);
717 } else {
718 active = 9 - clamp_val(t.active, 2, 9);
719 recovery = 15 - clamp_val(t.recover, 0, 15);
720 }
721 timing = (recovery << 4) | active | 0x08;
722 ld_qdi->clock[adev->devno] = timing;
723 outb(timing, ld_qdi->timing + 2 * adev->devno);
724 /* Clear the FIFO */
725 if (adev->class != ATA_DEV_ATA)
726 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
727}
728
729/**
730 * qdi_qc_issue - command issue
731 * @qc: command pending
732 *
733 * Called when the libata layer is about to issue a command. We wrap
734 * this interface so that we can load the correct ATA timings.
735 */
736
737static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
738{
739 struct ata_port *ap = qc->ap;
740 struct ata_device *adev = qc->dev;
741 struct legacy_data *ld_qdi = ap->host->private_data;
742
743 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
744 if (adev->pio_mode) {
745 ld_qdi->last = ld_qdi->clock[adev->devno];
746 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
747 2 * ap->port_no);
748 }
749 }
750 return ata_sff_qc_issue(qc);
751}
752
753static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
754 unsigned int buflen, int rw)
755{
756 struct ata_port *ap = adev->link->ap;
757 int slop = buflen & 3;
758
759 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
760 && (ap->pflags & ATA_PFLAG_PIO32)) {
761 if (rw == WRITE)
762 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
763 else
764 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
765
766 if (unlikely(slop)) {
767 __le32 pad;
768 if (rw == WRITE) {
769 memcpy(&pad, buf + buflen - slop, slop);
770 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
771 } else {
772 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
773 memcpy(buf + buflen - slop, &pad, slop);
774 }
775 }
776 return (buflen + 3) & ~3;
777 } else
778 return ata_sff_data_xfer(adev, buf, buflen, rw);
779}
780
781static int qdi_port(struct platform_device *dev,
782 struct legacy_probe *lp, struct legacy_data *ld)
783{
784 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
785 return -EBUSY;
786 ld->timing = lp->private;
787 return 0;
788}
789
790static struct ata_port_operations qdi6500_port_ops = {
791 .inherits = &legacy_base_port_ops,
792 .set_piomode = qdi6500_set_piomode,
793 .qc_issue = qdi_qc_issue,
794 .sff_data_xfer = vlb32_data_xfer,
795};
796
797static struct ata_port_operations qdi6580_port_ops = {
798 .inherits = &legacy_base_port_ops,
799 .set_piomode = qdi6580_set_piomode,
800 .sff_data_xfer = vlb32_data_xfer,
801};
802
803static struct ata_port_operations qdi6580dp_port_ops = {
804 .inherits = &legacy_base_port_ops,
805 .set_piomode = qdi6580dp_set_piomode,
806 .qc_issue = qdi_qc_issue,
807 .sff_data_xfer = vlb32_data_xfer,
808};
809
810static DEFINE_SPINLOCK(winbond_lock);
811
812static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
813{
814 unsigned long flags;
815 spin_lock_irqsave(&winbond_lock, flags);
816 outb(reg, port + 0x01);
817 outb(val, port + 0x02);
818 spin_unlock_irqrestore(&winbond_lock, flags);
819}
820
821static u8 winbond_readcfg(unsigned long port, u8 reg)
822{
823 u8 val;
824
825 unsigned long flags;
826 spin_lock_irqsave(&winbond_lock, flags);
827 outb(reg, port + 0x01);
828 val = inb(port + 0x02);
829 spin_unlock_irqrestore(&winbond_lock, flags);
830
831 return val;
832}
833
834static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
835{
836 struct ata_timing t;
837 struct legacy_data *ld_winbond = ap->host->private_data;
838 int active, recovery;
839 u8 reg;
840 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
841
842 reg = winbond_readcfg(ld_winbond->timing, 0x81);
843
844 /* Get the timing data in cycles */
845 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
846 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
847 else
848 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
849
850 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
851 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
852 timing = (active << 4) | recovery;
853 winbond_writecfg(ld_winbond->timing, timing, reg);
854
855 /* Load the setup timing */
856
857 reg = 0x35;
858 if (adev->class != ATA_DEV_ATA)
859 reg |= 0x08; /* FIFO off */
860 if (!ata_pio_need_iordy(adev))
861 reg |= 0x02; /* IORDY off */
862 reg |= (clamp_val(t.setup, 0, 3) << 6);
863 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
864}
865
866static int winbond_port(struct platform_device *dev,
867 struct legacy_probe *lp, struct legacy_data *ld)
868{
869 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
870 return -EBUSY;
871 ld->timing = lp->private;
872 return 0;
873}
874
875static struct ata_port_operations winbond_port_ops = {
876 .inherits = &legacy_base_port_ops,
877 .set_piomode = winbond_set_piomode,
878 .sff_data_xfer = vlb32_data_xfer,
879};
880
881static struct legacy_controller controllers[] = {
882 {"BIOS", &legacy_port_ops, 0x1F,
883 ATA_FLAG_NO_IORDY, 0, NULL },
884 {"Snooping", &simple_port_ops, 0x1F,
885 0, 0, NULL },
886 {"PDC20230", &pdc20230_port_ops, 0x7,
887 ATA_FLAG_NO_IORDY,
888 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
889 {"HT6560A", &ht6560a_port_ops, 0x07,
890 ATA_FLAG_NO_IORDY, 0, NULL },
891 {"HT6560B", &ht6560b_port_ops, 0x1F,
892 ATA_FLAG_NO_IORDY, 0, NULL },
893 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F,
894 0, 0, NULL },
895 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F,
896 0, 0, NULL },
897 {"QDI6500", &qdi6500_port_ops, 0x07,
898 ATA_FLAG_NO_IORDY,
899 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
900 {"QDI6580", &qdi6580_port_ops, 0x1F,
901 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
902 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F,
903 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
904 {"W83759A", &winbond_port_ops, 0x1F,
905 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
906 winbond_port }
907};
908
909/**
910 * probe_chip_type - Discover controller
911 * @probe: Probe entry to check
912 *
913 * Probe an ATA port and identify the type of controller. We don't
914 * check if the controller appears to be driveless at this point.
915 */
916
917static __init int probe_chip_type(struct legacy_probe *probe)
918{
919 int mask = 1 << probe->slot;
920
921 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
922 u8 reg = winbond_readcfg(winbond, 0x81);
923 reg |= 0x80; /* jumpered mode off */
924 winbond_writecfg(winbond, 0x81, reg);
925 reg = winbond_readcfg(winbond, 0x83);
926 reg |= 0xF0; /* local control */
927 winbond_writecfg(winbond, 0x83, reg);
928 reg = winbond_readcfg(winbond, 0x85);
929 reg |= 0xF0; /* programmable timing */
930 winbond_writecfg(winbond, 0x85, reg);
931
932 reg = winbond_readcfg(winbond, 0x81);
933
934 if (reg & mask)
935 return W83759A;
936 }
937 if (probe->port == 0x1F0) {
938 unsigned long flags;
939 local_irq_save(flags);
940 /* Probes */
941 outb(inb(0x1F2) | 0x80, 0x1F2);
942 inb(0x1F5);
943 inb(0x1F2);
944 inb(0x3F6);
945 inb(0x3F6);
946 inb(0x1F2);
947 inb(0x1F2);
948
949 if ((inb(0x1F2) & 0x80) == 0) {
950 /* PDC20230c or 20630 ? */
951 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
952 " detected.\n");
953 udelay(100);
954 inb(0x1F5);
955 local_irq_restore(flags);
956 return PDC20230;
957 } else {
958 outb(0x55, 0x1F2);
959 inb(0x1F2);
960 inb(0x1F2);
961 if (inb(0x1F2) == 0x00)
962 printk(KERN_INFO "PDC20230-B VLB ATA "
963 "controller detected.\n");
964 local_irq_restore(flags);
965 return BIOS;
966 }
967 local_irq_restore(flags);
968 }
969
970 if (ht6560a & mask)
971 return HT6560A;
972 if (ht6560b & mask)
973 return HT6560B;
974 if (opti82c611a & mask)
975 return OPTI611A;
976 if (opti82c46x & mask)
977 return OPTI46X;
978 if (autospeed & mask)
979 return SNOOP;
980 return BIOS;
981}
982
983
984/**
985 * legacy_init_one - attach a legacy interface
986 * @pl: probe record
987 *
988 * Register an ISA bus IDE interface. Such interfaces are PIO and we
989 * assume do not support IRQ sharing.
990 */
991
992static __init int legacy_init_one(struct legacy_probe *probe)
993{
994 struct legacy_controller *controller = &controllers[probe->type];
995 int pio_modes = controller->pio_mask;
996 unsigned long io = probe->port;
997 u32 mask = (1 << probe->slot);
998 struct ata_port_operations *ops = controller->ops;
999 struct legacy_data *ld = &legacy_data[probe->slot];
1000 struct ata_host *host = NULL;
1001 struct ata_port *ap;
1002 struct platform_device *pdev;
1003 struct ata_device *dev;
1004 void __iomem *io_addr, *ctrl_addr;
1005 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
1006 int ret;
1007
1008 iordy |= controller->flags;
1009
1010 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
1011 if (IS_ERR(pdev))
1012 return PTR_ERR(pdev);
1013
1014 ret = -EBUSY;
1015 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
1016 devm_request_region(&pdev->dev, io + 0x0206, 1,
1017 "pata_legacy") == NULL)
1018 goto fail;
1019
1020 ret = -ENOMEM;
1021 io_addr = devm_ioport_map(&pdev->dev, io, 8);
1022 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
1023 if (!io_addr || !ctrl_addr)
1024 goto fail;
1025 if (controller->setup)
1026 if (controller->setup(pdev, probe, ld) < 0)
1027 goto fail;
1028 host = ata_host_alloc(&pdev->dev, 1);
1029 if (!host)
1030 goto fail;
1031 ap = host->ports[0];
1032
1033 ap->ops = ops;
1034 ap->pio_mask = pio_modes;
1035 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
1036 ap->pflags |= controller->pflags;
1037 ap->ioaddr.cmd_addr = io_addr;
1038 ap->ioaddr.altstatus_addr = ctrl_addr;
1039 ap->ioaddr.ctl_addr = ctrl_addr;
1040 ata_sff_std_ports(&ap->ioaddr);
1041 ap->host->private_data = ld;
1042
1043 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1044
1045 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
1046 &legacy_sht);
1047 if (ret)
1048 goto fail;
1049 async_synchronize_full();
1050 ld->platform_dev = pdev;
1051
1052 /* Nothing found means we drop the port as its probably not there */
1053
1054 ret = -ENODEV;
1055 ata_for_each_dev(dev, &ap->link, ALL) {
1056 if (!ata_dev_absent(dev)) {
1057 legacy_host[probe->slot] = host;
1058 ld->platform_dev = pdev;
1059 return 0;
1060 }
1061 }
1062 ata_host_detach(host);
1063fail:
1064 platform_device_unregister(pdev);
1065 return ret;
1066}
1067
1068/**
1069 * legacy_check_special_cases - ATA special cases
1070 * @p: PCI device to check
1071 * @master: set this if we find an ATA master
1072 * @master: set this if we find an ATA secondary
1073 *
1074 * A small number of vendors implemented early PCI ATA interfaces
1075 * on bridge logic without the ATA interface being PCI visible.
1076 * Where we have a matching PCI driver we must skip the relevant
1077 * device here. If we don't know about it then the legacy driver
1078 * is the right driver anyway.
1079 */
1080
1081static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1082 int *secondary)
1083{
1084 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1085 if (p->vendor == 0x1078 && p->device == 0x0000) {
1086 *primary = *secondary = 1;
1087 return;
1088 }
1089 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1090 if (p->vendor == 0x1078 && p->device == 0x0002) {
1091 *primary = *secondary = 1;
1092 return;
1093 }
1094 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1095 if (p->vendor == 0x8086 && p->device == 0x1234) {
1096 u16 r;
1097 pci_read_config_word(p, 0x6C, &r);
1098 if (r & 0x8000) {
1099 /* ATA port enabled */
1100 if (r & 0x4000)
1101 *secondary = 1;
1102 else
1103 *primary = 1;
1104 }
1105 return;
1106 }
1107}
1108
1109static __init void probe_opti_vlb(void)
1110{
1111 /* If an OPTI 82C46X is present find out where the channels are */
1112 static const char *optis[4] = {
1113 "3/463MV", "5MV",
1114 "5MVA", "5MVB"
1115 };
1116 u8 chans = 1;
1117 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1118
1119 opti82c46x = 3; /* Assume master and slave first */
1120 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1121 optis[ctrl]);
1122 if (ctrl == 3)
1123 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1124 ctrl = opti_syscfg(0xAC);
1125 /* Check enabled and this port is the 465MV port. On the
1126 MVB we may have two channels */
1127 if (ctrl & 8) {
1128 if (chans == 2) {
1129 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1130 legacy_probe_add(0x170, 15, OPTI46X, 0);
1131 }
1132 if (ctrl & 4)
1133 legacy_probe_add(0x170, 15, OPTI46X, 0);
1134 else
1135 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1136 } else
1137 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1138}
1139
1140static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1141{
1142 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1143 /* Check card type */
1144 if ((r & 0xF0) == 0xC0) {
1145 /* QD6500: single channel */
1146 if (r & 8)
1147 /* Disabled ? */
1148 return;
1149 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1150 QDI6500, port);
1151 }
1152 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1153 /* QD6580: dual channel */
1154 if (!request_region(port + 2 , 2, "pata_qdi")) {
1155 release_region(port, 2);
1156 return;
1157 }
1158 res = inb(port + 3);
1159 /* Single channel mode ? */
1160 if (res & 1)
1161 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1162 QDI6580, port);
1163 else { /* Dual channel mode */
1164 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1165 /* port + 0x02, r & 0x04 */
1166 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1167 }
1168 release_region(port + 2, 2);
1169 }
1170}
1171
1172static __init void probe_qdi_vlb(void)
1173{
1174 unsigned long flags;
1175 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1176 int i;
1177
1178 /*
1179 * Check each possible QD65xx base address
1180 */
1181
1182 for (i = 0; i < 2; i++) {
1183 unsigned long port = qd_port[i];
1184 u8 r, res;
1185
1186
1187 if (request_region(port, 2, "pata_qdi")) {
1188 /* Check for a card */
1189 local_irq_save(flags);
1190 /* I have no h/w that needs this delay but it
1191 is present in the historic code */
1192 r = inb(port);
1193 udelay(1);
1194 outb(0x19, port);
1195 udelay(1);
1196 res = inb(port);
1197 udelay(1);
1198 outb(r, port);
1199 udelay(1);
1200 local_irq_restore(flags);
1201
1202 /* Fail */
1203 if (res == 0x19) {
1204 release_region(port, 2);
1205 continue;
1206 }
1207 /* Passes the presence test */
1208 r = inb(port + 1);
1209 udelay(1);
1210 /* Check port agrees with port set */
1211 if ((r & 2) >> 1 == i)
1212 qdi65_identify_port(r, res, port);
1213 release_region(port, 2);
1214 }
1215 }
1216}
1217
1218/**
1219 * legacy_init - attach legacy interfaces
1220 *
1221 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1222 * Right now we do not scan the ide0 and ide1 address but should do so
1223 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1224 * If you fix that note there are special cases to consider like VLB
1225 * drivers and CS5510/20.
1226 */
1227
1228static __init int legacy_init(void)
1229{
1230 int i;
1231 int ct = 0;
1232 int primary = 0;
1233 int secondary = 0;
1234 int pci_present = 0;
1235 struct legacy_probe *pl = &probe_list[0];
1236 int slot = 0;
1237
1238 struct pci_dev *p = NULL;
1239
1240 for_each_pci_dev(p) {
1241 int r;
1242 /* Check for any overlap of the system ATA mappings. Native
1243 mode controllers stuck on these addresses or some devices
1244 in 'raid' mode won't be found by the storage class test */
1245 for (r = 0; r < 6; r++) {
1246 if (pci_resource_start(p, r) == 0x1f0)
1247 primary = 1;
1248 if (pci_resource_start(p, r) == 0x170)
1249 secondary = 1;
1250 }
1251 /* Check for special cases */
1252 legacy_check_special_cases(p, &primary, &secondary);
1253
1254 /* If PCI bus is present then don't probe for tertiary
1255 legacy ports */
1256 pci_present = 1;
1257 }
1258
1259 if (winbond == 1)
1260 winbond = 0x130; /* Default port, alt is 1B0 */
1261
1262 if (primary == 0 || all)
1263 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1264 if (secondary == 0 || all)
1265 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1266
1267 if (probe_all || !pci_present) {
1268 /* ISA/VLB extra ports */
1269 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1270 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1271 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1272 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1273 }
1274
1275 if (opti82c46x)
1276 probe_opti_vlb();
1277 if (qdi)
1278 probe_qdi_vlb();
1279
1280 for (i = 0; i < NR_HOST; i++, pl++) {
1281 if (pl->port == 0)
1282 continue;
1283 if (pl->type == UNKNOWN)
1284 pl->type = probe_chip_type(pl);
1285 pl->slot = slot++;
1286 if (legacy_init_one(pl) == 0)
1287 ct++;
1288 }
1289 if (ct != 0)
1290 return 0;
1291 return -ENODEV;
1292}
1293
1294static __exit void legacy_exit(void)
1295{
1296 int i;
1297
1298 for (i = 0; i < nr_legacy_host; i++) {
1299 struct legacy_data *ld = &legacy_data[i];
1300 ata_host_detach(legacy_host[i]);
1301 platform_device_unregister(ld->platform_dev);
1302 }
1303}
1304
1305MODULE_AUTHOR("Alan Cox");
1306MODULE_DESCRIPTION("low-level driver for legacy ATA");
1307MODULE_LICENSE("GPL");
1308MODULE_VERSION(DRV_VERSION);
1309MODULE_ALIAS("pata_winbond");
1310
1311module_param(probe_all, int, 0);
1312module_param(autospeed, int, 0);
1313module_param(ht6560a, int, 0);
1314module_param(ht6560b, int, 0);
1315module_param(opti82c611a, int, 0);
1316module_param(opti82c46x, int, 0);
1317module_param(qdi, int, 0);
1318module_param(winbond, int, 0);
1319module_param(pio_mask, int, 0);
1320module_param(iordy_mask, int, 0);
1321
1322module_init(legacy_init);
1323module_exit(legacy_exit);