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1/*
2 * PATA driver for AT91SAM9260 Static Memory Controller
3 * with CompactFlash interface in True IDE mode
4 *
5 * Copyright (C) 2009 Matyukevich Sergey
6 * 2011 Igor Plyatov
7 *
8 * Based on:
9 * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
10 * * pata_at32 driver by Kristoffer Nyborg Gregertsen
11 * * at91_ide driver by Stanislaw Gruszka
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/blkdev.h>
22#include <linux/gfp.h>
23#include <scsi/scsi_host.h>
24#include <linux/ata.h>
25#include <linux/clk.h>
26#include <linux/libata.h>
27#include <linux/mfd/syscon.h>
28#include <linux/mfd/syscon/atmel-smc.h>
29#include <linux/platform_device.h>
30#include <linux/ata_platform.h>
31#include <linux/platform_data/atmel.h>
32#include <linux/regmap.h>
33#include <linux/gpio.h>
34
35#define DRV_NAME "pata_at91"
36#define DRV_VERSION "0.3"
37
38#define CF_IDE_OFFSET 0x00c00000
39#define CF_ALT_IDE_OFFSET 0x00e00000
40#define CF_IDE_RES_SIZE 0x08
41#define CS_PULSE_MAXIMUM 319
42#define ER_SMC_CALC 1
43#define ER_SMC_RECALC 2
44
45struct at91_ide_info {
46 unsigned long mode;
47 unsigned int cs;
48 struct clk *mck;
49 void __iomem *ide_addr;
50 void __iomem *alt_addr;
51};
52
53/**
54 * struct smc_range - range of valid values for SMC register.
55 */
56struct smc_range {
57 int min;
58 int max;
59};
60
61struct regmap *smc;
62
63struct at91sam9_smc_generic_fields {
64 struct regmap_field *setup;
65 struct regmap_field *pulse;
66 struct regmap_field *cycle;
67 struct regmap_field *mode;
68} fields;
69
70/**
71 * adjust_smc_value - adjust value for one of SMC registers.
72 * @value: adjusted value
73 * @range: array of SMC ranges with valid values
74 * @size: SMC ranges array size
75 *
76 * This returns the difference between input and output value or negative
77 * in case of invalid input value.
78 * If negative returned, then output value = maximal possible from ranges.
79 */
80static int adjust_smc_value(int *value, struct smc_range *range, int size)
81{
82 int maximum = (range + size - 1)->max;
83 int remainder;
84
85 do {
86 if (*value < range->min) {
87 remainder = range->min - *value;
88 *value = range->min; /* nearest valid value */
89 return remainder;
90 } else if ((range->min <= *value) && (*value <= range->max))
91 return 0;
92
93 range++;
94 } while (--size);
95 *value = maximum;
96
97 return -1; /* invalid value */
98}
99
100/**
101 * calc_smc_vals - calculate SMC register values
102 * @dev: ATA device
103 * @setup: SMC_SETUP register value
104 * @pulse: SMC_PULSE register value
105 * @cycle: SMC_CYCLE register value
106 *
107 * This returns negative in case of invalid values for SMC registers:
108 * -ER_SMC_RECALC - recalculation required for SMC values,
109 * -ER_SMC_CALC - calculation failed (invalid input values).
110 *
111 * SMC use special coding scheme, see "Coding and Range of Timing
112 * Parameters" table from AT91SAM9 datasheets.
113 *
114 * SMC_SETUP = 128*setup[5] + setup[4:0]
115 * SMC_PULSE = 256*pulse[6] + pulse[5:0]
116 * SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
117 */
118static int calc_smc_vals(struct device *dev,
119 int *setup, int *pulse, int *cycle, int *cs_pulse)
120{
121 int ret_val;
122 int err = 0;
123 struct smc_range range_setup[] = { /* SMC_SETUP valid values */
124 {.min = 0, .max = 31}, /* first range */
125 {.min = 128, .max = 159} /* second range */
126 };
127 struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
128 {.min = 0, .max = 63}, /* first range */
129 {.min = 256, .max = 319} /* second range */
130 };
131 struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
132 {.min = 0, .max = 127}, /* first range */
133 {.min = 256, .max = 383}, /* second range */
134 {.min = 512, .max = 639}, /* third range */
135 {.min = 768, .max = 895} /* fourth range */
136 };
137
138 ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
139 if (ret_val < 0)
140 dev_warn(dev, "maximal SMC Setup value\n");
141 else
142 *cycle += ret_val;
143
144 ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
145 if (ret_val < 0)
146 dev_warn(dev, "maximal SMC Pulse value\n");
147 else
148 *cycle += ret_val;
149
150 ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
151 if (ret_val < 0)
152 dev_warn(dev, "maximal SMC Cycle value\n");
153
154 *cs_pulse = *cycle;
155 if (*cs_pulse > CS_PULSE_MAXIMUM) {
156 dev_err(dev, "unable to calculate valid SMC settings\n");
157 return -ER_SMC_CALC;
158 }
159
160 ret_val = adjust_smc_value(cs_pulse, range_pulse,
161 ARRAY_SIZE(range_pulse));
162 if (ret_val < 0) {
163 dev_warn(dev, "maximal SMC CS Pulse value\n");
164 } else if (ret_val != 0) {
165 *cycle = *cs_pulse;
166 dev_warn(dev, "SMC Cycle extended\n");
167 err = -ER_SMC_RECALC;
168 }
169
170 return err;
171}
172
173/**
174 * to_smc_format - convert values into SMC format
175 * @setup: SETUP value of SMC Setup Register
176 * @pulse: PULSE value of SMC Pulse Register
177 * @cycle: CYCLE value of SMC Cycle Register
178 * @cs_pulse: NCS_PULSE value of SMC Pulse Register
179 */
180static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
181{
182 *setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
183 *pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
184 *cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
185 *cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
186}
187
188static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
189{
190 unsigned long mul;
191
192 /*
193 * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
194 * x * (f / 1_000_000_000) =
195 * x * ((f * 65536) / 1_000_000_000) / 65536 =
196 * x * (((f / 10_000) * 65536) / 100_000) / 65536 =
197 */
198
199 mul = (mck_hz / 10000) << 16;
200 mul /= 100000;
201
202 return (ns * mul + 65536) >> 16; /* rounding */
203}
204
205/**
206 * set_smc_timing - SMC timings setup.
207 * @dev: device
208 * @info: AT91 IDE info
209 * @ata: ATA timings
210 *
211 * Its assumed that write timings are same as read timings,
212 * cs_setup = 0 and cs_pulse = cycle.
213 */
214static void set_smc_timing(struct device *dev, struct ata_device *adev,
215 struct at91_ide_info *info, const struct ata_timing *ata)
216{
217 int ret = 0;
218 int use_iordy;
219 unsigned int t6z; /* data tristate time in ns */
220 unsigned int cycle; /* SMC Cycle width in MCK ticks */
221 unsigned int setup; /* SMC Setup width in MCK ticks */
222 unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
223 unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
224 unsigned int tdf_cycles; /* SMC TDF MCK ticks */
225 unsigned long mck_hz; /* MCK frequency in Hz */
226
227 t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
228 mck_hz = clk_get_rate(info->mck);
229 cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
230 setup = calc_mck_cycles(ata->setup, mck_hz);
231 pulse = calc_mck_cycles(ata->act8b, mck_hz);
232 tdf_cycles = calc_mck_cycles(t6z, mck_hz);
233
234 do {
235 ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
236 } while (ret == -ER_SMC_RECALC);
237
238 if (ret == -ER_SMC_CALC)
239 dev_err(dev, "Interface may not operate correctly\n");
240
241 dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
242 setup, pulse, cycle, cs_pulse);
243 to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
244 /* disable or enable waiting for IORDY signal */
245 use_iordy = ata_pio_need_iordy(adev);
246 if (use_iordy)
247 info->mode |= AT91_SMC_EXNWMODE_READY;
248
249 if (tdf_cycles > 15) {
250 tdf_cycles = 15;
251 dev_warn(dev, "maximal SMC TDF Cycles value\n");
252 }
253
254 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
255
256 regmap_fields_write(fields.setup, info->cs,
257 AT91SAM9_SMC_NRDSETUP(setup) |
258 AT91SAM9_SMC_NWESETUP(setup) |
259 AT91SAM9_SMC_NCS_NRDSETUP(0) |
260 AT91SAM9_SMC_NCS_WRSETUP(0));
261 regmap_fields_write(fields.pulse, info->cs,
262 AT91SAM9_SMC_NRDPULSE(pulse) |
263 AT91SAM9_SMC_NWEPULSE(pulse) |
264 AT91SAM9_SMC_NCS_NRDPULSE(cs_pulse) |
265 AT91SAM9_SMC_NCS_WRPULSE(cs_pulse));
266 regmap_fields_write(fields.cycle, info->cs,
267 AT91SAM9_SMC_NRDCYCLE(cycle) |
268 AT91SAM9_SMC_NWECYCLE(cycle));
269 regmap_fields_write(fields.mode, info->cs, info->mode |
270 AT91_SMC_TDF_(tdf_cycles));
271}
272
273static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
274{
275 struct at91_ide_info *info = ap->host->private_data;
276 struct ata_timing timing;
277 int ret;
278
279 /* Compute ATA timing and set it to SMC */
280 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
281 if (ret) {
282 dev_warn(ap->dev, "Failed to compute ATA timing %d, "
283 "set PIO_0 timing\n", ret);
284 timing = *ata_timing_find_mode(XFER_PIO_0);
285 }
286 set_smc_timing(ap->dev, adev, info, &timing);
287}
288
289static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
290 unsigned char *buf, unsigned int buflen, int rw)
291{
292 struct at91_ide_info *info = dev->link->ap->host->private_data;
293 unsigned int consumed;
294 unsigned int mode;
295 unsigned long flags;
296
297 local_irq_save(flags);
298 regmap_fields_read(fields.mode, info->cs, &mode);
299
300 /* set 16bit mode before writing data */
301 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
302 AT91_SMC_DBW_16);
303
304 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
305
306 /* restore 8bit mode after data is written */
307 regmap_fields_write(fields.mode, info->cs, (mode & ~AT91_SMC_DBW) |
308 AT91_SMC_DBW_8);
309
310 local_irq_restore(flags);
311 return consumed;
312}
313
314static struct scsi_host_template pata_at91_sht = {
315 ATA_PIO_SHT(DRV_NAME),
316};
317
318static struct ata_port_operations pata_at91_port_ops = {
319 .inherits = &ata_sff_port_ops,
320
321 .sff_data_xfer = pata_at91_data_xfer_noirq,
322 .set_piomode = pata_at91_set_piomode,
323 .cable_detect = ata_cable_40wire,
324};
325
326static int at91sam9_smc_fields_init(struct device *dev)
327{
328 struct reg_field field = REG_FIELD(0, 0, 31);
329
330 field.id_size = 8;
331 field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
332
333 field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
334 fields.setup = devm_regmap_field_alloc(dev, smc, field);
335 if (IS_ERR(fields.setup))
336 return PTR_ERR(fields.setup);
337
338 field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
339 fields.pulse = devm_regmap_field_alloc(dev, smc, field);
340 if (IS_ERR(fields.pulse))
341 return PTR_ERR(fields.pulse);
342
343 field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
344 fields.cycle = devm_regmap_field_alloc(dev, smc, field);
345 if (IS_ERR(fields.cycle))
346 return PTR_ERR(fields.cycle);
347
348 field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
349 fields.mode = devm_regmap_field_alloc(dev, smc, field);
350 if (IS_ERR(fields.mode))
351 return PTR_ERR(fields.mode);
352
353 return 0;
354}
355
356static int pata_at91_probe(struct platform_device *pdev)
357{
358 struct at91_cf_data *board = dev_get_platdata(&pdev->dev);
359 struct device *dev = &pdev->dev;
360 struct at91_ide_info *info;
361 struct resource *mem_res;
362 struct ata_host *host;
363 struct ata_port *ap;
364
365 int irq_flags = 0;
366 int irq = 0;
367 int ret;
368
369 /* get platform resources: IO/CTL memories and irq/rst pins */
370
371 if (pdev->num_resources != 1) {
372 dev_err(&pdev->dev, "invalid number of resources\n");
373 return -EINVAL;
374 }
375
376 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377
378 if (!mem_res) {
379 dev_err(dev, "failed to get mem resource\n");
380 return -EINVAL;
381 }
382
383 irq = board->irq_pin;
384
385 smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "atmel,smc");
386 if (IS_ERR(smc))
387 return PTR_ERR(smc);
388
389 ret = at91sam9_smc_fields_init(dev);
390 if (ret < 0)
391 return ret;
392
393 /* init ata host */
394
395 host = ata_host_alloc(dev, 1);
396
397 if (!host)
398 return -ENOMEM;
399
400 ap = host->ports[0];
401 ap->ops = &pata_at91_port_ops;
402 ap->flags |= ATA_FLAG_SLAVE_POSS;
403 ap->pio_mask = ATA_PIO4;
404
405 if (!gpio_is_valid(irq)) {
406 ap->flags |= ATA_FLAG_PIO_POLLING;
407 ata_port_desc(ap, "no IRQ, using PIO polling");
408 }
409
410 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
411
412 if (!info) {
413 dev_err(dev, "failed to allocate memory for private data\n");
414 return -ENOMEM;
415 }
416
417 info->mck = clk_get(NULL, "mck");
418
419 if (IS_ERR(info->mck)) {
420 dev_err(dev, "failed to get access to mck clock\n");
421 return -ENODEV;
422 }
423
424 info->cs = board->chipselect;
425 info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
426 AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
427 AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);
428
429 info->ide_addr = devm_ioremap(dev,
430 mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
431
432 if (!info->ide_addr) {
433 dev_err(dev, "failed to map IO base\n");
434 ret = -ENOMEM;
435 goto err_put;
436 }
437
438 info->alt_addr = devm_ioremap(dev,
439 mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
440
441 if (!info->alt_addr) {
442 dev_err(dev, "failed to map CTL base\n");
443 ret = -ENOMEM;
444 goto err_put;
445 }
446
447 ap->ioaddr.cmd_addr = info->ide_addr;
448 ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
449 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
450
451 ata_sff_std_ports(&ap->ioaddr);
452
453 ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
454 (unsigned long long)mem_res->start + CF_IDE_OFFSET,
455 (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
456
457 host->private_data = info;
458
459 ret = ata_host_activate(host, gpio_is_valid(irq) ? gpio_to_irq(irq) : 0,
460 gpio_is_valid(irq) ? ata_sff_interrupt : NULL,
461 irq_flags, &pata_at91_sht);
462 if (ret)
463 goto err_put;
464
465 return 0;
466
467err_put:
468 clk_put(info->mck);
469 return ret;
470}
471
472static int pata_at91_remove(struct platform_device *pdev)
473{
474 struct ata_host *host = platform_get_drvdata(pdev);
475 struct at91_ide_info *info;
476
477 if (!host)
478 return 0;
479 info = host->private_data;
480
481 ata_host_detach(host);
482
483 if (!info)
484 return 0;
485
486 clk_put(info->mck);
487
488 return 0;
489}
490
491static struct platform_driver pata_at91_driver = {
492 .probe = pata_at91_probe,
493 .remove = pata_at91_remove,
494 .driver = {
495 .name = DRV_NAME,
496 },
497};
498
499module_platform_driver(pata_at91_driver);
500
501MODULE_LICENSE("GPL");
502MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
503MODULE_AUTHOR("Matyukevich Sergey");
504MODULE_VERSION(DRV_VERSION);
505
1/*
2 * PATA driver for AT91SAM9260 Static Memory Controller
3 * with CompactFlash interface in True IDE mode
4 *
5 * Copyright (C) 2009 Matyukevich Sergey
6 * 2011 Igor Plyatov
7 *
8 * Based on:
9 * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
10 * * pata_at32 driver by Kristoffer Nyborg Gregertsen
11 * * at91_ide driver by Stanislaw Gruszka
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2
15 * as published by the Free Software Foundation.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/gfp.h>
24#include <scsi/scsi_host.h>
25#include <linux/ata.h>
26#include <linux/clk.h>
27#include <linux/libata.h>
28#include <linux/platform_device.h>
29#include <linux/ata_platform.h>
30
31#include <mach/at91sam9_smc.h>
32#include <mach/board.h>
33#include <mach/gpio.h>
34
35#define DRV_NAME "pata_at91"
36#define DRV_VERSION "0.3"
37
38#define CF_IDE_OFFSET 0x00c00000
39#define CF_ALT_IDE_OFFSET 0x00e00000
40#define CF_IDE_RES_SIZE 0x08
41#define CS_PULSE_MAXIMUM 319
42#define ER_SMC_CALC 1
43#define ER_SMC_RECALC 2
44
45struct at91_ide_info {
46 unsigned long mode;
47 unsigned int cs;
48 struct clk *mck;
49 void __iomem *ide_addr;
50 void __iomem *alt_addr;
51};
52
53/**
54 * struct smc_range - range of valid values for SMC register.
55 */
56struct smc_range {
57 int min;
58 int max;
59};
60
61/**
62 * adjust_smc_value - adjust value for one of SMC registers.
63 * @value: adjusted value
64 * @range: array of SMC ranges with valid values
65 * @size: SMC ranges array size
66 *
67 * This returns the difference between input and output value or negative
68 * in case of invalid input value.
69 * If negative returned, then output value = maximal possible from ranges.
70 */
71static int adjust_smc_value(int *value, struct smc_range *range, int size)
72{
73 int maximum = (range + size - 1)->max;
74 int remainder;
75
76 do {
77 if (*value < range->min) {
78 remainder = range->min - *value;
79 *value = range->min; /* nearest valid value */
80 return remainder;
81 } else if ((range->min <= *value) && (*value <= range->max))
82 return 0;
83
84 range++;
85 } while (--size);
86 *value = maximum;
87
88 return -1; /* invalid value */
89}
90
91/**
92 * calc_smc_vals - calculate SMC register values
93 * @dev: ATA device
94 * @setup: SMC_SETUP register value
95 * @pulse: SMC_PULSE register value
96 * @cycle: SMC_CYCLE register value
97 *
98 * This returns negative in case of invalid values for SMC registers:
99 * -ER_SMC_RECALC - recalculation required for SMC values,
100 * -ER_SMC_CALC - calculation failed (invalid input values).
101 *
102 * SMC use special coding scheme, see "Coding and Range of Timing
103 * Parameters" table from AT91SAM9 datasheets.
104 *
105 * SMC_SETUP = 128*setup[5] + setup[4:0]
106 * SMC_PULSE = 256*pulse[6] + pulse[5:0]
107 * SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
108 */
109static int calc_smc_vals(struct device *dev,
110 int *setup, int *pulse, int *cycle, int *cs_pulse)
111{
112 int ret_val;
113 int err = 0;
114 struct smc_range range_setup[] = { /* SMC_SETUP valid values */
115 {.min = 0, .max = 31}, /* first range */
116 {.min = 128, .max = 159} /* second range */
117 };
118 struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
119 {.min = 0, .max = 63}, /* first range */
120 {.min = 256, .max = 319} /* second range */
121 };
122 struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
123 {.min = 0, .max = 127}, /* first range */
124 {.min = 256, .max = 383}, /* second range */
125 {.min = 512, .max = 639}, /* third range */
126 {.min = 768, .max = 895} /* fourth range */
127 };
128
129 ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
130 if (ret_val < 0)
131 dev_warn(dev, "maximal SMC Setup value\n");
132 else
133 *cycle += ret_val;
134
135 ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
136 if (ret_val < 0)
137 dev_warn(dev, "maximal SMC Pulse value\n");
138 else
139 *cycle += ret_val;
140
141 ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
142 if (ret_val < 0)
143 dev_warn(dev, "maximal SMC Cycle value\n");
144
145 *cs_pulse = *cycle;
146 if (*cs_pulse > CS_PULSE_MAXIMUM) {
147 dev_err(dev, "unable to calculate valid SMC settings\n");
148 return -ER_SMC_CALC;
149 }
150
151 ret_val = adjust_smc_value(cs_pulse, range_pulse,
152 ARRAY_SIZE(range_pulse));
153 if (ret_val < 0) {
154 dev_warn(dev, "maximal SMC CS Pulse value\n");
155 } else if (ret_val != 0) {
156 *cycle = *cs_pulse;
157 dev_warn(dev, "SMC Cycle extended\n");
158 err = -ER_SMC_RECALC;
159 }
160
161 return err;
162}
163
164/**
165 * to_smc_format - convert values into SMC format
166 * @setup: SETUP value of SMC Setup Register
167 * @pulse: PULSE value of SMC Pulse Register
168 * @cycle: CYCLE value of SMC Cycle Register
169 * @cs_pulse: NCS_PULSE value of SMC Pulse Register
170 */
171static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
172{
173 *setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
174 *pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
175 *cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
176 *cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
177}
178
179static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
180{
181 unsigned long mul;
182
183 /*
184 * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] =
185 * x * (f / 1_000_000_000) =
186 * x * ((f * 65536) / 1_000_000_000) / 65536 =
187 * x * (((f / 10_000) * 65536) / 100_000) / 65536 =
188 */
189
190 mul = (mck_hz / 10000) << 16;
191 mul /= 100000;
192
193 return (ns * mul + 65536) >> 16; /* rounding */
194}
195
196/**
197 * set_smc_timing - SMC timings setup.
198 * @dev: device
199 * @info: AT91 IDE info
200 * @ata: ATA timings
201 *
202 * Its assumed that write timings are same as read timings,
203 * cs_setup = 0 and cs_pulse = cycle.
204 */
205static void set_smc_timing(struct device *dev, struct ata_device *adev,
206 struct at91_ide_info *info, const struct ata_timing *ata)
207{
208 int ret = 0;
209 int use_iordy;
210 unsigned int t6z; /* data tristate time in ns */
211 unsigned int cycle; /* SMC Cycle width in MCK ticks */
212 unsigned int setup; /* SMC Setup width in MCK ticks */
213 unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
214 unsigned int cs_setup = 0;/* CS4 or CS5 setup width in MCK ticks */
215 unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
216 unsigned int tdf_cycles; /* SMC TDF MCK ticks */
217 unsigned long mck_hz; /* MCK frequency in Hz */
218
219 t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
220 mck_hz = clk_get_rate(info->mck);
221 cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
222 setup = calc_mck_cycles(ata->setup, mck_hz);
223 pulse = calc_mck_cycles(ata->act8b, mck_hz);
224 tdf_cycles = calc_mck_cycles(t6z, mck_hz);
225
226 do {
227 ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
228 } while (ret == -ER_SMC_RECALC);
229
230 if (ret == -ER_SMC_CALC)
231 dev_err(dev, "Interface may not operate correctly\n");
232
233 dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
234 setup, pulse, cycle, cs_pulse);
235 to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
236 /* disable or enable waiting for IORDY signal */
237 use_iordy = ata_pio_need_iordy(adev);
238 if (use_iordy)
239 info->mode |= AT91_SMC_EXNWMODE_READY;
240
241 if (tdf_cycles > 15) {
242 tdf_cycles = 15;
243 dev_warn(dev, "maximal SMC TDF Cycles value\n");
244 }
245
246 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
247 info->mode |= AT91_SMC_TDF_(tdf_cycles);
248
249 /* write SMC Setup Register */
250 at91_sys_write(AT91_SMC_SETUP(info->cs),
251 AT91_SMC_NWESETUP_(setup) |
252 AT91_SMC_NRDSETUP_(setup) |
253 AT91_SMC_NCS_WRSETUP_(cs_setup) |
254 AT91_SMC_NCS_RDSETUP_(cs_setup));
255 /* write SMC Pulse Register */
256 at91_sys_write(AT91_SMC_PULSE(info->cs),
257 AT91_SMC_NWEPULSE_(pulse) |
258 AT91_SMC_NRDPULSE_(pulse) |
259 AT91_SMC_NCS_WRPULSE_(cs_pulse) |
260 AT91_SMC_NCS_RDPULSE_(cs_pulse));
261 /* write SMC Cycle Register */
262 at91_sys_write(AT91_SMC_CYCLE(info->cs),
263 AT91_SMC_NWECYCLE_(cycle) |
264 AT91_SMC_NRDCYCLE_(cycle));
265 /* write SMC Mode Register*/
266 at91_sys_write(AT91_SMC_MODE(info->cs), info->mode);
267}
268
269static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
270{
271 struct at91_ide_info *info = ap->host->private_data;
272 struct ata_timing timing;
273 int ret;
274
275 /* Compute ATA timing and set it to SMC */
276 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
277 if (ret) {
278 dev_warn(ap->dev, "Failed to compute ATA timing %d, "
279 "set PIO_0 timing\n", ret);
280 timing = *ata_timing_find_mode(XFER_PIO_0);
281 }
282 set_smc_timing(ap->dev, adev, info, &timing);
283}
284
285static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
286 unsigned char *buf, unsigned int buflen, int rw)
287{
288 struct at91_ide_info *info = dev->link->ap->host->private_data;
289 unsigned int consumed;
290 unsigned long flags;
291 unsigned int mode;
292
293 local_irq_save(flags);
294 mode = at91_sys_read(AT91_SMC_MODE(info->cs));
295
296 /* set 16bit mode before writing data */
297 at91_sys_write(AT91_SMC_MODE(info->cs),
298 (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16);
299
300 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
301
302 /* restore 8bit mode after data is written */
303 at91_sys_write(AT91_SMC_MODE(info->cs),
304 (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8);
305
306 local_irq_restore(flags);
307 return consumed;
308}
309
310static struct scsi_host_template pata_at91_sht = {
311 ATA_PIO_SHT(DRV_NAME),
312};
313
314static struct ata_port_operations pata_at91_port_ops = {
315 .inherits = &ata_sff_port_ops,
316
317 .sff_data_xfer = pata_at91_data_xfer_noirq,
318 .set_piomode = pata_at91_set_piomode,
319 .cable_detect = ata_cable_40wire,
320};
321
322static int __devinit pata_at91_probe(struct platform_device *pdev)
323{
324 struct at91_cf_data *board = pdev->dev.platform_data;
325 struct device *dev = &pdev->dev;
326 struct at91_ide_info *info;
327 struct resource *mem_res;
328 struct ata_host *host;
329 struct ata_port *ap;
330
331 int irq_flags = 0;
332 int irq = 0;
333 int ret;
334
335 /* get platform resources: IO/CTL memories and irq/rst pins */
336
337 if (pdev->num_resources != 1) {
338 dev_err(&pdev->dev, "invalid number of resources\n");
339 return -EINVAL;
340 }
341
342 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343
344 if (!mem_res) {
345 dev_err(dev, "failed to get mem resource\n");
346 return -EINVAL;
347 }
348
349 irq = board->irq_pin;
350
351 /* init ata host */
352
353 host = ata_host_alloc(dev, 1);
354
355 if (!host)
356 return -ENOMEM;
357
358 ap = host->ports[0];
359 ap->ops = &pata_at91_port_ops;
360 ap->flags |= ATA_FLAG_SLAVE_POSS;
361 ap->pio_mask = ATA_PIO4;
362
363 if (!irq) {
364 ap->flags |= ATA_FLAG_PIO_POLLING;
365 ata_port_desc(ap, "no IRQ, using PIO polling");
366 }
367
368 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
369
370 if (!info) {
371 dev_err(dev, "failed to allocate memory for private data\n");
372 return -ENOMEM;
373 }
374
375 info->mck = clk_get(NULL, "mck");
376
377 if (IS_ERR(info->mck)) {
378 dev_err(dev, "failed to get access to mck clock\n");
379 return -ENODEV;
380 }
381
382 info->cs = board->chipselect;
383 info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
384 AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT |
385 AT91_SMC_DBW_8 | AT91_SMC_TDF_(0);
386
387 info->ide_addr = devm_ioremap(dev,
388 mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE);
389
390 if (!info->ide_addr) {
391 dev_err(dev, "failed to map IO base\n");
392 ret = -ENOMEM;
393 goto err_put;
394 }
395
396 info->alt_addr = devm_ioremap(dev,
397 mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE);
398
399 if (!info->alt_addr) {
400 dev_err(dev, "failed to map CTL base\n");
401 ret = -ENOMEM;
402 goto err_put;
403 }
404
405 ap->ioaddr.cmd_addr = info->ide_addr;
406 ap->ioaddr.ctl_addr = info->alt_addr + 0x06;
407 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
408
409 ata_sff_std_ports(&ap->ioaddr);
410
411 ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx",
412 (unsigned long long)mem_res->start + CF_IDE_OFFSET,
413 (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET);
414
415 host->private_data = info;
416
417 return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0,
418 irq ? ata_sff_interrupt : NULL,
419 irq_flags, &pata_at91_sht);
420
421err_put:
422 clk_put(info->mck);
423 return ret;
424}
425
426static int __devexit pata_at91_remove(struct platform_device *pdev)
427{
428 struct ata_host *host = dev_get_drvdata(&pdev->dev);
429 struct at91_ide_info *info;
430
431 if (!host)
432 return 0;
433 info = host->private_data;
434
435 ata_host_detach(host);
436
437 if (!info)
438 return 0;
439
440 clk_put(info->mck);
441
442 return 0;
443}
444
445static struct platform_driver pata_at91_driver = {
446 .probe = pata_at91_probe,
447 .remove = __devexit_p(pata_at91_remove),
448 .driver = {
449 .name = DRV_NAME,
450 .owner = THIS_MODULE,
451 },
452};
453
454static int __init pata_at91_init(void)
455{
456 return platform_driver_register(&pata_at91_driver);
457}
458
459static void __exit pata_at91_exit(void)
460{
461 platform_driver_unregister(&pata_at91_driver);
462}
463
464
465module_init(pata_at91_init);
466module_exit(pata_at91_exit);
467
468
469MODULE_LICENSE("GPL");
470MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC");
471MODULE_AUTHOR("Matyukevich Sergey");
472MODULE_VERSION(DRV_VERSION);
473