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1/*
2 * pata_artop.c - ARTOP ATA controller driver
3 *
4 * (C) 2006 Red Hat
5 * (C) 2007,2011 Bartlomiej Zolnierkiewicz
6 *
7 * Based in part on drivers/ide/pci/aec62xx.c
8 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
9 * 865/865R fixes for Macintosh card version from a patch to the old
10 * driver by Thibaut VARENE <varenet@parisc-linux.org>
11 * When setting the PCI latency we must set 0x80 or higher for burst
12 * performance Alessandro Zummo <alessandro.zummo@towertech.it>
13 *
14 * TODO
15 * Investigate no_dsc on 850R
16 * Clock detect
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27#include <linux/ata.h>
28
29#define DRV_NAME "pata_artop"
30#define DRV_VERSION "0.4.6"
31
32/*
33 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
34 * get PCI bus speed functionality we leave this as 0. Its a variable
35 * for when we get the functionality and also for folks wanting to
36 * test stuff.
37 */
38
39static int clock = 0;
40
41/**
42 * artop62x0_pre_reset - probe begin
43 * @link: link
44 * @deadline: deadline jiffies for the operation
45 *
46 * Nothing complicated needed here.
47 */
48
49static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
50{
51 static const struct pci_bits artop_enable_bits[] = {
52 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
53 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
54 };
55
56 struct ata_port *ap = link->ap;
57 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
58
59 /* Odd numbered device ids are the units with enable bits. */
60 if ((pdev->device & 1) &&
61 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
62 return -ENOENT;
63
64 return ata_sff_prereset(link, deadline);
65}
66
67/**
68 * artop6260_cable_detect - identify cable type
69 * @ap: Port
70 *
71 * Identify the cable type for the ARTOP interface in question
72 */
73
74static int artop6260_cable_detect(struct ata_port *ap)
75{
76 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
77 u8 tmp;
78 pci_read_config_byte(pdev, 0x49, &tmp);
79 if (tmp & (1 << ap->port_no))
80 return ATA_CBL_PATA40;
81 return ATA_CBL_PATA80;
82}
83
84/**
85 * artop6210_load_piomode - Load a set of PATA PIO timings
86 * @ap: Port whose timings we are configuring
87 * @adev: Device
88 * @pio: PIO mode
89 *
90 * Set PIO mode for device, in host controller PCI config space. This
91 * is used both to set PIO timings in PIO mode and also to set the
92 * matching PIO clocking for UDMA, as well as the MWDMA timings.
93 *
94 * LOCKING:
95 * None (inherited from caller).
96 */
97
98static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
99{
100 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
101 int dn = adev->devno + 2 * ap->port_no;
102 const u16 timing[2][5] = {
103 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
104 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
105
106 };
107 /* Load the PIO timing active/recovery bits */
108 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
109}
110
111/**
112 * artop6210_set_piomode - Initialize host controller PATA PIO timings
113 * @ap: Port whose timings we are configuring
114 * @adev: Device we are configuring
115 *
116 * Set PIO mode for device, in host controller PCI config space. For
117 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
118 * the event UDMA is used the later call to set_dmamode will set the
119 * bits as required.
120 *
121 * LOCKING:
122 * None (inherited from caller).
123 */
124
125static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
126{
127 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
128 int dn = adev->devno + 2 * ap->port_no;
129 u8 ultra;
130
131 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
132
133 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
134 pci_read_config_byte(pdev, 0x54, &ultra);
135 ultra &= ~(3 << (2 * dn));
136 pci_write_config_byte(pdev, 0x54, ultra);
137}
138
139/**
140 * artop6260_load_piomode - Initialize host controller PATA PIO timings
141 * @ap: Port whose timings we are configuring
142 * @adev: Device we are configuring
143 * @pio: PIO mode
144 *
145 * Set PIO mode for device, in host controller PCI config space. The
146 * ARTOP6260 and relatives store the timing data differently.
147 *
148 * LOCKING:
149 * None (inherited from caller).
150 */
151
152static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
153{
154 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
155 int dn = adev->devno + 2 * ap->port_no;
156 const u8 timing[2][5] = {
157 { 0x00, 0x0A, 0x08, 0x33, 0x31 },
158 { 0x70, 0x7A, 0x78, 0x43, 0x41 }
159
160 };
161 /* Load the PIO timing active/recovery bits */
162 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
163}
164
165/**
166 * artop6260_set_piomode - Initialize host controller PATA PIO timings
167 * @ap: Port whose timings we are configuring
168 * @adev: Device we are configuring
169 *
170 * Set PIO mode for device, in host controller PCI config space. For
171 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
172 * the event UDMA is used the later call to set_dmamode will set the
173 * bits as required.
174 *
175 * LOCKING:
176 * None (inherited from caller).
177 */
178
179static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
180{
181 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
182 u8 ultra;
183
184 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
185
186 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
187 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
188 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
189 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
190}
191
192/**
193 * artop6210_set_dmamode - Initialize host controller PATA PIO timings
194 * @ap: Port whose timings we are configuring
195 * @adev: Device whose timings we are configuring
196 *
197 * Set DMA mode for device, in host controller PCI config space.
198 *
199 * LOCKING:
200 * None (inherited from caller).
201 */
202
203static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
204{
205 unsigned int pio;
206 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
207 int dn = adev->devno + 2 * ap->port_no;
208 u8 ultra;
209
210 if (adev->dma_mode == XFER_MW_DMA_0)
211 pio = 1;
212 else
213 pio = 4;
214
215 /* Load the PIO timing active/recovery bits */
216 artop6210_load_piomode(ap, adev, pio);
217
218 pci_read_config_byte(pdev, 0x54, &ultra);
219 ultra &= ~(3 << (2 * dn));
220
221 /* Add ultra DMA bits if in UDMA mode */
222 if (adev->dma_mode >= XFER_UDMA_0) {
223 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
224 if (mode == 0)
225 mode = 1;
226 ultra |= (mode << (2 * dn));
227 }
228 pci_write_config_byte(pdev, 0x54, ultra);
229}
230
231/**
232 * artop6260_set_dmamode - Initialize host controller PATA PIO timings
233 * @ap: Port whose timings we are configuring
234 * @adev: Device we are configuring
235 *
236 * Set DMA mode for device, in host controller PCI config space. The
237 * ARTOP6260 and relatives store the timing data differently.
238 *
239 * LOCKING:
240 * None (inherited from caller).
241 */
242
243static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
244{
245 unsigned int pio = adev->pio_mode - XFER_PIO_0;
246 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
247 u8 ultra;
248
249 if (adev->dma_mode == XFER_MW_DMA_0)
250 pio = 1;
251 else
252 pio = 4;
253
254 /* Load the PIO timing active/recovery bits */
255 artop6260_load_piomode(ap, adev, pio);
256
257 /* Add ultra DMA bits if in UDMA mode */
258 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
259 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
260 if (adev->dma_mode >= XFER_UDMA_0) {
261 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
262 if (mode == 0)
263 mode = 1;
264 ultra |= (mode << (4 * adev->devno));
265 }
266 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
267}
268
269/**
270 * artop_6210_qc_defer - implement serialization
271 * @qc: command
272 *
273 * Issue commands per host on this chip.
274 */
275
276static int artop6210_qc_defer(struct ata_queued_cmd *qc)
277{
278 struct ata_host *host = qc->ap->host;
279 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
280 int rc;
281
282 /* First apply the usual rules */
283 rc = ata_std_qc_defer(qc);
284 if (rc != 0)
285 return rc;
286
287 /* Now apply serialization rules. Only allow a command if the
288 other channel state machine is idle */
289 if (alt && alt->qc_active)
290 return ATA_DEFER_PORT;
291 return 0;
292}
293
294static struct scsi_host_template artop_sht = {
295 ATA_BMDMA_SHT(DRV_NAME),
296};
297
298static struct ata_port_operations artop6210_ops = {
299 .inherits = &ata_bmdma_port_ops,
300 .cable_detect = ata_cable_40wire,
301 .set_piomode = artop6210_set_piomode,
302 .set_dmamode = artop6210_set_dmamode,
303 .prereset = artop62x0_pre_reset,
304 .qc_defer = artop6210_qc_defer,
305};
306
307static struct ata_port_operations artop6260_ops = {
308 .inherits = &ata_bmdma_port_ops,
309 .cable_detect = artop6260_cable_detect,
310 .set_piomode = artop6260_set_piomode,
311 .set_dmamode = artop6260_set_dmamode,
312 .prereset = artop62x0_pre_reset,
313};
314
315static void atp8xx_fixup(struct pci_dev *pdev)
316{
317 if (pdev->device == 0x0005)
318 /* BIOS may have left us in UDMA, clear it before libata probe */
319 pci_write_config_byte(pdev, 0x54, 0);
320 else if (pdev->device == 0x0008 || pdev->device == 0x0009) {
321 u8 reg;
322
323 /* Mac systems come up with some registers not set as we
324 will need them */
325
326 /* Clear reset & test bits */
327 pci_read_config_byte(pdev, 0x49, ®);
328 pci_write_config_byte(pdev, 0x49, reg & ~0x30);
329
330 /* PCI latency must be > 0x80 for burst mode, tweak it
331 * if required.
332 */
333 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
334 if (reg <= 0x80)
335 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
336
337 /* Enable IRQ output and burst mode */
338 pci_read_config_byte(pdev, 0x4a, ®);
339 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
340 }
341}
342
343/**
344 * artop_init_one - Register ARTOP ATA PCI device with kernel services
345 * @pdev: PCI device to register
346 * @ent: Entry in artop_pci_tbl matching with @pdev
347 *
348 * Called from kernel PCI layer.
349 *
350 * LOCKING:
351 * Inherited from PCI layer (may sleep).
352 *
353 * RETURNS:
354 * Zero on success, or -ERRNO value.
355 */
356
357static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
358{
359 static const struct ata_port_info info_6210 = {
360 .flags = ATA_FLAG_SLAVE_POSS,
361 .pio_mask = ATA_PIO4,
362 .mwdma_mask = ATA_MWDMA2,
363 .udma_mask = ATA_UDMA2,
364 .port_ops = &artop6210_ops,
365 };
366 static const struct ata_port_info info_626x = {
367 .flags = ATA_FLAG_SLAVE_POSS,
368 .pio_mask = ATA_PIO4,
369 .mwdma_mask = ATA_MWDMA2,
370 .udma_mask = ATA_UDMA4,
371 .port_ops = &artop6260_ops,
372 };
373 static const struct ata_port_info info_628x = {
374 .flags = ATA_FLAG_SLAVE_POSS,
375 .pio_mask = ATA_PIO4,
376 .mwdma_mask = ATA_MWDMA2,
377 .udma_mask = ATA_UDMA5,
378 .port_ops = &artop6260_ops,
379 };
380 static const struct ata_port_info info_628x_fast = {
381 .flags = ATA_FLAG_SLAVE_POSS,
382 .pio_mask = ATA_PIO4,
383 .mwdma_mask = ATA_MWDMA2,
384 .udma_mask = ATA_UDMA6,
385 .port_ops = &artop6260_ops,
386 };
387 const struct ata_port_info *ppi[] = { NULL, NULL };
388 int rc;
389
390 ata_print_version_once(&pdev->dev, DRV_VERSION);
391
392 rc = pcim_enable_device(pdev);
393 if (rc)
394 return rc;
395
396 if (id->driver_data == 0) /* 6210 variant */
397 ppi[0] = &info_6210;
398 else if (id->driver_data == 1) /* 6260 */
399 ppi[0] = &info_626x;
400 else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
401 unsigned long io = pci_resource_start(pdev, 4);
402
403 ppi[0] = &info_628x;
404 if (inb(io) & 0x10)
405 ppi[0] = &info_628x_fast;
406 }
407
408 BUG_ON(ppi[0] == NULL);
409
410 atp8xx_fixup(pdev);
411
412 return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
413}
414
415static const struct pci_device_id artop_pci_tbl[] = {
416 { PCI_VDEVICE(ARTOP, 0x0005), 0 },
417 { PCI_VDEVICE(ARTOP, 0x0006), 1 },
418 { PCI_VDEVICE(ARTOP, 0x0007), 1 },
419 { PCI_VDEVICE(ARTOP, 0x0008), 2 },
420 { PCI_VDEVICE(ARTOP, 0x0009), 2 },
421
422 { } /* terminate list */
423};
424
425#ifdef CONFIG_PM_SLEEP
426static int atp8xx_reinit_one(struct pci_dev *pdev)
427{
428 struct ata_host *host = pci_get_drvdata(pdev);
429 int rc;
430
431 rc = ata_pci_device_do_resume(pdev);
432 if (rc)
433 return rc;
434
435 atp8xx_fixup(pdev);
436
437 ata_host_resume(host);
438 return 0;
439}
440#endif
441
442static struct pci_driver artop_pci_driver = {
443 .name = DRV_NAME,
444 .id_table = artop_pci_tbl,
445 .probe = artop_init_one,
446 .remove = ata_pci_remove_one,
447#ifdef CONFIG_PM_SLEEP
448 .suspend = ata_pci_device_suspend,
449 .resume = atp8xx_reinit_one,
450#endif
451};
452
453module_pci_driver(artop_pci_driver);
454
455MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
456MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
457MODULE_LICENSE("GPL");
458MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
459MODULE_VERSION(DRV_VERSION);
1/*
2 * pata_artop.c - ARTOP ATA controller driver
3 *
4 * (C) 2006 Red Hat
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * Based in part on drivers/ide/pci/aec62xx.c
8 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
9 * 865/865R fixes for Macintosh card version from a patch to the old
10 * driver by Thibaut VARENE <varenet@parisc-linux.org>
11 * When setting the PCI latency we must set 0x80 or higher for burst
12 * performance Alessandro Zummo <alessandro.zummo@towertech.it>
13 *
14 * TODO
15 * Investigate no_dsc on 850R
16 * Clock detect
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28#include <linux/ata.h>
29
30#define DRV_NAME "pata_artop"
31#define DRV_VERSION "0.4.5"
32
33/*
34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
35 * get PCI bus speed functionality we leave this as 0. Its a variable
36 * for when we get the functionality and also for folks wanting to
37 * test stuff.
38 */
39
40static int clock = 0;
41
42static int artop6210_pre_reset(struct ata_link *link, unsigned long deadline)
43{
44 struct ata_port *ap = link->ap;
45 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
46 const struct pci_bits artop_enable_bits[] = {
47 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
48 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
49 };
50
51 if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
52 return -ENOENT;
53
54 return ata_sff_prereset(link, deadline);
55}
56
57/**
58 * artop6260_pre_reset - check for 40/80 pin
59 * @link: link
60 * @deadline: deadline jiffies for the operation
61 *
62 * The ARTOP hardware reports the cable detect bits in register 0x49.
63 * Nothing complicated needed here.
64 */
65
66static int artop6260_pre_reset(struct ata_link *link, unsigned long deadline)
67{
68 static const struct pci_bits artop_enable_bits[] = {
69 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
70 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
71 };
72
73 struct ata_port *ap = link->ap;
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
75
76 /* Odd numbered device ids are the units with enable bits (the -R cards) */
77 if ((pdev->device & 1) &&
78 !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
79 return -ENOENT;
80
81 return ata_sff_prereset(link, deadline);
82}
83
84/**
85 * artop6260_cable_detect - identify cable type
86 * @ap: Port
87 *
88 * Identify the cable type for the ARTOP interface in question
89 */
90
91static int artop6260_cable_detect(struct ata_port *ap)
92{
93 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
94 u8 tmp;
95 pci_read_config_byte(pdev, 0x49, &tmp);
96 if (tmp & (1 << ap->port_no))
97 return ATA_CBL_PATA40;
98 return ATA_CBL_PATA80;
99}
100
101/**
102 * artop6210_load_piomode - Load a set of PATA PIO timings
103 * @ap: Port whose timings we are configuring
104 * @adev: Device
105 * @pio: PIO mode
106 *
107 * Set PIO mode for device, in host controller PCI config space. This
108 * is used both to set PIO timings in PIO mode and also to set the
109 * matching PIO clocking for UDMA, as well as the MWDMA timings.
110 *
111 * LOCKING:
112 * None (inherited from caller).
113 */
114
115static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
116{
117 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
118 int dn = adev->devno + 2 * ap->port_no;
119 const u16 timing[2][5] = {
120 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
121 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
122
123 };
124 /* Load the PIO timing active/recovery bits */
125 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
126}
127
128/**
129 * artop6210_set_piomode - Initialize host controller PATA PIO timings
130 * @ap: Port whose timings we are configuring
131 * @adev: Device we are configuring
132 *
133 * Set PIO mode for device, in host controller PCI config space. For
134 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
135 * the event UDMA is used the later call to set_dmamode will set the
136 * bits as required.
137 *
138 * LOCKING:
139 * None (inherited from caller).
140 */
141
142static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
143{
144 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
145 int dn = adev->devno + 2 * ap->port_no;
146 u8 ultra;
147
148 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
149
150 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
151 pci_read_config_byte(pdev, 0x54, &ultra);
152 ultra &= ~(3 << (2 * dn));
153 pci_write_config_byte(pdev, 0x54, ultra);
154}
155
156/**
157 * artop6260_load_piomode - Initialize host controller PATA PIO timings
158 * @ap: Port whose timings we are configuring
159 * @adev: Device we are configuring
160 * @pio: PIO mode
161 *
162 * Set PIO mode for device, in host controller PCI config space. The
163 * ARTOP6260 and relatives store the timing data differently.
164 *
165 * LOCKING:
166 * None (inherited from caller).
167 */
168
169static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
170{
171 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
172 int dn = adev->devno + 2 * ap->port_no;
173 const u8 timing[2][5] = {
174 { 0x00, 0x0A, 0x08, 0x33, 0x31 },
175 { 0x70, 0x7A, 0x78, 0x43, 0x41 }
176
177 };
178 /* Load the PIO timing active/recovery bits */
179 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
180}
181
182/**
183 * artop6260_set_piomode - Initialize host controller PATA PIO timings
184 * @ap: Port whose timings we are configuring
185 * @adev: Device we are configuring
186 *
187 * Set PIO mode for device, in host controller PCI config space. For
188 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
189 * the event UDMA is used the later call to set_dmamode will set the
190 * bits as required.
191 *
192 * LOCKING:
193 * None (inherited from caller).
194 */
195
196static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
197{
198 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
199 u8 ultra;
200
201 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
202
203 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
204 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
205 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
206 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
207}
208
209/**
210 * artop6210_set_dmamode - Initialize host controller PATA PIO timings
211 * @ap: Port whose timings we are configuring
212 * @adev: Device whose timings we are configuring
213 *
214 * Set DMA mode for device, in host controller PCI config space.
215 *
216 * LOCKING:
217 * None (inherited from caller).
218 */
219
220static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
221{
222 unsigned int pio;
223 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
224 int dn = adev->devno + 2 * ap->port_no;
225 u8 ultra;
226
227 if (adev->dma_mode == XFER_MW_DMA_0)
228 pio = 1;
229 else
230 pio = 4;
231
232 /* Load the PIO timing active/recovery bits */
233 artop6210_load_piomode(ap, adev, pio);
234
235 pci_read_config_byte(pdev, 0x54, &ultra);
236 ultra &= ~(3 << (2 * dn));
237
238 /* Add ultra DMA bits if in UDMA mode */
239 if (adev->dma_mode >= XFER_UDMA_0) {
240 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
241 if (mode == 0)
242 mode = 1;
243 ultra |= (mode << (2 * dn));
244 }
245 pci_write_config_byte(pdev, 0x54, ultra);
246}
247
248/**
249 * artop6260_set_dmamode - Initialize host controller PATA PIO timings
250 * @ap: Port whose timings we are configuring
251 * @adev: Device we are configuring
252 *
253 * Set DMA mode for device, in host controller PCI config space. The
254 * ARTOP6260 and relatives store the timing data differently.
255 *
256 * LOCKING:
257 * None (inherited from caller).
258 */
259
260static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
261{
262 unsigned int pio = adev->pio_mode - XFER_PIO_0;
263 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
264 u8 ultra;
265
266 if (adev->dma_mode == XFER_MW_DMA_0)
267 pio = 1;
268 else
269 pio = 4;
270
271 /* Load the PIO timing active/recovery bits */
272 artop6260_load_piomode(ap, adev, pio);
273
274 /* Add ultra DMA bits if in UDMA mode */
275 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
276 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
277 if (adev->dma_mode >= XFER_UDMA_0) {
278 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
279 if (mode == 0)
280 mode = 1;
281 ultra |= (mode << (4 * adev->devno));
282 }
283 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
284}
285
286/**
287 * artop_6210_qc_defer - implement serialization
288 * @qc: command
289 *
290 * Issue commands per host on this chip.
291 */
292
293static int artop6210_qc_defer(struct ata_queued_cmd *qc)
294{
295 struct ata_host *host = qc->ap->host;
296 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
297 int rc;
298
299 /* First apply the usual rules */
300 rc = ata_std_qc_defer(qc);
301 if (rc != 0)
302 return rc;
303
304 /* Now apply serialization rules. Only allow a command if the
305 other channel state machine is idle */
306 if (alt && alt->qc_active)
307 return ATA_DEFER_PORT;
308 return 0;
309}
310
311static struct scsi_host_template artop_sht = {
312 ATA_BMDMA_SHT(DRV_NAME),
313};
314
315static struct ata_port_operations artop6210_ops = {
316 .inherits = &ata_bmdma_port_ops,
317 .cable_detect = ata_cable_40wire,
318 .set_piomode = artop6210_set_piomode,
319 .set_dmamode = artop6210_set_dmamode,
320 .prereset = artop6210_pre_reset,
321 .qc_defer = artop6210_qc_defer,
322};
323
324static struct ata_port_operations artop6260_ops = {
325 .inherits = &ata_bmdma_port_ops,
326 .cable_detect = artop6260_cable_detect,
327 .set_piomode = artop6260_set_piomode,
328 .set_dmamode = artop6260_set_dmamode,
329 .prereset = artop6260_pre_reset,
330};
331
332
333/**
334 * artop_init_one - Register ARTOP ATA PCI device with kernel services
335 * @pdev: PCI device to register
336 * @ent: Entry in artop_pci_tbl matching with @pdev
337 *
338 * Called from kernel PCI layer.
339 *
340 * LOCKING:
341 * Inherited from PCI layer (may sleep).
342 *
343 * RETURNS:
344 * Zero on success, or -ERRNO value.
345 */
346
347static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
348{
349 static const struct ata_port_info info_6210 = {
350 .flags = ATA_FLAG_SLAVE_POSS,
351 .pio_mask = ATA_PIO4,
352 .mwdma_mask = ATA_MWDMA2,
353 .udma_mask = ATA_UDMA2,
354 .port_ops = &artop6210_ops,
355 };
356 static const struct ata_port_info info_626x = {
357 .flags = ATA_FLAG_SLAVE_POSS,
358 .pio_mask = ATA_PIO4,
359 .mwdma_mask = ATA_MWDMA2,
360 .udma_mask = ATA_UDMA4,
361 .port_ops = &artop6260_ops,
362 };
363 static const struct ata_port_info info_628x = {
364 .flags = ATA_FLAG_SLAVE_POSS,
365 .pio_mask = ATA_PIO4,
366 .mwdma_mask = ATA_MWDMA2,
367 .udma_mask = ATA_UDMA5,
368 .port_ops = &artop6260_ops,
369 };
370 static const struct ata_port_info info_628x_fast = {
371 .flags = ATA_FLAG_SLAVE_POSS,
372 .pio_mask = ATA_PIO4,
373 .mwdma_mask = ATA_MWDMA2,
374 .udma_mask = ATA_UDMA6,
375 .port_ops = &artop6260_ops,
376 };
377 const struct ata_port_info *ppi[] = { NULL, NULL };
378 int rc;
379
380 ata_print_version_once(&pdev->dev, DRV_VERSION);
381
382 rc = pcim_enable_device(pdev);
383 if (rc)
384 return rc;
385
386 if (id->driver_data == 0) { /* 6210 variant */
387 ppi[0] = &info_6210;
388 /* BIOS may have left us in UDMA, clear it before libata probe */
389 pci_write_config_byte(pdev, 0x54, 0);
390 }
391 else if (id->driver_data == 1) /* 6260 */
392 ppi[0] = &info_626x;
393 else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
394 unsigned long io = pci_resource_start(pdev, 4);
395 u8 reg;
396
397 ppi[0] = &info_628x;
398 if (inb(io) & 0x10)
399 ppi[0] = &info_628x_fast;
400 /* Mac systems come up with some registers not set as we
401 will need them */
402
403 /* Clear reset & test bits */
404 pci_read_config_byte(pdev, 0x49, ®);
405 pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
406
407 /* PCI latency must be > 0x80 for burst mode, tweak it
408 * if required.
409 */
410 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
411 if (reg <= 0x80)
412 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
413
414 /* Enable IRQ output and burst mode */
415 pci_read_config_byte(pdev, 0x4a, ®);
416 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
417
418 }
419
420 BUG_ON(ppi[0] == NULL);
421
422 return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
423}
424
425static const struct pci_device_id artop_pci_tbl[] = {
426 { PCI_VDEVICE(ARTOP, 0x0005), 0 },
427 { PCI_VDEVICE(ARTOP, 0x0006), 1 },
428 { PCI_VDEVICE(ARTOP, 0x0007), 1 },
429 { PCI_VDEVICE(ARTOP, 0x0008), 2 },
430 { PCI_VDEVICE(ARTOP, 0x0009), 2 },
431
432 { } /* terminate list */
433};
434
435static struct pci_driver artop_pci_driver = {
436 .name = DRV_NAME,
437 .id_table = artop_pci_tbl,
438 .probe = artop_init_one,
439 .remove = ata_pci_remove_one,
440};
441
442static int __init artop_init(void)
443{
444 return pci_register_driver(&artop_pci_driver);
445}
446
447static void __exit artop_exit(void)
448{
449 pci_unregister_driver(&artop_pci_driver);
450}
451
452module_init(artop_init);
453module_exit(artop_exit);
454
455MODULE_AUTHOR("Alan Cox");
456MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
457MODULE_LICENSE("GPL");
458MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
459MODULE_VERSION(DRV_VERSION);
460