Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "drm_flip_work.h"
19#include <drm/drm_plane_helper.h>
20
21#include "tilcdc_drv.h"
22#include "tilcdc_regs.h"
23
24#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
25
26struct tilcdc_crtc {
27 struct drm_crtc base;
28
29 const struct tilcdc_panel_info *info;
30 struct drm_pending_vblank_event *event;
31 int dpms;
32 wait_queue_head_t frame_done_wq;
33 bool frame_done;
34 spinlock_t irq_lock;
35
36 ktime_t last_vblank;
37
38 struct drm_framebuffer *curr_fb;
39 struct drm_framebuffer *next_fb;
40
41 /* for deferred fb unref's: */
42 struct drm_flip_work unref_work;
43
44 /* Only set if an external encoder is connected */
45 bool simulate_vesa_sync;
46
47 int sync_lost_count;
48 bool frame_intact;
49};
50#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
51
52static void unref_worker(struct drm_flip_work *work, void *val)
53{
54 struct tilcdc_crtc *tilcdc_crtc =
55 container_of(work, struct tilcdc_crtc, unref_work);
56 struct drm_device *dev = tilcdc_crtc->base.dev;
57
58 mutex_lock(&dev->mode_config.mutex);
59 drm_framebuffer_unreference(val);
60 mutex_unlock(&dev->mode_config.mutex);
61}
62
63static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
64{
65 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
66 struct drm_device *dev = crtc->dev;
67 struct drm_gem_cma_object *gem;
68 unsigned int depth, bpp;
69 dma_addr_t start, end;
70
71 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
72 gem = drm_fb_cma_get_gem_obj(fb, 0);
73
74 start = gem->paddr + fb->offsets[0] +
75 crtc->y * fb->pitches[0] +
76 crtc->x * bpp / 8;
77
78 end = start + (crtc->mode.vdisplay * fb->pitches[0]);
79
80 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
81 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
82
83 if (tilcdc_crtc->curr_fb)
84 drm_flip_work_queue(&tilcdc_crtc->unref_work,
85 tilcdc_crtc->curr_fb);
86
87 tilcdc_crtc->curr_fb = fb;
88}
89
90static void reset(struct drm_crtc *crtc)
91{
92 struct drm_device *dev = crtc->dev;
93 struct tilcdc_drm_private *priv = dev->dev_private;
94
95 if (priv->rev != 2)
96 return;
97
98 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
99 usleep_range(250, 1000);
100 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
101}
102
103static void start(struct drm_crtc *crtc)
104{
105 struct drm_device *dev = crtc->dev;
106
107 reset(crtc);
108
109 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
110 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
111 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
112}
113
114static void stop(struct drm_crtc *crtc)
115{
116 struct drm_device *dev = crtc->dev;
117
118 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
119}
120
121static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
122{
123 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
124
125 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
126
127 of_node_put(crtc->port);
128 drm_crtc_cleanup(crtc);
129 drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
130}
131
132static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
133{
134 struct drm_device *dev = crtc->dev;
135 unsigned int depth, bpp;
136
137 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
138
139 if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
140 dev_err(dev->dev,
141 "Invalid pitch: fb and crtc widths must be the same");
142 return -EINVAL;
143 }
144
145 return 0;
146}
147
148static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
149 struct drm_framebuffer *fb,
150 struct drm_pending_vblank_event *event,
151 uint32_t page_flip_flags)
152{
153 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
154 struct drm_device *dev = crtc->dev;
155 int r;
156 unsigned long flags;
157 s64 tdiff;
158 ktime_t next_vblank;
159
160 r = tilcdc_verify_fb(crtc, fb);
161 if (r)
162 return r;
163
164 if (tilcdc_crtc->event) {
165 dev_err(dev->dev, "already pending page flip!\n");
166 return -EBUSY;
167 }
168
169 drm_framebuffer_reference(fb);
170
171 crtc->primary->fb = fb;
172
173 pm_runtime_get_sync(dev->dev);
174
175 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
176
177 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
178 1000000 / crtc->hwmode.vrefresh);
179
180 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
181
182 if (tdiff >= TILCDC_VBLANK_SAFETY_THRESHOLD_US)
183 set_scanout(crtc, fb);
184 else
185 tilcdc_crtc->next_fb = fb;
186
187 tilcdc_crtc->event = event;
188
189 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
190
191 pm_runtime_put_sync(dev->dev);
192
193 return 0;
194}
195
196void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
197{
198 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct tilcdc_drm_private *priv = dev->dev_private;
201
202 /* we really only care about on or off: */
203 if (mode != DRM_MODE_DPMS_ON)
204 mode = DRM_MODE_DPMS_OFF;
205
206 if (tilcdc_crtc->dpms == mode)
207 return;
208
209 tilcdc_crtc->dpms = mode;
210
211 if (mode == DRM_MODE_DPMS_ON) {
212 pm_runtime_get_sync(dev->dev);
213 start(crtc);
214 } else {
215 tilcdc_crtc->frame_done = false;
216 stop(crtc);
217
218 /*
219 * if necessary wait for framedone irq which will still come
220 * before putting things to sleep..
221 */
222 if (priv->rev == 2) {
223 int ret = wait_event_timeout(
224 tilcdc_crtc->frame_done_wq,
225 tilcdc_crtc->frame_done,
226 msecs_to_jiffies(50));
227 if (ret == 0)
228 dev_err(dev->dev, "timeout waiting for framedone\n");
229 }
230
231 pm_runtime_put_sync(dev->dev);
232
233 if (tilcdc_crtc->next_fb) {
234 drm_flip_work_queue(&tilcdc_crtc->unref_work,
235 tilcdc_crtc->next_fb);
236 tilcdc_crtc->next_fb = NULL;
237 }
238
239 if (tilcdc_crtc->curr_fb) {
240 drm_flip_work_queue(&tilcdc_crtc->unref_work,
241 tilcdc_crtc->curr_fb);
242 tilcdc_crtc->curr_fb = NULL;
243 }
244
245 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
246 }
247}
248
249static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
250 const struct drm_display_mode *mode,
251 struct drm_display_mode *adjusted_mode)
252{
253 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
254
255 if (!tilcdc_crtc->simulate_vesa_sync)
256 return true;
257
258 /*
259 * tilcdc does not generate VESA-compliant sync but aligns
260 * VS on the second edge of HS instead of first edge.
261 * We use adjusted_mode, to fixup sync by aligning both rising
262 * edges and add HSKEW offset to fix the sync.
263 */
264 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
265 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
266
267 if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
268 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
269 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
270 } else {
271 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
272 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
273 }
274
275 return true;
276}
277
278static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
279{
280 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
281}
282
283static void tilcdc_crtc_commit(struct drm_crtc *crtc)
284{
285 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
286}
287
288static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
289 struct drm_display_mode *mode,
290 struct drm_display_mode *adjusted_mode,
291 int x, int y,
292 struct drm_framebuffer *old_fb)
293{
294 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
295 struct drm_device *dev = crtc->dev;
296 struct tilcdc_drm_private *priv = dev->dev_private;
297 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
298 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
299 int ret;
300
301 ret = tilcdc_crtc_mode_valid(crtc, mode);
302 if (WARN_ON(ret))
303 return ret;
304
305 if (WARN_ON(!info))
306 return -EINVAL;
307
308 ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
309 if (ret)
310 return ret;
311
312 pm_runtime_get_sync(dev->dev);
313
314 /* Configure the Burst Size and fifo threshold of DMA: */
315 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
316 switch (info->dma_burst_sz) {
317 case 1:
318 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
319 break;
320 case 2:
321 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
322 break;
323 case 4:
324 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
325 break;
326 case 8:
327 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
328 break;
329 case 16:
330 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
331 break;
332 default:
333 return -EINVAL;
334 }
335 reg |= (info->fifo_th << 8);
336 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
337
338 /* Configure timings: */
339 hbp = mode->htotal - mode->hsync_end;
340 hfp = mode->hsync_start - mode->hdisplay;
341 hsw = mode->hsync_end - mode->hsync_start;
342 vbp = mode->vtotal - mode->vsync_end;
343 vfp = mode->vsync_start - mode->vdisplay;
344 vsw = mode->vsync_end - mode->vsync_start;
345
346 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
347 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
348
349 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
350 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
351 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
352 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
353
354 /*
355 * subtract one from hfp, hbp, hsw because the hardware uses
356 * a value of 0 as 1
357 */
358 if (priv->rev == 2) {
359 /* clear bits we're going to set */
360 reg &= ~0x78000033;
361 reg |= ((hfp-1) & 0x300) >> 8;
362 reg |= ((hbp-1) & 0x300) >> 4;
363 reg |= ((hsw-1) & 0x3c0) << 21;
364 }
365 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
366
367 reg = (((mode->hdisplay >> 4) - 1) << 4) |
368 (((hbp-1) & 0xff) << 24) |
369 (((hfp-1) & 0xff) << 16) |
370 (((hsw-1) & 0x3f) << 10);
371 if (priv->rev == 2)
372 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
373 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
374
375 reg = ((mode->vdisplay - 1) & 0x3ff) |
376 ((vbp & 0xff) << 24) |
377 ((vfp & 0xff) << 16) |
378 (((vsw-1) & 0x3f) << 10);
379 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
380
381 /*
382 * be sure to set Bit 10 for the V2 LCDC controller,
383 * otherwise limited to 1024 pixels width, stopping
384 * 1920x1080 being suppoted.
385 */
386 if (priv->rev == 2) {
387 if ((mode->vdisplay - 1) & 0x400) {
388 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
389 LCDC_LPP_B10);
390 } else {
391 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
392 LCDC_LPP_B10);
393 }
394 }
395
396 /* Configure display type: */
397 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
398 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
399 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
400 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
401 if (info->tft_alt_mode)
402 reg |= LCDC_TFT_ALT_ENABLE;
403 if (priv->rev == 2) {
404 unsigned int depth, bpp;
405
406 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
407 switch (bpp) {
408 case 16:
409 break;
410 case 32:
411 reg |= LCDC_V2_TFT_24BPP_UNPACK;
412 /* fallthrough */
413 case 24:
414 reg |= LCDC_V2_TFT_24BPP_MODE;
415 break;
416 default:
417 dev_err(dev->dev, "invalid pixel format\n");
418 return -EINVAL;
419 }
420 }
421 reg |= info->fdd < 12;
422 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
423
424 if (info->invert_pxl_clk)
425 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
426 else
427 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
428
429 if (info->sync_ctrl)
430 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
431 else
432 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
433
434 if (info->sync_edge)
435 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
436 else
437 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
438
439 /*
440 * use value from adjusted_mode here as this might have been
441 * changed as part of the fixup for slave encoders to solve the
442 * issue where tilcdc timings are not VESA compliant
443 */
444 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
445 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
446 else
447 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
448
449 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
450 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
451 else
452 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
453
454 if (info->raster_order)
455 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
456 else
457 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
458
459 drm_framebuffer_reference(crtc->primary->fb);
460
461 set_scanout(crtc, crtc->primary->fb);
462
463 tilcdc_crtc_update_clk(crtc);
464
465 pm_runtime_put_sync(dev->dev);
466
467 return 0;
468}
469
470static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
471 struct drm_framebuffer *old_fb)
472{
473 struct drm_device *dev = crtc->dev;
474 int r;
475
476 r = tilcdc_verify_fb(crtc, crtc->primary->fb);
477 if (r)
478 return r;
479
480 drm_framebuffer_reference(crtc->primary->fb);
481
482 pm_runtime_get_sync(dev->dev);
483
484 set_scanout(crtc, crtc->primary->fb);
485
486 pm_runtime_put_sync(dev->dev);
487
488 return 0;
489}
490
491static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
492 .destroy = tilcdc_crtc_destroy,
493 .set_config = drm_crtc_helper_set_config,
494 .page_flip = tilcdc_crtc_page_flip,
495};
496
497static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
498 .dpms = tilcdc_crtc_dpms,
499 .mode_fixup = tilcdc_crtc_mode_fixup,
500 .prepare = tilcdc_crtc_prepare,
501 .commit = tilcdc_crtc_commit,
502 .mode_set = tilcdc_crtc_mode_set,
503 .mode_set_base = tilcdc_crtc_mode_set_base,
504};
505
506int tilcdc_crtc_max_width(struct drm_crtc *crtc)
507{
508 struct drm_device *dev = crtc->dev;
509 struct tilcdc_drm_private *priv = dev->dev_private;
510 int max_width = 0;
511
512 if (priv->rev == 1)
513 max_width = 1024;
514 else if (priv->rev == 2)
515 max_width = 2048;
516
517 return max_width;
518}
519
520int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
521{
522 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
523 unsigned int bandwidth;
524 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
525
526 /*
527 * check to see if the width is within the range that
528 * the LCD Controller physically supports
529 */
530 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
531 return MODE_VIRTUAL_X;
532
533 /* width must be multiple of 16 */
534 if (mode->hdisplay & 0xf)
535 return MODE_VIRTUAL_X;
536
537 if (mode->vdisplay > 2048)
538 return MODE_VIRTUAL_Y;
539
540 DBG("Processing mode %dx%d@%d with pixel clock %d",
541 mode->hdisplay, mode->vdisplay,
542 drm_mode_vrefresh(mode), mode->clock);
543
544 hbp = mode->htotal - mode->hsync_end;
545 hfp = mode->hsync_start - mode->hdisplay;
546 hsw = mode->hsync_end - mode->hsync_start;
547 vbp = mode->vtotal - mode->vsync_end;
548 vfp = mode->vsync_start - mode->vdisplay;
549 vsw = mode->vsync_end - mode->vsync_start;
550
551 if ((hbp-1) & ~0x3ff) {
552 DBG("Pruning mode: Horizontal Back Porch out of range");
553 return MODE_HBLANK_WIDE;
554 }
555
556 if ((hfp-1) & ~0x3ff) {
557 DBG("Pruning mode: Horizontal Front Porch out of range");
558 return MODE_HBLANK_WIDE;
559 }
560
561 if ((hsw-1) & ~0x3ff) {
562 DBG("Pruning mode: Horizontal Sync Width out of range");
563 return MODE_HSYNC_WIDE;
564 }
565
566 if (vbp & ~0xff) {
567 DBG("Pruning mode: Vertical Back Porch out of range");
568 return MODE_VBLANK_WIDE;
569 }
570
571 if (vfp & ~0xff) {
572 DBG("Pruning mode: Vertical Front Porch out of range");
573 return MODE_VBLANK_WIDE;
574 }
575
576 if ((vsw-1) & ~0x3f) {
577 DBG("Pruning mode: Vertical Sync Width out of range");
578 return MODE_VSYNC_WIDE;
579 }
580
581 /*
582 * some devices have a maximum allowed pixel clock
583 * configured from the DT
584 */
585 if (mode->clock > priv->max_pixelclock) {
586 DBG("Pruning mode: pixel clock too high");
587 return MODE_CLOCK_HIGH;
588 }
589
590 /*
591 * some devices further limit the max horizontal resolution
592 * configured from the DT
593 */
594 if (mode->hdisplay > priv->max_width)
595 return MODE_BAD_WIDTH;
596
597 /* filter out modes that would require too much memory bandwidth: */
598 bandwidth = mode->hdisplay * mode->vdisplay *
599 drm_mode_vrefresh(mode);
600 if (bandwidth > priv->max_bandwidth) {
601 DBG("Pruning mode: exceeds defined bandwidth limit");
602 return MODE_BAD;
603 }
604
605 return MODE_OK;
606}
607
608void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
609 const struct tilcdc_panel_info *info)
610{
611 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
612 tilcdc_crtc->info = info;
613}
614
615void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
616 bool simulate_vesa_sync)
617{
618 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
619
620 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
621}
622
623void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
624{
625 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
626 struct drm_device *dev = crtc->dev;
627 struct tilcdc_drm_private *priv = dev->dev_private;
628 int dpms = tilcdc_crtc->dpms;
629 unsigned long lcd_clk;
630 const unsigned clkdiv = 2; /* using a fixed divider of 2 */
631 int ret;
632
633 pm_runtime_get_sync(dev->dev);
634
635 if (dpms == DRM_MODE_DPMS_ON)
636 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
637
638 /* mode.clock is in KHz, set_rate wants parameter in Hz */
639 ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
640 if (ret < 0) {
641 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
642 crtc->mode.clock);
643 goto out;
644 }
645
646 lcd_clk = clk_get_rate(priv->clk);
647
648 DBG("lcd_clk=%lu, mode clock=%d, div=%u",
649 lcd_clk, crtc->mode.clock, clkdiv);
650
651 /* Configure the LCD clock divisor. */
652 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
653 LCDC_RASTER_MODE);
654
655 if (priv->rev == 2)
656 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
657 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
658 LCDC_V2_CORE_CLK_EN);
659
660 if (dpms == DRM_MODE_DPMS_ON)
661 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
662
663out:
664 pm_runtime_put_sync(dev->dev);
665}
666
667#define SYNC_LOST_COUNT_LIMIT 50
668
669irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
670{
671 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
672 struct drm_device *dev = crtc->dev;
673 struct tilcdc_drm_private *priv = dev->dev_private;
674 uint32_t stat;
675
676 stat = tilcdc_read_irqstatus(dev);
677 tilcdc_clear_irqstatus(dev, stat);
678
679 if (stat & LCDC_END_OF_FRAME0) {
680 unsigned long flags;
681 bool skip_event = false;
682 ktime_t now;
683
684 now = ktime_get();
685
686 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
687
688 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
689
690 tilcdc_crtc->last_vblank = now;
691
692 if (tilcdc_crtc->next_fb) {
693 set_scanout(crtc, tilcdc_crtc->next_fb);
694 tilcdc_crtc->next_fb = NULL;
695 skip_event = true;
696 }
697
698 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
699
700 drm_handle_vblank(dev, 0);
701
702 if (!skip_event) {
703 struct drm_pending_vblank_event *event;
704
705 spin_lock_irqsave(&dev->event_lock, flags);
706
707 event = tilcdc_crtc->event;
708 tilcdc_crtc->event = NULL;
709 if (event)
710 drm_send_vblank_event(dev, 0, event);
711
712 spin_unlock_irqrestore(&dev->event_lock, flags);
713 }
714
715 if (tilcdc_crtc->frame_intact)
716 tilcdc_crtc->sync_lost_count = 0;
717 else
718 tilcdc_crtc->frame_intact = true;
719 }
720
721 if (priv->rev == 2) {
722 if (stat & LCDC_FRAME_DONE) {
723 tilcdc_crtc->frame_done = true;
724 wake_up(&tilcdc_crtc->frame_done_wq);
725 }
726 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
727 }
728
729 if (stat & LCDC_SYNC_LOST) {
730 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
731 __func__, stat);
732 tilcdc_crtc->frame_intact = false;
733 if (tilcdc_crtc->sync_lost_count++ > SYNC_LOST_COUNT_LIMIT) {
734 dev_err(dev->dev,
735 "%s(0x%08x): Sync lost flood detected, disabling the interrupt",
736 __func__, stat);
737 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
738 LCDC_SYNC_LOST);
739 }
740 }
741
742 if (stat & LCDC_FIFO_UNDERFLOW)
743 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
744 __func__, stat);
745
746 return IRQ_HANDLED;
747}
748
749struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
750{
751 struct tilcdc_drm_private *priv = dev->dev_private;
752 struct tilcdc_crtc *tilcdc_crtc;
753 struct drm_crtc *crtc;
754 int ret;
755
756 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
757 if (!tilcdc_crtc) {
758 dev_err(dev->dev, "allocation failed\n");
759 return NULL;
760 }
761
762 crtc = &tilcdc_crtc->base;
763
764 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
765 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
766
767 drm_flip_work_init(&tilcdc_crtc->unref_work,
768 "unref", unref_worker);
769
770 spin_lock_init(&tilcdc_crtc->irq_lock);
771
772 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
773 if (ret < 0)
774 goto fail;
775
776 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
777
778 if (priv->is_componentized) {
779 struct device_node *ports =
780 of_get_child_by_name(dev->dev->of_node, "ports");
781
782 if (ports) {
783 crtc->port = of_get_child_by_name(ports, "port");
784 of_node_put(ports);
785 } else {
786 crtc->port =
787 of_get_child_by_name(dev->dev->of_node, "port");
788 }
789 if (!crtc->port) { /* This should never happen */
790 dev_err(dev->dev, "Port node not found in %s\n",
791 dev->dev->of_node->full_name);
792 goto fail;
793 }
794 }
795
796 return crtc;
797
798fail:
799 tilcdc_crtc_destroy(crtc);
800 return NULL;
801}