1/**
  2 * \file amdgpu_drv.c
  3 * AMD Amdgpu driver
  4 *
  5 * \author Gareth Hughes <gareth@valinux.com>
  6 */
  7
  8/*
  9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 10 * All Rights Reserved.
 11 *
 12 * Permission is hereby granted, free of charge, to any person obtaining a
 13 * copy of this software and associated documentation files (the "Software"),
 14 * to deal in the Software without restriction, including without limitation
 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 16 * and/or sell copies of the Software, and to permit persons to whom the
 17 * Software is furnished to do so, subject to the following conditions:
 18 *
 19 * The above copyright notice and this permission notice (including the next
 20 * paragraph) shall be included in all copies or substantial portions of the
 21 * Software.
 22 *
 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 29 * OTHER DEALINGS IN THE SOFTWARE.
 30 */
 31
 32#include <drm/drmP.h>
 33#include <drm/amdgpu_drm.h>
 34#include <drm/drm_gem.h>
 35#include "amdgpu_drv.h"
 36
 37#include <drm/drm_pciids.h>
 38#include <linux/console.h>
 39#include <linux/module.h>
 40#include <linux/pm_runtime.h>
 41#include <linux/vga_switcheroo.h>
 42#include "drm_crtc_helper.h"
 43
 44#include "amdgpu.h"
 45#include "amdgpu_irq.h"
 46
 47#include "amdgpu_amdkfd.h"
 48
 49/*
 50 * KMS wrapper.
 51 * - 3.0.0 - initial driver
 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
 53 */
 54#define KMS_DRIVER_MAJOR	3
 55#define KMS_DRIVER_MINOR	1
 56#define KMS_DRIVER_PATCHLEVEL	0
 57
 58int amdgpu_vram_limit = 0;
 59int amdgpu_gart_size = -1; /* auto */
 60int amdgpu_benchmarking = 0;
 61int amdgpu_testing = 0;
 62int amdgpu_audio = -1;
 63int amdgpu_disp_priority = 0;
 64int amdgpu_hw_i2c = 0;
 65int amdgpu_pcie_gen2 = -1;
 66int amdgpu_msi = -1;
 67int amdgpu_lockup_timeout = 0;
 68int amdgpu_dpm = -1;
 69int amdgpu_smc_load_fw = 1;
 70int amdgpu_aspm = -1;
 71int amdgpu_runtime_pm = -1;
 72unsigned amdgpu_ip_block_mask = 0xffffffff;
 73int amdgpu_bapm = -1;
 74int amdgpu_deep_color = 0;
 75int amdgpu_vm_size = 64;
 76int amdgpu_vm_block_size = -1;
 77int amdgpu_vm_fault_stop = 0;
 78int amdgpu_vm_debug = 0;
 79int amdgpu_exp_hw_support = 0;
 80int amdgpu_sched_jobs = 32;
 81int amdgpu_sched_hw_submission = 2;
 82int amdgpu_powerplay = -1;
 83unsigned amdgpu_pcie_gen_cap = 0;
 84unsigned amdgpu_pcie_lane_cap = 0;
 85
 86MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 87module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 88
 89MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
 90module_param_named(gartsize, amdgpu_gart_size, int, 0600);
 91
 92MODULE_PARM_DESC(benchmark, "Run benchmark");
 93module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 94
 95MODULE_PARM_DESC(test, "Run tests");
 96module_param_named(test, amdgpu_testing, int, 0444);
 97
 98MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 99module_param_named(audio, amdgpu_audio, int, 0444);
100
101MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
102module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
103
104MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
105module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
106
107MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
108module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
109
110MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
111module_param_named(msi, amdgpu_msi, int, 0444);
112
113MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
114module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
115
116MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
117module_param_named(dpm, amdgpu_dpm, int, 0444);
118
119MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
120module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
121
122MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
123module_param_named(aspm, amdgpu_aspm, int, 0444);
124
125MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
126module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
127
128MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
129module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
130
131MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
132module_param_named(bapm, amdgpu_bapm, int, 0444);
133
134MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
135module_param_named(deep_color, amdgpu_deep_color, int, 0444);
136
137MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
138module_param_named(vm_size, amdgpu_vm_size, int, 0444);
139
140MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
141module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
142
143MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
144module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
145
146MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
147module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
148
149MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
150module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
151
152MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
153module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
154
155MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
156module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
157
158#ifdef CONFIG_DRM_AMD_POWERPLAY
159MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
160module_param_named(powerplay, amdgpu_powerplay, int, 0444);
161#endif
162
163MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
164module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
165
166MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
167module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
168
169static struct pci_device_id pciidlist[] = {
170#ifdef CONFIG_DRM_AMDGPU_CIK
171	/* Kaveri */
172	{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
173	{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
174	{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
175	{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
176	{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
177	{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
178	{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
179	{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
180	{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
181	{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
182	{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
183	{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
184	{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
185	{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
186	{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
187	{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
188	{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
189	{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
190	{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
191	{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
192	{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
193	{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
194	/* Bonaire */
195	{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
196	{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
197	{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
198	{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
199	{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
200	{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
201	{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
202	{0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
203	{0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
204	{0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
205	{0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
206	/* Hawaii */
207	{0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
208	{0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
209	{0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
210	{0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
211	{0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
212	{0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
213	{0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
214	{0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
215	{0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
216	{0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
217	{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
218	{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
219	/* Kabini */
220	{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
221	{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
222	{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
223	{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
224	{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
225	{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
226	{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
227	{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
228	{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
229	{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
230	{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
231	{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
232	{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
233	{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
234	{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
235	{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
236	/* mullins */
237	{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
238	{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
239	{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
240	{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
241	{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
242	{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
243	{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
244	{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
245	{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
246	{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
247	{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
248	{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
249	{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
250	{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
251	{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
252	{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
253#endif
254	/* topaz */
255	{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
256	{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
257	{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
258	{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
259	{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260	/* tonga */
261	{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
262	{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
263	{0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
264	{0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
265	{0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
266	{0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
267	{0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
268	{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
269	{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
270	/* fiji */
271	{0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
272	/* carrizo */
273	{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
274	{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
275	{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
276	{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
277	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
278	/* stoney */
279	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
280
281	{0, 0, 0}
282};
283
284MODULE_DEVICE_TABLE(pci, pciidlist);
285
286static struct drm_driver kms_driver;
287
288static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
289{
290	struct apertures_struct *ap;
291	bool primary = false;
292
293	ap = alloc_apertures(1);
294	if (!ap)
295		return -ENOMEM;
296
297	ap->ranges[0].base = pci_resource_start(pdev, 0);
298	ap->ranges[0].size = pci_resource_len(pdev, 0);
299
300#ifdef CONFIG_X86
301	primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
302#endif
303	remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
304	kfree(ap);
305
306	return 0;
307}
308
309static int amdgpu_pci_probe(struct pci_dev *pdev,
310			    const struct pci_device_id *ent)
311{
312	unsigned long flags = ent->driver_data;
313	int ret;
314
315	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
316		DRM_INFO("This hardware requires experimental hardware support.\n"
317			 "See modparam exp_hw_support\n");
318		return -ENODEV;
319	}
320
321	/*
322	 * Initialize amdkfd before starting radeon. If it was not loaded yet,
323	 * defer radeon probing
324	 */
325	ret = amdgpu_amdkfd_init();
326	if (ret == -EPROBE_DEFER)
327		return ret;
328
329	/* Get rid of things like offb */
330	ret = amdgpu_kick_out_firmware_fb(pdev);
331	if (ret)
332		return ret;
333
334	return drm_get_pci_dev(pdev, ent, &kms_driver);
335}
336
337static void
338amdgpu_pci_remove(struct pci_dev *pdev)
339{
340	struct drm_device *dev = pci_get_drvdata(pdev);
341
342	drm_put_dev(dev);
343}
344
345static int amdgpu_pmops_suspend(struct device *dev)
346{
347	struct pci_dev *pdev = to_pci_dev(dev);
348	struct drm_device *drm_dev = pci_get_drvdata(pdev);
349	return amdgpu_suspend_kms(drm_dev, true, true);
350}
351
352static int amdgpu_pmops_resume(struct device *dev)
353{
354	struct pci_dev *pdev = to_pci_dev(dev);
355	struct drm_device *drm_dev = pci_get_drvdata(pdev);
356	return amdgpu_resume_kms(drm_dev, true, true);
357}
358
359static int amdgpu_pmops_freeze(struct device *dev)
360{
361	struct pci_dev *pdev = to_pci_dev(dev);
362	struct drm_device *drm_dev = pci_get_drvdata(pdev);
363	return amdgpu_suspend_kms(drm_dev, false, true);
364}
365
366static int amdgpu_pmops_thaw(struct device *dev)
367{
368	struct pci_dev *pdev = to_pci_dev(dev);
369	struct drm_device *drm_dev = pci_get_drvdata(pdev);
370	return amdgpu_resume_kms(drm_dev, false, true);
371}
372
373static int amdgpu_pmops_runtime_suspend(struct device *dev)
374{
375	struct pci_dev *pdev = to_pci_dev(dev);
376	struct drm_device *drm_dev = pci_get_drvdata(pdev);
377	int ret;
378
379	if (!amdgpu_device_is_px(drm_dev)) {
380		pm_runtime_forbid(dev);
381		return -EBUSY;
382	}
383
384	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
385	drm_kms_helper_poll_disable(drm_dev);
386	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
387
388	ret = amdgpu_suspend_kms(drm_dev, false, false);
389	pci_save_state(pdev);
390	pci_disable_device(pdev);
391	pci_ignore_hotplug(pdev);
392	pci_set_power_state(pdev, PCI_D3cold);
393	drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
394
395	return 0;
396}
397
398static int amdgpu_pmops_runtime_resume(struct device *dev)
399{
400	struct pci_dev *pdev = to_pci_dev(dev);
401	struct drm_device *drm_dev = pci_get_drvdata(pdev);
402	int ret;
403
404	if (!amdgpu_device_is_px(drm_dev))
405		return -EINVAL;
406
407	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
408
409	pci_set_power_state(pdev, PCI_D0);
410	pci_restore_state(pdev);
411	ret = pci_enable_device(pdev);
412	if (ret)
413		return ret;
414	pci_set_master(pdev);
415
416	ret = amdgpu_resume_kms(drm_dev, false, false);
417	drm_kms_helper_poll_enable(drm_dev);
418	vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
419	drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
420	return 0;
421}
422
423static int amdgpu_pmops_runtime_idle(struct device *dev)
424{
425	struct pci_dev *pdev = to_pci_dev(dev);
426	struct drm_device *drm_dev = pci_get_drvdata(pdev);
427	struct drm_crtc *crtc;
428
429	if (!amdgpu_device_is_px(drm_dev)) {
430		pm_runtime_forbid(dev);
431		return -EBUSY;
432	}
433
434	list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
435		if (crtc->enabled) {
436			DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
437			return -EBUSY;
438		}
439	}
440
441	pm_runtime_mark_last_busy(dev);
442	pm_runtime_autosuspend(dev);
443	/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
444	return 1;
445}
446
447long amdgpu_drm_ioctl(struct file *filp,
448		      unsigned int cmd, unsigned long arg)
449{
450	struct drm_file *file_priv = filp->private_data;
451	struct drm_device *dev;
452	long ret;
453	dev = file_priv->minor->dev;
454	ret = pm_runtime_get_sync(dev->dev);
455	if (ret < 0)
456		return ret;
457
458	ret = drm_ioctl(filp, cmd, arg);
459
460	pm_runtime_mark_last_busy(dev->dev);
461	pm_runtime_put_autosuspend(dev->dev);
462	return ret;
463}
464
465static const struct dev_pm_ops amdgpu_pm_ops = {
466	.suspend = amdgpu_pmops_suspend,
467	.resume = amdgpu_pmops_resume,
468	.freeze = amdgpu_pmops_freeze,
469	.thaw = amdgpu_pmops_thaw,
470	.poweroff = amdgpu_pmops_freeze,
471	.restore = amdgpu_pmops_resume,
472	.runtime_suspend = amdgpu_pmops_runtime_suspend,
473	.runtime_resume = amdgpu_pmops_runtime_resume,
474	.runtime_idle = amdgpu_pmops_runtime_idle,
475};
476
477static const struct file_operations amdgpu_driver_kms_fops = {
478	.owner = THIS_MODULE,
479	.open = drm_open,
480	.release = drm_release,
481	.unlocked_ioctl = amdgpu_drm_ioctl,
482	.mmap = amdgpu_mmap,
483	.poll = drm_poll,
484	.read = drm_read,
485#ifdef CONFIG_COMPAT
486	.compat_ioctl = amdgpu_kms_compat_ioctl,
487#endif
488};
489
490static struct drm_driver kms_driver = {
491	.driver_features =
492	    DRIVER_USE_AGP |
493	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
494	    DRIVER_PRIME | DRIVER_RENDER,
495	.dev_priv_size = 0,
496	.load = amdgpu_driver_load_kms,
497	.open = amdgpu_driver_open_kms,
498	.preclose = amdgpu_driver_preclose_kms,
499	.postclose = amdgpu_driver_postclose_kms,
500	.lastclose = amdgpu_driver_lastclose_kms,
501	.set_busid = drm_pci_set_busid,
502	.unload = amdgpu_driver_unload_kms,
503	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
504	.enable_vblank = amdgpu_enable_vblank_kms,
505	.disable_vblank = amdgpu_disable_vblank_kms,
506	.get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
507	.get_scanout_position = amdgpu_get_crtc_scanoutpos,
508#if defined(CONFIG_DEBUG_FS)
509	.debugfs_init = amdgpu_debugfs_init,
510	.debugfs_cleanup = amdgpu_debugfs_cleanup,
511#endif
512	.irq_preinstall = amdgpu_irq_preinstall,
513	.irq_postinstall = amdgpu_irq_postinstall,
514	.irq_uninstall = amdgpu_irq_uninstall,
515	.irq_handler = amdgpu_irq_handler,
516	.ioctls = amdgpu_ioctls_kms,
517	.gem_free_object = amdgpu_gem_object_free,
518	.gem_open_object = amdgpu_gem_object_open,
519	.gem_close_object = amdgpu_gem_object_close,
520	.dumb_create = amdgpu_mode_dumb_create,
521	.dumb_map_offset = amdgpu_mode_dumb_mmap,
522	.dumb_destroy = drm_gem_dumb_destroy,
523	.fops = &amdgpu_driver_kms_fops,
524
525	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
526	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
527	.gem_prime_export = amdgpu_gem_prime_export,
528	.gem_prime_import = drm_gem_prime_import,
529	.gem_prime_pin = amdgpu_gem_prime_pin,
530	.gem_prime_unpin = amdgpu_gem_prime_unpin,
531	.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
532	.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
533	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
534	.gem_prime_vmap = amdgpu_gem_prime_vmap,
535	.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
536
537	.name = DRIVER_NAME,
538	.desc = DRIVER_DESC,
539	.date = DRIVER_DATE,
540	.major = KMS_DRIVER_MAJOR,
541	.minor = KMS_DRIVER_MINOR,
542	.patchlevel = KMS_DRIVER_PATCHLEVEL,
543};
544
545static struct drm_driver *driver;
546static struct pci_driver *pdriver;
547
548static struct pci_driver amdgpu_kms_pci_driver = {
549	.name = DRIVER_NAME,
550	.id_table = pciidlist,
551	.probe = amdgpu_pci_probe,
552	.remove = amdgpu_pci_remove,
553	.driver.pm = &amdgpu_pm_ops,
554};
555
556static int __init amdgpu_init(void)
557{
558	amdgpu_sync_init();
559#ifdef CONFIG_VGA_CONSOLE
560	if (vgacon_text_force()) {
561		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
562		return -EINVAL;
563	}
564#endif
565	DRM_INFO("amdgpu kernel modesetting enabled.\n");
566	driver = &kms_driver;
567	pdriver = &amdgpu_kms_pci_driver;
568	driver->driver_features |= DRIVER_MODESET;
569	driver->num_ioctls = amdgpu_max_kms_ioctl;
570	amdgpu_register_atpx_handler();
571
572	/* let modprobe override vga console setting */
573	return drm_pci_init(driver, pdriver);
574}
575
576static void __exit amdgpu_exit(void)
577{
578	amdgpu_amdkfd_fini();
579	drm_pci_exit(driver, pdriver);
580	amdgpu_unregister_atpx_handler();
581	amdgpu_sync_fini();
582}
583
584module_init(amdgpu_init);
585module_exit(amdgpu_exit);
586
587MODULE_AUTHOR(DRIVER_AUTHOR);
588MODULE_DESCRIPTION(DRIVER_DESC);
589MODULE_LICENSE("GPL and additional rights");