1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
 7 *	Douglas Leung <douglas@mips.com>
 8 *	Steven J. Hill <sjhill@mips.com>
 9 */
10#ifndef _MIPS_SEAD3INT_H
11#define _MIPS_SEAD3INT_H
12
13#include <linux/irqchip/mips-gic.h>
14
15/* SEAD-3 GIC address space definitions. */
16#define GIC_BASE_ADDR		0x1b1c0000
17#define GIC_ADDRSPACE_SZ	(128 * 1024)
18
19/* CPU interrupt offsets */
20#define CPU_INT_GIC		2
21#define CPU_INT_EHCI		2
22#define CPU_INT_UART0		4
23#define CPU_INT_UART1		4
24#define CPU_INT_NET		6
25
26/* GIC interrupt offsets */
27#define GIC_INT_NET		GIC_SHARED_TO_HWIRQ(0)
28#define GIC_INT_UART1		GIC_SHARED_TO_HWIRQ(2)
29#define GIC_INT_UART0		GIC_SHARED_TO_HWIRQ(3)
30#define GIC_INT_EHCI		GIC_SHARED_TO_HWIRQ(5)
31
32#endif /* !(_MIPS_SEAD3INT_H) */