1/*
 2 * Samsung's Exynos pinctrl bindings
 3 *
 4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 5 *		http://www.samsung.com
 6 * Author: Krzysztof Kozlowski <krzk@kernel.org>
 7 *
 8 * This program is free software; you can redistribute it and/or modify
 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
14#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
15
16#define EXYNOS_PIN_PULL_NONE		0
17#define EXYNOS_PIN_PULL_DOWN		1
18#define EXYNOS_PIN_PULL_UP		3
19
20#define S3C64XX_PIN_PULL_NONE		0
21#define S3C64XX_PIN_PULL_DOWN		1
22#define S3C64XX_PIN_PULL_UP		2
23
24/* Pin function in power down mode */
25#define EXYNOS_PIN_PDN_OUT0		0
26#define EXYNOS_PIN_PDN_OUT1		1
27#define EXYNOS_PIN_PDN_INPUT		2
28#define EXYNOS_PIN_PDN_PREV		3
29
30/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
31#define EXYNOS4_PIN_DRV_LV1		0
32#define EXYNOS4_PIN_DRV_LV2		2
33#define EXYNOS4_PIN_DRV_LV3		1
34#define EXYNOS4_PIN_DRV_LV4		3
35
36/* Drive strengths for Exynos5260 */
37#define EXYNOS5260_PIN_DRV_LV1		0
38#define EXYNOS5260_PIN_DRV_LV2		1
39#define EXYNOS5260_PIN_DRV_LV4		2
40#define EXYNOS5260_PIN_DRV_LV6		3
41
42/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */
43#define EXYNOS5420_PIN_DRV_LV1		0
44#define EXYNOS5420_PIN_DRV_LV2		1
45#define EXYNOS5420_PIN_DRV_LV3		2
46#define EXYNOS5420_PIN_DRV_LV4		3
47
48/* Drive strengths for Exynos5433 */
49#define EXYNOS5433_PIN_DRV_FAST_SR1	0
50#define EXYNOS5433_PIN_DRV_FAST_SR2	1
51#define EXYNOS5433_PIN_DRV_FAST_SR3	2
52#define EXYNOS5433_PIN_DRV_FAST_SR4	3
53#define EXYNOS5433_PIN_DRV_FAST_SR5	4
54#define EXYNOS5433_PIN_DRV_FAST_SR6	5
55#define EXYNOS5433_PIN_DRV_SLOW_SR1	8
56#define EXYNOS5433_PIN_DRV_SLOW_SR2	9
57#define EXYNOS5433_PIN_DRV_SLOW_SR3	0xa
58#define EXYNOS5433_PIN_DRV_SLOW_SR4	0xb
59#define EXYNOS5433_PIN_DRV_SLOW_SR5	0xc
60#define EXYNOS5433_PIN_DRV_SLOW_SR6	0xf
61
62#define EXYNOS_PIN_FUNC_INPUT		0
63#define EXYNOS_PIN_FUNC_OUTPUT		1
64#define EXYNOS_PIN_FUNC_2		2
65#define EXYNOS_PIN_FUNC_3		3
66#define EXYNOS_PIN_FUNC_4		4
67#define EXYNOS_PIN_FUNC_5		5
68#define EXYNOS_PIN_FUNC_6		6
69#define EXYNOS_PIN_FUNC_EINT		0xf
70#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT
71
72/* Drive strengths for Exynos7 FSYS1 block */
73#define EXYNOS7_FSYS1_PIN_DRV_LV1	0
74#define EXYNOS7_FSYS1_PIN_DRV_LV2	4
75#define EXYNOS7_FSYS1_PIN_DRV_LV3	2
76#define EXYNOS7_FSYS1_PIN_DRV_LV4	6
77#define EXYNOS7_FSYS1_PIN_DRV_LV5	1
78#define EXYNOS7_FSYS1_PIN_DRV_LV6	5
79
80#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */