1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 *  Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.
  4 *  All rights reserved.
  5 */
  6
  7#ifndef M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
  8#define M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H
  9
 10/*******************************************************************
 11 * Register Block
 12 * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_REGMAP
 13 *******************************************************************/
 14struct m00233_video_measure_regmap {
 15	uint32_t irq_status;        /* Reg 0x0000 */
 16	/* The vertical counter starts on rising edge of vsync */
 17	uint32_t vsync_time;        /* Reg 0x0004 */
 18	uint32_t vback_porch;       /* Reg 0x0008 */
 19	uint32_t vactive_area;      /* Reg 0x000c */
 20	uint32_t vfront_porch;      /* Reg 0x0010 */
 21	/* The horizontal counter starts on rising edge of hsync. */
 22	uint32_t hsync_time;        /* Reg 0x0014 */
 23	uint32_t hback_porch;       /* Reg 0x0018 */
 24	uint32_t hactive_area;      /* Reg 0x001c */
 25	uint32_t hfront_porch;      /* Reg 0x0020 */
 26	uint32_t control;           /* Reg 0x0024, Default=0x0 */
 27	uint32_t irq_triggers;      /* Reg 0x0028, Default=0xff */
 28	/* Value is given in number of register bus clock periods between */
 29	/* falling and rising edge of hsync. Must be non-zero. */
 30	uint32_t hsync_timeout_val; /* Reg 0x002c, Default=0x1fff */
 31	uint32_t status;            /* Reg 0x0030 */
 32};
 33
 34#define M00233_VIDEO_MEASURE_REG_IRQ_STATUS_OFST 0
 35#define M00233_VIDEO_MEASURE_REG_VSYNC_TIME_OFST 4
 36#define M00233_VIDEO_MEASURE_REG_VBACK_PORCH_OFST 8
 37#define M00233_VIDEO_MEASURE_REG_VACTIVE_AREA_OFST 12
 38#define M00233_VIDEO_MEASURE_REG_VFRONT_PORCH_OFST 16
 39#define M00233_VIDEO_MEASURE_REG_HSYNC_TIME_OFST 20
 40#define M00233_VIDEO_MEASURE_REG_HBACK_PORCH_OFST 24
 41#define M00233_VIDEO_MEASURE_REG_HACTIVE_AREA_OFST 28
 42#define M00233_VIDEO_MEASURE_REG_HFRONT_PORCH_OFST 32
 43#define M00233_VIDEO_MEASURE_REG_CONTROL_OFST 36
 44#define M00233_VIDEO_MEASURE_REG_IRQ_TRIGGERS_OFST 40
 45#define M00233_VIDEO_MEASURE_REG_HSYNC_TIMEOUT_VAL_OFST 44
 46#define M00233_VIDEO_MEASURE_REG_STATUS_OFST 48
 47
 48/*******************************************************************
 49 * Bit Mask for register
 50 * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_BITMAP
 51 *******************************************************************/
 52/* irq_status [7:0] */
 53#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST      (0)
 54#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_MSK       (0x1 << M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST)
 55#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST     (1)
 56#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_MSK      (0x1 << M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST)
 57#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST    (2)
 58#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST)
 59#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST    (3)
 60#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST)
 61#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST      (4)
 62#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_MSK       (0x1 << M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST)
 63#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST     (5)
 64#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_MSK      (0x1 << M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST)
 65#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST    (6)
 66#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST)
 67#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST    (7)
 68#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_MSK     (0x1 << M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST)
 69/* control [4:0] */
 70#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (0)
 71#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK  (0x1 << M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)
 72#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (1)
 73#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK  (0x1 << M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST)
 74#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST     (2)
 75#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK      (0x1 << M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST)
 76#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST   (3)
 77#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK    (0x1 << M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST)
 78#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST    (4)
 79#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK     (0x1 << M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST)
 80/* irq_triggers [7:0] */
 81#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST    (0)
 82#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_MSK     (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST)
 83#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST   (1)
 84#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_MSK    (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST)
 85#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST  (2)
 86#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST)
 87#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST  (3)
 88#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST)
 89#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST    (4)
 90#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_MSK     (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST)
 91#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST   (5)
 92#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_MSK    (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST)
 93#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST  (6)
 94#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST)
 95#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST  (7)
 96#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_MSK   (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST)
 97/* status [1:0] */
 98#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST       (0)
 99#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK        (0x1 << M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST)
100#define M00233_STATUS_BITMAP_INIT_DONE_OFST           (1)
101#define M00233_STATUS_BITMAP_INIT_DONE_MSK            (0x1 << M00233_STATUS_BITMAP_INIT_DONE_OFST)
102
103#endif /*M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H*/