1Amlogic specific extensions to the Synopsys Designware HDMI Controller
  2======================================================================
  3
  4The Amlogic Meson Synopsys Designware Integration is composed of :
  5- A Synopsys DesignWare HDMI Controller IP
  6- A TOP control block controlling the Clocks and PHY
  7- A custom HDMI PHY in order to convert video to TMDS signal
  8 ___________________________________
  9|            HDMI TOP               |<= HPD
 10|___________________________________|
 11|                  |                |
 12|  Synopsys HDMI   |   HDMI PHY     |=> TMDS
 13|    Controller    |________________|
 14|___________________________________|<=> DDC
 15
 16The HDMI TOP block only supports HPD sensing.
 17The Synopsys HDMI Controller interrupt is routed through the
 18TOP Block interrupt.
 19Communication to the TOP Block and the Synopsys HDMI Controller is done
 20via a pair of dedicated addr+read/write registers.
 21The HDMI PHY is configured by registers in the HHI register block.
 22
 23Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
 24selects either the ENCI encoder for the 576i or 480i formats or the ENCP
 25encoder for all the other formats including interlaced HD formats.
 26
 27The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
 28DVI timings for the HDMI controller.
 29
 30Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
 31HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
 32audio source interfaces.
 33
 34Required properties:
 35- compatible: value should be different for each SoC family as :
 36	- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
 37	- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
 38	- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
 39	followed by the common "amlogic,meson-gx-dw-hdmi"
 40- reg: Physical base address and length of the controller's registers.
 41- interrupts: The HDMI interrupt number
 42- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
 43  and the Amlogic Meson venci clocks as described in
 44  Documentation/devicetree/bindings/clock/clock-bindings.txt,
 45  the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
 46- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
 47  resets as described in :
 48  Documentation/devicetree/bindings/reset/reset.txt,
 49  the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
 50
 51Optional properties:
 52- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
 53  logic, as described in the file ../regulator/regulator.txt
 54
 55Required nodes:
 56
 57The connections to the HDMI ports are modeled using the OF graph
 58bindings specified in Documentation/devicetree/bindings/graph.txt.
 59
 60The following table lists for each supported model the port number
 61corresponding to each HDMI output and input.
 62
 63		Port 0		Port 1
 64-----------------------------------------
 65 S905 (GXBB)	VENC Input	TMDS Output
 66 S905X (GXL)	VENC Input	TMDS Output
 67 S905D (GXL)	VENC Input	TMDS Output
 68 S912 (GXM)	VENC Input	TMDS Output
 69
 70Example:
 71
 72hdmi-connector {
 73	compatible = "hdmi-connector";
 74	type = "a";
 75
 76	port {
 77		hdmi_connector_in: endpoint {
 78			remote-endpoint = <&hdmi_tx_tmds_out>;
 79		};
 80	};
 81};
 82
 83hdmi_tx: hdmi-tx@c883a000 {
 84	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 85	reg = <0x0 0xc883a000 0x0 0x1c>;
 86	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
 87	resets = <&reset RESET_HDMITX_CAPB3>,
 88		 <&reset RESET_HDMI_SYSTEM_RESET>,
 89		 <&reset RESET_HDMI_TX>;
 90	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 91	clocks = <&clkc CLKID_HDMI_PCLK>,
 92		 <&clkc CLKID_CLK81>,
 93		 <&clkc CLKID_GCLK_VENCI_INT0>;
 94	clock-names = "isfr", "iahb", "venci";
 95	#address-cells = <1>;
 96	#size-cells = <0>;
 97
 98	/* VPU VENC Input */
 99	hdmi_tx_venc_port: port@0 {
100		reg = <0>;
101
102		hdmi_tx_in: endpoint {
103			remote-endpoint = <&hdmi_tx_out>;
104		};
105	};
106
107	/* TMDS Output */
108	hdmi_tx_tmds_port: port@1 {
109		reg = <1>;
110
111		hdmi_tx_tmds_out: endpoint {
112			remote-endpoint = <&hdmi_connector_in>;
113		};
114	};
115};