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1/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
8 * based on davinci-mcasp.c DT support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * TODO:
15 * on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/platform_data/davinci_asp.h>
26
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/initval.h>
31#include <sound/soc.h>
32#include <sound/dmaengine_pcm.h>
33
34#include "edma-pcm.h"
35#include "davinci-i2s.h"
36
37#define DRV_NAME "davinci-i2s"
38
39/*
40 * NOTE: terminology here is confusing.
41 *
42 * - This driver supports the "Audio Serial Port" (ASP),
43 * found on dm6446, dm355, and other DaVinci chips.
44 *
45 * - But it labels it a "Multi-channel Buffered Serial Port"
46 * (McBSP) as on older chips like the dm642 ... which was
47 * backward-compatible, possibly explaining that confusion.
48 *
49 * - OMAP chips have a controller called McBSP, which is
50 * incompatible with the DaVinci flavor of McBSP.
51 *
52 * - Newer DaVinci chips have a controller called McASP,
53 * incompatible with ASP and with either McBSP.
54 *
55 * In short: this uses ASP to implement I2S, not McBSP.
56 * And it won't be the only DaVinci implemention of I2S.
57 */
58#define DAVINCI_MCBSP_DRR_REG 0x00
59#define DAVINCI_MCBSP_DXR_REG 0x04
60#define DAVINCI_MCBSP_SPCR_REG 0x08
61#define DAVINCI_MCBSP_RCR_REG 0x0c
62#define DAVINCI_MCBSP_XCR_REG 0x10
63#define DAVINCI_MCBSP_SRGR_REG 0x14
64#define DAVINCI_MCBSP_PCR_REG 0x24
65
66#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
67#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
68#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
69#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
70#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
71#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
72#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
73
74#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
75#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
76#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
77#define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
78#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
79#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
80#define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
81
82#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
83#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
84#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
85#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
86#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
87#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
88#define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
89
90#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
91#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
92#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
93#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
94
95#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
96#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
97#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
98#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
99#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
100#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
101#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
102#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
103#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
104
105enum {
106 DAVINCI_MCBSP_WORD_8 = 0,
107 DAVINCI_MCBSP_WORD_12,
108 DAVINCI_MCBSP_WORD_16,
109 DAVINCI_MCBSP_WORD_20,
110 DAVINCI_MCBSP_WORD_24,
111 DAVINCI_MCBSP_WORD_32,
112};
113
114static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
115 [SNDRV_PCM_FORMAT_S8] = 1,
116 [SNDRV_PCM_FORMAT_S16_LE] = 2,
117 [SNDRV_PCM_FORMAT_S32_LE] = 4,
118};
119
120static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
121 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
122 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
123 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
124};
125
126static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
127 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
128 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
129};
130
131struct davinci_mcbsp_dev {
132 struct device *dev;
133 struct snd_dmaengine_dai_dma_data dma_data[2];
134 int dma_request[2];
135 void __iomem *base;
136#define MOD_DSP_A 0
137#define MOD_DSP_B 1
138 int mode;
139 u32 pcr;
140 struct clk *clk;
141 /*
142 * Combining both channels into 1 element will at least double the
143 * amount of time between servicing the dma channel, increase
144 * effiency, and reduce the chance of overrun/underrun. But,
145 * it will result in the left & right channels being swapped.
146 *
147 * If relabeling the left and right channels is not possible,
148 * you may want to let the codec know to swap them back.
149 *
150 * It may allow x10 the amount of time to service dma requests,
151 * if the codec is master and is using an unnecessarily fast bit clock
152 * (ie. tlvaic23b), independent of the sample rate. So, having an
153 * entire frame at once means it can be serviced at the sample rate
154 * instead of the bit clock rate.
155 *
156 * In the now unlikely case that an underrun still
157 * occurs, both the left and right samples will be repeated
158 * so that no pops are heard, and the left and right channels
159 * won't end up being swapped because of the underrun.
160 */
161 unsigned enable_channel_combine:1;
162
163 unsigned int fmt;
164 int clk_div;
165 int clk_input_pin;
166 bool i2s_accurate_sck;
167};
168
169static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
170 int reg, u32 val)
171{
172 __raw_writel(val, dev->base + reg);
173}
174
175static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
176{
177 return __raw_readl(dev->base + reg);
178}
179
180static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
181{
182 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
183 /* The clock needs to toggle to complete reset.
184 * So, fake it by toggling the clk polarity.
185 */
186 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
187 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
188}
189
190static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
191 struct snd_pcm_substream *substream)
192{
193 struct snd_soc_pcm_runtime *rtd = substream->private_data;
194 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
195 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
196 u32 spcr;
197 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
198 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
199 if (spcr & mask) {
200 /* start off disabled */
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
202 spcr & ~mask);
203 toggle_clock(dev, playback);
204 }
205 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
206 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
207 /* Start the sample generator */
208 spcr |= DAVINCI_MCBSP_SPCR_GRST;
209 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
210 }
211
212 if (playback) {
213 /* Stop the DMA to avoid data loss */
214 /* while the transmitter is out of reset to handle XSYNCERR */
215 if (component->driver->ops->trigger) {
216 int ret = component->driver->ops->trigger(substream,
217 SNDRV_PCM_TRIGGER_STOP);
218 if (ret < 0)
219 printk(KERN_DEBUG "Playback DMA stop failed\n");
220 }
221
222 /* Enable the transmitter */
223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr |= DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
226
227 /* wait for any unexpected frame sync error to occur */
228 udelay(100);
229
230 /* Disable the transmitter to clear any outstanding XSYNCERR */
231 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
232 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
233 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
234 toggle_clock(dev, playback);
235
236 /* Restart the DMA */
237 if (component->driver->ops->trigger) {
238 int ret = component->driver->ops->trigger(substream,
239 SNDRV_PCM_TRIGGER_START);
240 if (ret < 0)
241 printk(KERN_DEBUG "Playback DMA start failed\n");
242 }
243 }
244
245 /* Enable transmitter or receiver */
246 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
247 spcr |= mask;
248
249 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
250 /* Start frame sync */
251 spcr |= DAVINCI_MCBSP_SPCR_FRST;
252 }
253 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
254}
255
256static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
257{
258 u32 spcr;
259
260 /* Reset transmitter/receiver and sample rate/frame sync generators */
261 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
262 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
263 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
264 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
265 toggle_clock(dev, playback);
266}
267
268#define DEFAULT_BITPERSAMPLE 16
269
270static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
271 unsigned int fmt)
272{
273 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
274 unsigned int pcr;
275 unsigned int srgr;
276 bool inv_fs = false;
277 /* Attention srgr is updated by hw_params! */
278 srgr = DAVINCI_MCBSP_SRGR_FSGM |
279 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
280 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
281
282 dev->fmt = fmt;
283 /* set master/slave audio interface */
284 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
285 case SND_SOC_DAIFMT_CBS_CFS:
286 /* cpu is master */
287 pcr = DAVINCI_MCBSP_PCR_FSXM |
288 DAVINCI_MCBSP_PCR_FSRM |
289 DAVINCI_MCBSP_PCR_CLKXM |
290 DAVINCI_MCBSP_PCR_CLKRM;
291 break;
292 case SND_SOC_DAIFMT_CBM_CFS:
293 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
294 /*
295 * Selection of the clock input pin that is the
296 * input for the Sample Rate Generator.
297 * McBSP FSR and FSX are driven by the Sample Rate
298 * Generator.
299 */
300 switch (dev->clk_input_pin) {
301 case MCBSP_CLKS:
302 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
303 DAVINCI_MCBSP_PCR_CLKRM;
304 break;
305 case MCBSP_CLKR:
306 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
307 break;
308 default:
309 dev_err(dev->dev, "bad clk_input_pin\n");
310 return -EINVAL;
311 }
312
313 break;
314 case SND_SOC_DAIFMT_CBM_CFM:
315 /* codec is master */
316 pcr = 0;
317 break;
318 default:
319 printk(KERN_ERR "%s:bad master\n", __func__);
320 return -EINVAL;
321 }
322
323 /* interface format */
324 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
325 case SND_SOC_DAIFMT_I2S:
326 /* Davinci doesn't support TRUE I2S, but some codecs will have
327 * the left and right channels contiguous. This allows
328 * dsp_a mode to be used with an inverted normal frame clk.
329 * If your codec is master and does not have contiguous
330 * channels, then you will have sound on only one channel.
331 * Try using a different mode, or codec as slave.
332 *
333 * The TLV320AIC33 is an example of a codec where this works.
334 * It has a variable bit clock frequency allowing it to have
335 * valid data on every bit clock.
336 *
337 * The TLV320AIC23 is an example of a codec where this does not
338 * work. It has a fixed bit clock frequency with progressively
339 * more empty bit clock slots between channels as the sample
340 * rate is lowered.
341 */
342 inv_fs = true;
343 case SND_SOC_DAIFMT_DSP_A:
344 dev->mode = MOD_DSP_A;
345 break;
346 case SND_SOC_DAIFMT_DSP_B:
347 dev->mode = MOD_DSP_B;
348 break;
349 default:
350 printk(KERN_ERR "%s:bad format\n", __func__);
351 return -EINVAL;
352 }
353
354 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
355 case SND_SOC_DAIFMT_NB_NF:
356 /* CLKRP Receive clock polarity,
357 * 1 - sampled on rising edge of CLKR
358 * valid on rising edge
359 * CLKXP Transmit clock polarity,
360 * 1 - clocked on falling edge of CLKX
361 * valid on rising edge
362 * FSRP Receive frame sync pol, 0 - active high
363 * FSXP Transmit frame sync pol, 0 - active high
364 */
365 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
366 break;
367 case SND_SOC_DAIFMT_IB_IF:
368 /* CLKRP Receive clock polarity,
369 * 0 - sampled on falling edge of CLKR
370 * valid on falling edge
371 * CLKXP Transmit clock polarity,
372 * 0 - clocked on rising edge of CLKX
373 * valid on falling edge
374 * FSRP Receive frame sync pol, 1 - active low
375 * FSXP Transmit frame sync pol, 1 - active low
376 */
377 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
378 break;
379 case SND_SOC_DAIFMT_NB_IF:
380 /* CLKRP Receive clock polarity,
381 * 1 - sampled on rising edge of CLKR
382 * valid on rising edge
383 * CLKXP Transmit clock polarity,
384 * 1 - clocked on falling edge of CLKX
385 * valid on rising edge
386 * FSRP Receive frame sync pol, 1 - active low
387 * FSXP Transmit frame sync pol, 1 - active low
388 */
389 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
390 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
391 break;
392 case SND_SOC_DAIFMT_IB_NF:
393 /* CLKRP Receive clock polarity,
394 * 0 - sampled on falling edge of CLKR
395 * valid on falling edge
396 * CLKXP Transmit clock polarity,
397 * 0 - clocked on rising edge of CLKX
398 * valid on falling edge
399 * FSRP Receive frame sync pol, 0 - active high
400 * FSXP Transmit frame sync pol, 0 - active high
401 */
402 break;
403 default:
404 return -EINVAL;
405 }
406 if (inv_fs == true)
407 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
408 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
409 dev->pcr = pcr;
410 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
411 return 0;
412}
413
414static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
415 int div_id, int div)
416{
417 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
418
419 if (div_id != DAVINCI_MCBSP_CLKGDV)
420 return -ENODEV;
421
422 dev->clk_div = div;
423 return 0;
424}
425
426static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
427 struct snd_pcm_hw_params *params,
428 struct snd_soc_dai *dai)
429{
430 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
431 struct snd_interval *i = NULL;
432 int mcbsp_word_length, master;
433 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
434 u32 spcr;
435 snd_pcm_format_t fmt;
436 unsigned element_cnt = 1;
437
438 /* general line settings */
439 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
440 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
441 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
442 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
443 } else {
444 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
445 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
446 }
447
448 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
449 fmt = params_format(params);
450 mcbsp_word_length = asp_word_length[fmt];
451
452 switch (master) {
453 case SND_SOC_DAIFMT_CBS_CFS:
454 freq = clk_get_rate(dev->clk);
455 srgr = DAVINCI_MCBSP_SRGR_FSGM |
456 DAVINCI_MCBSP_SRGR_CLKSM;
457 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
458 8 - 1);
459 if (dev->i2s_accurate_sck) {
460 clk_div = 256;
461 do {
462 framesize = (freq / (--clk_div)) /
463 params->rate_num *
464 params->rate_den;
465 } while (((framesize < 33) || (framesize > 4095)) &&
466 (clk_div));
467 clk_div--;
468 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
469 } else {
470 /* symmetric waveforms */
471 clk_div = freq / (mcbsp_word_length * 16) /
472 params->rate_num * params->rate_den;
473 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
474 16 - 1);
475 }
476 clk_div &= 0xFF;
477 srgr |= clk_div;
478 break;
479 case SND_SOC_DAIFMT_CBM_CFS:
480 srgr = DAVINCI_MCBSP_SRGR_FSGM;
481 clk_div = dev->clk_div - 1;
482 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
483 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
484 clk_div &= 0xFF;
485 srgr |= clk_div;
486 break;
487 case SND_SOC_DAIFMT_CBM_CFM:
488 /* Clock and frame sync given from external sources */
489 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
490 srgr = DAVINCI_MCBSP_SRGR_FSGM;
491 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
492 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
493 __func__, __LINE__, snd_interval_value(i) - 1);
494
495 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
496 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
497 break;
498 default:
499 return -EINVAL;
500 }
501 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
502
503 rcr = DAVINCI_MCBSP_RCR_RFIG;
504 xcr = DAVINCI_MCBSP_XCR_XFIG;
505 if (dev->mode == MOD_DSP_B) {
506 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
507 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
508 } else {
509 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
510 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
511 }
512 /* Determine xfer data type */
513 fmt = params_format(params);
514 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
515 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
516 return -EINVAL;
517 }
518
519 if (params_channels(params) == 2) {
520 element_cnt = 2;
521 if (double_fmt[fmt] && dev->enable_channel_combine) {
522 element_cnt = 1;
523 fmt = double_fmt[fmt];
524 }
525 switch (master) {
526 case SND_SOC_DAIFMT_CBS_CFS:
527 case SND_SOC_DAIFMT_CBS_CFM:
528 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
529 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
530 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
531 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
532 break;
533 case SND_SOC_DAIFMT_CBM_CFM:
534 case SND_SOC_DAIFMT_CBM_CFS:
535 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
536 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
537 break;
538 default:
539 return -EINVAL;
540 }
541 }
542 mcbsp_word_length = asp_word_length[fmt];
543
544 switch (master) {
545 case SND_SOC_DAIFMT_CBS_CFS:
546 case SND_SOC_DAIFMT_CBS_CFM:
547 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
548 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
549 break;
550 case SND_SOC_DAIFMT_CBM_CFM:
551 case SND_SOC_DAIFMT_CBM_CFS:
552 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
553 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
560 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
561 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
562 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
563
564 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
565 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
566 else
567 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
568
569 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
570 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
571 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
572 return 0;
573}
574
575static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
576 struct snd_soc_dai *dai)
577{
578 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
579 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
580 davinci_mcbsp_stop(dev, playback);
581 return 0;
582}
583
584static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
585 struct snd_soc_dai *dai)
586{
587 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
588 int ret = 0;
589 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
590
591 switch (cmd) {
592 case SNDRV_PCM_TRIGGER_START:
593 case SNDRV_PCM_TRIGGER_RESUME:
594 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
595 davinci_mcbsp_start(dev, substream);
596 break;
597 case SNDRV_PCM_TRIGGER_STOP:
598 case SNDRV_PCM_TRIGGER_SUSPEND:
599 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
600 davinci_mcbsp_stop(dev, playback);
601 break;
602 default:
603 ret = -EINVAL;
604 }
605 return ret;
606}
607
608static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
609 struct snd_soc_dai *dai)
610{
611 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
612 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
613 davinci_mcbsp_stop(dev, playback);
614}
615
616#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
617
618static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
619 .shutdown = davinci_i2s_shutdown,
620 .prepare = davinci_i2s_prepare,
621 .trigger = davinci_i2s_trigger,
622 .hw_params = davinci_i2s_hw_params,
623 .set_fmt = davinci_i2s_set_dai_fmt,
624 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
625
626};
627
628static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
629{
630 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
631
632 dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
633 dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
634
635 return 0;
636}
637
638static struct snd_soc_dai_driver davinci_i2s_dai = {
639 .probe = davinci_i2s_dai_probe,
640 .playback = {
641 .channels_min = 2,
642 .channels_max = 2,
643 .rates = DAVINCI_I2S_RATES,
644 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
645 .capture = {
646 .channels_min = 2,
647 .channels_max = 2,
648 .rates = DAVINCI_I2S_RATES,
649 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
650 .ops = &davinci_i2s_dai_ops,
651
652};
653
654static const struct snd_soc_component_driver davinci_i2s_component = {
655 .name = DRV_NAME,
656};
657
658static int davinci_i2s_probe(struct platform_device *pdev)
659{
660 struct snd_dmaengine_dai_dma_data *dma_data;
661 struct davinci_mcbsp_dev *dev;
662 struct resource *mem, *res;
663 void __iomem *io_base;
664 int *dma;
665 int ret;
666
667 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
668 if (!mem) {
669 dev_warn(&pdev->dev,
670 "\"mpu\" mem resource not found, using index 0\n");
671 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 if (!mem) {
673 dev_err(&pdev->dev, "no mem resource?\n");
674 return -ENODEV;
675 }
676 }
677
678 io_base = devm_ioremap_resource(&pdev->dev, mem);
679 if (IS_ERR(io_base))
680 return PTR_ERR(io_base);
681
682 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
683 GFP_KERNEL);
684 if (!dev)
685 return -ENOMEM;
686
687 dev->base = io_base;
688
689 /* setup DMA, first TX, then RX */
690 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
691 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
692
693 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
694 if (res) {
695 dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
696 *dma = res->start;
697 dma_data->filter_data = dma;
698 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
699 dma_data->filter_data = "tx";
700 } else {
701 dev_err(&pdev->dev, "Missing DMA tx resource\n");
702 return -ENODEV;
703 }
704
705 dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
706 dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
707
708 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
709 if (res) {
710 dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
711 *dma = res->start;
712 dma_data->filter_data = dma;
713 } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
714 dma_data->filter_data = "rx";
715 } else {
716 dev_err(&pdev->dev, "Missing DMA rx resource\n");
717 return -ENODEV;
718 }
719
720 dev->clk = clk_get(&pdev->dev, NULL);
721 if (IS_ERR(dev->clk))
722 return -ENODEV;
723 clk_enable(dev->clk);
724
725 dev->dev = &pdev->dev;
726 dev_set_drvdata(&pdev->dev, dev);
727
728 ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
729 &davinci_i2s_dai, 1);
730 if (ret != 0)
731 goto err_release_clk;
732
733 ret = edma_pcm_platform_register(&pdev->dev);
734 if (ret) {
735 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
736 goto err_unregister_component;
737 }
738
739 return 0;
740
741err_unregister_component:
742 snd_soc_unregister_component(&pdev->dev);
743err_release_clk:
744 clk_disable(dev->clk);
745 clk_put(dev->clk);
746 return ret;
747}
748
749static int davinci_i2s_remove(struct platform_device *pdev)
750{
751 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
752
753 snd_soc_unregister_component(&pdev->dev);
754
755 clk_disable(dev->clk);
756 clk_put(dev->clk);
757 dev->clk = NULL;
758
759 return 0;
760}
761
762static const struct of_device_id davinci_i2s_match[] = {
763 { .compatible = "ti,da850-mcbsp" },
764 {},
765};
766MODULE_DEVICE_TABLE(of, davinci_i2s_match);
767
768static struct platform_driver davinci_mcbsp_driver = {
769 .probe = davinci_i2s_probe,
770 .remove = davinci_i2s_remove,
771 .driver = {
772 .name = "davinci-mcbsp",
773 .of_match_table = of_match_ptr(davinci_i2s_match),
774 },
775};
776
777module_platform_driver(davinci_mcbsp_driver);
778
779MODULE_AUTHOR("Vladimir Barinov");
780MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
781MODULE_LICENSE("GPL");