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1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
4 * Copyright (C) 2022 StarFive Technology Co., Ltd.
5 */
6
7#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
8#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
9
10/* SYSCRG resets */
11#define JH7110_SYSRST_JTAG_APB 0
12#define JH7110_SYSRST_SYSCON_APB 1
13#define JH7110_SYSRST_IOMUX_APB 2
14#define JH7110_SYSRST_BUS 3
15#define JH7110_SYSRST_DEBUG 4
16#define JH7110_SYSRST_CORE0 5
17#define JH7110_SYSRST_CORE1 6
18#define JH7110_SYSRST_CORE2 7
19#define JH7110_SYSRST_CORE3 8
20#define JH7110_SYSRST_CORE4 9
21#define JH7110_SYSRST_CORE0_ST 10
22#define JH7110_SYSRST_CORE1_ST 11
23#define JH7110_SYSRST_CORE2_ST 12
24#define JH7110_SYSRST_CORE3_ST 13
25#define JH7110_SYSRST_CORE4_ST 14
26#define JH7110_SYSRST_TRACE0 15
27#define JH7110_SYSRST_TRACE1 16
28#define JH7110_SYSRST_TRACE2 17
29#define JH7110_SYSRST_TRACE3 18
30#define JH7110_SYSRST_TRACE4 19
31#define JH7110_SYSRST_TRACE_COM 20
32#define JH7110_SYSRST_GPU_APB 21
33#define JH7110_SYSRST_GPU_DOMA 22
34#define JH7110_SYSRST_NOC_BUS_APB 23
35#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
36#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
37#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
38#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
39#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
40#define JH7110_SYSRST_NOC_BUS_DDRC 29
41#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
42#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
43
44#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
45#define JH7110_SYSRST_AXI_CFG1_AHB 33
46#define JH7110_SYSRST_AXI_CFG1_MAIN 34
47#define JH7110_SYSRST_AXI_CFG0_MAIN 35
48#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
49#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
50#define JH7110_SYSRST_DDR_AXI 38
51#define JH7110_SYSRST_DDR_OSC 39
52#define JH7110_SYSRST_DDR_APB 40
53#define JH7110_SYSRST_ISP_TOP 41
54#define JH7110_SYSRST_ISP_TOP_AXI 42
55#define JH7110_SYSRST_VOUT_TOP_SRC 43
56#define JH7110_SYSRST_CODAJ12_AXI 44
57#define JH7110_SYSRST_CODAJ12_CORE 45
58#define JH7110_SYSRST_CODAJ12_APB 46
59#define JH7110_SYSRST_WAVE511_AXI 47
60#define JH7110_SYSRST_WAVE511_BPU 48
61#define JH7110_SYSRST_WAVE511_VCE 49
62#define JH7110_SYSRST_WAVE511_APB 50
63#define JH7110_SYSRST_VDEC_JPG 51
64#define JH7110_SYSRST_VDEC_MAIN 52
65#define JH7110_SYSRST_AXIMEM0_AXI 53
66#define JH7110_SYSRST_WAVE420L_AXI 54
67#define JH7110_SYSRST_WAVE420L_BPU 55
68#define JH7110_SYSRST_WAVE420L_VCE 56
69#define JH7110_SYSRST_WAVE420L_APB 57
70#define JH7110_SYSRST_AXIMEM1_AXI 58
71#define JH7110_SYSRST_AXIMEM2_AXI 59
72#define JH7110_SYSRST_INTMEM 60
73#define JH7110_SYSRST_QSPI_AHB 61
74#define JH7110_SYSRST_QSPI_APB 62
75#define JH7110_SYSRST_QSPI_REF 63
76
77#define JH7110_SYSRST_SDIO0_AHB 64
78#define JH7110_SYSRST_SDIO1_AHB 65
79#define JH7110_SYSRST_GMAC1_AXI 66
80#define JH7110_SYSRST_GMAC1_AHB 67
81#define JH7110_SYSRST_MAILBOX_APB 68
82#define JH7110_SYSRST_SPI0_APB 69
83#define JH7110_SYSRST_SPI1_APB 70
84#define JH7110_SYSRST_SPI2_APB 71
85#define JH7110_SYSRST_SPI3_APB 72
86#define JH7110_SYSRST_SPI4_APB 73
87#define JH7110_SYSRST_SPI5_APB 74
88#define JH7110_SYSRST_SPI6_APB 75
89#define JH7110_SYSRST_I2C0_APB 76
90#define JH7110_SYSRST_I2C1_APB 77
91#define JH7110_SYSRST_I2C2_APB 78
92#define JH7110_SYSRST_I2C3_APB 79
93#define JH7110_SYSRST_I2C4_APB 80
94#define JH7110_SYSRST_I2C5_APB 81
95#define JH7110_SYSRST_I2C6_APB 82
96#define JH7110_SYSRST_UART0_APB 83
97#define JH7110_SYSRST_UART0_CORE 84
98#define JH7110_SYSRST_UART1_APB 85
99#define JH7110_SYSRST_UART1_CORE 86
100#define JH7110_SYSRST_UART2_APB 87
101#define JH7110_SYSRST_UART2_CORE 88
102#define JH7110_SYSRST_UART3_APB 89
103#define JH7110_SYSRST_UART3_CORE 90
104#define JH7110_SYSRST_UART4_APB 91
105#define JH7110_SYSRST_UART4_CORE 92
106#define JH7110_SYSRST_UART5_APB 93
107#define JH7110_SYSRST_UART5_CORE 94
108#define JH7110_SYSRST_SPDIF_APB 95
109
110#define JH7110_SYSRST_PWMDAC_APB 96
111#define JH7110_SYSRST_PDM_DMIC 97
112#define JH7110_SYSRST_PDM_APB 98
113#define JH7110_SYSRST_I2SRX_APB 99
114#define JH7110_SYSRST_I2SRX_BCLK 100
115#define JH7110_SYSRST_I2STX0_APB 101
116#define JH7110_SYSRST_I2STX0_BCLK 102
117#define JH7110_SYSRST_I2STX1_APB 103
118#define JH7110_SYSRST_I2STX1_BCLK 104
119#define JH7110_SYSRST_TDM_AHB 105
120#define JH7110_SYSRST_TDM_CORE 106
121#define JH7110_SYSRST_TDM_APB 107
122#define JH7110_SYSRST_PWM_APB 108
123#define JH7110_SYSRST_WDT_APB 109
124#define JH7110_SYSRST_WDT_CORE 110
125#define JH7110_SYSRST_CAN0_APB 111
126#define JH7110_SYSRST_CAN0_CORE 112
127#define JH7110_SYSRST_CAN0_TIMER 113
128#define JH7110_SYSRST_CAN1_APB 114
129#define JH7110_SYSRST_CAN1_CORE 115
130#define JH7110_SYSRST_CAN1_TIMER 116
131#define JH7110_SYSRST_TIMER_APB 117
132#define JH7110_SYSRST_TIMER0 118
133#define JH7110_SYSRST_TIMER1 119
134#define JH7110_SYSRST_TIMER2 120
135#define JH7110_SYSRST_TIMER3 121
136#define JH7110_SYSRST_INT_CTRL_APB 122
137#define JH7110_SYSRST_TEMP_APB 123
138#define JH7110_SYSRST_TEMP_CORE 124
139#define JH7110_SYSRST_JTAG_CERTIFICATION 125
140
141#define JH7110_SYSRST_END 126
142
143/* AONCRG resets */
144#define JH7110_AONRST_GMAC0_AXI 0
145#define JH7110_AONRST_GMAC0_AHB 1
146#define JH7110_AONRST_IOMUX 2
147#define JH7110_AONRST_PMU_APB 3
148#define JH7110_AONRST_PMU_WKUP 4
149#define JH7110_AONRST_RTC_APB 5
150#define JH7110_AONRST_RTC_CAL 6
151#define JH7110_AONRST_RTC_32K 7
152
153#define JH7110_AONRST_END 8
154
155/* STGCRG resets */
156#define JH7110_STGRST_SYSCON 0
157#define JH7110_STGRST_HIFI4_CORE 1
158#define JH7110_STGRST_HIFI4_AXI 2
159#define JH7110_STGRST_SEC_AHB 3
160#define JH7110_STGRST_E24_CORE 4
161#define JH7110_STGRST_DMA1P_AXI 5
162#define JH7110_STGRST_DMA1P_AHB 6
163#define JH7110_STGRST_USB0_AXI 7
164#define JH7110_STGRST_USB0_APB 8
165#define JH7110_STGRST_USB0_UTMI_APB 9
166#define JH7110_STGRST_USB0_PWRUP 10
167#define JH7110_STGRST_PCIE0_AXI_MST0 11
168#define JH7110_STGRST_PCIE0_AXI_SLV0 12
169#define JH7110_STGRST_PCIE0_AXI_SLV 13
170#define JH7110_STGRST_PCIE0_BRG 14
171#define JH7110_STGRST_PCIE0_CORE 15
172#define JH7110_STGRST_PCIE0_APB 16
173#define JH7110_STGRST_PCIE1_AXI_MST0 17
174#define JH7110_STGRST_PCIE1_AXI_SLV0 18
175#define JH7110_STGRST_PCIE1_AXI_SLV 19
176#define JH7110_STGRST_PCIE1_BRG 20
177#define JH7110_STGRST_PCIE1_CORE 21
178#define JH7110_STGRST_PCIE1_APB 22
179
180#define JH7110_STGRST_END 23
181
182/* ISPCRG resets */
183#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
184#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
185#define JH7110_ISPRST_M31DPHY_HW 2
186#define JH7110_ISPRST_M31DPHY_B09_AON 3
187#define JH7110_ISPRST_VIN_APB 4
188#define JH7110_ISPRST_VIN_PIXEL_IF0 5
189#define JH7110_ISPRST_VIN_PIXEL_IF1 6
190#define JH7110_ISPRST_VIN_PIXEL_IF2 7
191#define JH7110_ISPRST_VIN_PIXEL_IF3 8
192#define JH7110_ISPRST_VIN_SYS 9
193#define JH7110_ISPRST_VIN_P_AXI_RD 10
194#define JH7110_ISPRST_VIN_P_AXI_WR 11
195
196#define JH7110_ISPRST_END 12
197
198/* VOUTCRG resets */
199#define JH7110_VOUTRST_DC8200_AXI 0
200#define JH7110_VOUTRST_DC8200_AHB 1
201#define JH7110_VOUTRST_DC8200_CORE 2
202#define JH7110_VOUTRST_DSITX_DPI 3
203#define JH7110_VOUTRST_DSITX_APB 4
204#define JH7110_VOUTRST_DSITX_RXESC 5
205#define JH7110_VOUTRST_DSITX_SYS 6
206#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
207#define JH7110_VOUTRST_DSITX_TXESC 8
208#define JH7110_VOUTRST_HDMI_TX_HDMI 9
209#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
210#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
211
212#define JH7110_VOUTRST_END 12
213
214#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */