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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __DTS_MARVELL_PXA168_CLOCK_H
3#define __DTS_MARVELL_PXA168_CLOCK_H
4
5/* fixed clocks and plls */
6#define PXA168_CLK_CLK32 1
7#define PXA168_CLK_VCTCXO 2
8#define PXA168_CLK_PLL1 3
9#define PXA168_CLK_PLL1_2 8
10#define PXA168_CLK_PLL1_4 9
11#define PXA168_CLK_PLL1_8 10
12#define PXA168_CLK_PLL1_16 11
13#define PXA168_CLK_PLL1_6 12
14#define PXA168_CLK_PLL1_12 13
15#define PXA168_CLK_PLL1_24 14
16#define PXA168_CLK_PLL1_48 15
17#define PXA168_CLK_PLL1_96 16
18#define PXA168_CLK_PLL1_13 17
19#define PXA168_CLK_PLL1_13_1_5 18
20#define PXA168_CLK_PLL1_2_1_5 19
21#define PXA168_CLK_PLL1_3_16 20
22#define PXA168_CLK_PLL1_192 21
23#define PXA168_CLK_UART_PLL 27
24#define PXA168_CLK_USB_PLL 28
25
26/* apb periphrals */
27#define PXA168_CLK_TWSI0 60
28#define PXA168_CLK_TWSI1 61
29#define PXA168_CLK_TWSI2 62
30#define PXA168_CLK_TWSI3 63
31#define PXA168_CLK_GPIO 64
32#define PXA168_CLK_KPC 65
33#define PXA168_CLK_RTC 66
34#define PXA168_CLK_PWM0 67
35#define PXA168_CLK_PWM1 68
36#define PXA168_CLK_PWM2 69
37#define PXA168_CLK_PWM3 70
38#define PXA168_CLK_UART0 71
39#define PXA168_CLK_UART1 72
40#define PXA168_CLK_UART2 73
41#define PXA168_CLK_SSP0 74
42#define PXA168_CLK_SSP1 75
43#define PXA168_CLK_SSP2 76
44#define PXA168_CLK_SSP3 77
45#define PXA168_CLK_SSP4 78
46#define PXA168_CLK_TIMER 79
47
48/* axi periphrals */
49#define PXA168_CLK_DFC 100
50#define PXA168_CLK_SDH0 101
51#define PXA168_CLK_SDH1 102
52#define PXA168_CLK_SDH2 103
53#define PXA168_CLK_USB 104
54#define PXA168_CLK_SPH 105
55#define PXA168_CLK_DISP0 106
56#define PXA168_CLK_CCIC0 107
57#define PXA168_CLK_CCIC0_PHY 108
58#define PXA168_CLK_CCIC0_SPHY 109
59
60#define PXA168_NR_CLKS 200
61#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __DTS_MARVELL_PXA168_CLOCK_H
3#define __DTS_MARVELL_PXA168_CLOCK_H
4
5/* fixed clocks and plls */
6#define PXA168_CLK_CLK32 1
7#define PXA168_CLK_VCTCXO 2
8#define PXA168_CLK_PLL1 3
9#define PXA168_CLK_PLL1_2 8
10#define PXA168_CLK_PLL1_4 9
11#define PXA168_CLK_PLL1_8 10
12#define PXA168_CLK_PLL1_16 11
13#define PXA168_CLK_PLL1_6 12
14#define PXA168_CLK_PLL1_12 13
15#define PXA168_CLK_PLL1_24 14
16#define PXA168_CLK_PLL1_48 15
17#define PXA168_CLK_PLL1_96 16
18#define PXA168_CLK_PLL1_13 17
19#define PXA168_CLK_PLL1_13_1_5 18
20#define PXA168_CLK_PLL1_2_1_5 19
21#define PXA168_CLK_PLL1_3_16 20
22#define PXA168_CLK_PLL1_192 21
23#define PXA168_CLK_PLL1_2_1_10 22
24#define PXA168_CLK_PLL1_2_3_16 23
25#define PXA168_CLK_UART_PLL 27
26#define PXA168_CLK_USB_PLL 28
27#define PXA168_CLK_CLK32_2 50
28
29/* apb peripherals */
30#define PXA168_CLK_TWSI0 60
31#define PXA168_CLK_TWSI1 61
32#define PXA168_CLK_TWSI2 62
33#define PXA168_CLK_TWSI3 63
34#define PXA168_CLK_GPIO 64
35#define PXA168_CLK_KPC 65
36#define PXA168_CLK_RTC 66
37#define PXA168_CLK_PWM0 67
38#define PXA168_CLK_PWM1 68
39#define PXA168_CLK_PWM2 69
40#define PXA168_CLK_PWM3 70
41#define PXA168_CLK_UART0 71
42#define PXA168_CLK_UART1 72
43#define PXA168_CLK_UART2 73
44#define PXA168_CLK_SSP0 74
45#define PXA168_CLK_SSP1 75
46#define PXA168_CLK_SSP2 76
47#define PXA168_CLK_SSP3 77
48#define PXA168_CLK_SSP4 78
49#define PXA168_CLK_TIMER 79
50
51/* axi peripherals */
52#define PXA168_CLK_DFC 100
53#define PXA168_CLK_SDH0 101
54#define PXA168_CLK_SDH1 102
55#define PXA168_CLK_SDH2 103
56#define PXA168_CLK_USB 104
57#define PXA168_CLK_SPH 105
58#define PXA168_CLK_DISP0 106
59#define PXA168_CLK_CCIC0 107
60#define PXA168_CLK_CCIC0_PHY 108
61#define PXA168_CLK_CCIC0_SPHY 109
62#define PXA168_CLK_SDH3 110
63#define PXA168_CLK_SDH01_AXI 111
64#define PXA168_CLK_SDH23_AXI 112
65
66#endif