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1// SPDX-License-Identifier: GPL-2.0
2/**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/version.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/interrupt.h>
19#include <linux/ioport.h>
20#include <linux/io.h>
21#include <linux/list.h>
22#include <linux/delay.h>
23#include <linux/dma-mapping.h>
24#include <linux/of.h>
25#include <linux/acpi.h>
26#include <linux/pinctrl/consumer.h>
27
28#include <linux/usb/ch9.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/of.h>
31#include <linux/usb/otg.h>
32
33#include "core.h"
34#include "gadget.h"
35#include "io.h"
36
37#include "debug.h"
38
39#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
40
41/**
42 * dwc3_get_dr_mode - Validates and sets dr_mode
43 * @dwc: pointer to our context structure
44 */
45static int dwc3_get_dr_mode(struct dwc3 *dwc)
46{
47 enum usb_dr_mode mode;
48 struct device *dev = dwc->dev;
49 unsigned int hw_mode;
50
51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
52 dwc->dr_mode = USB_DR_MODE_OTG;
53
54 mode = dwc->dr_mode;
55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
56
57 switch (hw_mode) {
58 case DWC3_GHWPARAMS0_MODE_GADGET:
59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
60 dev_err(dev,
61 "Controller does not support host mode.\n");
62 return -EINVAL;
63 }
64 mode = USB_DR_MODE_PERIPHERAL;
65 break;
66 case DWC3_GHWPARAMS0_MODE_HOST:
67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
68 dev_err(dev,
69 "Controller does not support device mode.\n");
70 return -EINVAL;
71 }
72 mode = USB_DR_MODE_HOST;
73 break;
74 default:
75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
76 mode = USB_DR_MODE_HOST;
77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
78 mode = USB_DR_MODE_PERIPHERAL;
79 }
80
81 if (mode != dwc->dr_mode) {
82 dev_warn(dev,
83 "Configuration mismatch. dr_mode forced to %s\n",
84 mode == USB_DR_MODE_HOST ? "host" : "gadget");
85
86 dwc->dr_mode = mode;
87 }
88
89 return 0;
90}
91
92void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
93{
94 u32 reg;
95
96 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
97 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
98 reg |= DWC3_GCTL_PRTCAPDIR(mode);
99 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
100
101 dwc->current_dr_role = mode;
102}
103
104static void __dwc3_set_mode(struct work_struct *work)
105{
106 struct dwc3 *dwc = work_to_dwc(work);
107 unsigned long flags;
108 int ret;
109
110 if (dwc->dr_mode != USB_DR_MODE_OTG)
111 return;
112
113 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
114 dwc3_otg_update(dwc, 0);
115
116 if (!dwc->desired_dr_role)
117 return;
118
119 if (dwc->desired_dr_role == dwc->current_dr_role)
120 return;
121
122 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
123 return;
124
125 switch (dwc->current_dr_role) {
126 case DWC3_GCTL_PRTCAP_HOST:
127 dwc3_host_exit(dwc);
128 break;
129 case DWC3_GCTL_PRTCAP_DEVICE:
130 dwc3_gadget_exit(dwc);
131 dwc3_event_buffers_cleanup(dwc);
132 break;
133 case DWC3_GCTL_PRTCAP_OTG:
134 dwc3_otg_exit(dwc);
135 spin_lock_irqsave(&dwc->lock, flags);
136 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
137 spin_unlock_irqrestore(&dwc->lock, flags);
138 dwc3_otg_update(dwc, 1);
139 break;
140 default:
141 break;
142 }
143
144 spin_lock_irqsave(&dwc->lock, flags);
145
146 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
147
148 spin_unlock_irqrestore(&dwc->lock, flags);
149
150 switch (dwc->desired_dr_role) {
151 case DWC3_GCTL_PRTCAP_HOST:
152 ret = dwc3_host_init(dwc);
153 if (ret) {
154 dev_err(dwc->dev, "failed to initialize host\n");
155 } else {
156 if (dwc->usb2_phy)
157 otg_set_vbus(dwc->usb2_phy->otg, true);
158 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
159 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
160 phy_calibrate(dwc->usb2_generic_phy);
161 }
162 break;
163 case DWC3_GCTL_PRTCAP_DEVICE:
164 dwc3_event_buffers_setup(dwc);
165
166 if (dwc->usb2_phy)
167 otg_set_vbus(dwc->usb2_phy->otg, false);
168 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
169 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
170
171 ret = dwc3_gadget_init(dwc);
172 if (ret)
173 dev_err(dwc->dev, "failed to initialize peripheral\n");
174 break;
175 case DWC3_GCTL_PRTCAP_OTG:
176 dwc3_otg_init(dwc);
177 dwc3_otg_update(dwc, 0);
178 break;
179 default:
180 break;
181 }
182
183}
184
185void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
186{
187 unsigned long flags;
188
189 spin_lock_irqsave(&dwc->lock, flags);
190 dwc->desired_dr_role = mode;
191 spin_unlock_irqrestore(&dwc->lock, flags);
192
193 queue_work(system_freezable_wq, &dwc->drd_work);
194}
195
196u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
197{
198 struct dwc3 *dwc = dep->dwc;
199 u32 reg;
200
201 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
202 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
203 DWC3_GDBGFIFOSPACE_TYPE(type));
204
205 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
206
207 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
208}
209
210/**
211 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
212 * @dwc: pointer to our context structure
213 */
214static int dwc3_core_soft_reset(struct dwc3 *dwc)
215{
216 u32 reg;
217 int retries = 1000;
218 int ret;
219
220 usb_phy_init(dwc->usb2_phy);
221 usb_phy_init(dwc->usb3_phy);
222 ret = phy_init(dwc->usb2_generic_phy);
223 if (ret < 0)
224 return ret;
225
226 ret = phy_init(dwc->usb3_generic_phy);
227 if (ret < 0) {
228 phy_exit(dwc->usb2_generic_phy);
229 return ret;
230 }
231
232 /*
233 * We're resetting only the device side because, if we're in host mode,
234 * XHCI driver will reset the host block. If dwc3 was configured for
235 * host-only mode, then we can return early.
236 */
237 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
238 return 0;
239
240 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
241 reg |= DWC3_DCTL_CSFTRST;
242 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
243
244 do {
245 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
246 if (!(reg & DWC3_DCTL_CSFTRST))
247 goto done;
248
249 udelay(1);
250 } while (--retries);
251
252 phy_exit(dwc->usb3_generic_phy);
253 phy_exit(dwc->usb2_generic_phy);
254
255 return -ETIMEDOUT;
256
257done:
258 /*
259 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
260 * we must wait at least 50ms before accessing the PHY domain
261 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
262 */
263 if (dwc3_is_usb31(dwc))
264 msleep(50);
265
266 return 0;
267}
268
269/*
270 * dwc3_frame_length_adjustment - Adjusts frame length if required
271 * @dwc3: Pointer to our controller context structure
272 */
273static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
274{
275 u32 reg;
276 u32 dft;
277
278 if (dwc->revision < DWC3_REVISION_250A)
279 return;
280
281 if (dwc->fladj == 0)
282 return;
283
284 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
285 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
286 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
287 "request value same as default, ignoring\n")) {
288 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
289 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
290 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
291 }
292}
293
294/**
295 * dwc3_free_one_event_buffer - Frees one event buffer
296 * @dwc: Pointer to our controller context structure
297 * @evt: Pointer to event buffer to be freed
298 */
299static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
300 struct dwc3_event_buffer *evt)
301{
302 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
303}
304
305/**
306 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
307 * @dwc: Pointer to our controller context structure
308 * @length: size of the event buffer
309 *
310 * Returns a pointer to the allocated event buffer structure on success
311 * otherwise ERR_PTR(errno).
312 */
313static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
314 unsigned length)
315{
316 struct dwc3_event_buffer *evt;
317
318 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
319 if (!evt)
320 return ERR_PTR(-ENOMEM);
321
322 evt->dwc = dwc;
323 evt->length = length;
324 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
325 if (!evt->cache)
326 return ERR_PTR(-ENOMEM);
327
328 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
329 &evt->dma, GFP_KERNEL);
330 if (!evt->buf)
331 return ERR_PTR(-ENOMEM);
332
333 return evt;
334}
335
336/**
337 * dwc3_free_event_buffers - frees all allocated event buffers
338 * @dwc: Pointer to our controller context structure
339 */
340static void dwc3_free_event_buffers(struct dwc3 *dwc)
341{
342 struct dwc3_event_buffer *evt;
343
344 evt = dwc->ev_buf;
345 if (evt)
346 dwc3_free_one_event_buffer(dwc, evt);
347}
348
349/**
350 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
351 * @dwc: pointer to our controller context structure
352 * @length: size of event buffer
353 *
354 * Returns 0 on success otherwise negative errno. In the error case, dwc
355 * may contain some buffers allocated but not all which were requested.
356 */
357static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
358{
359 struct dwc3_event_buffer *evt;
360
361 evt = dwc3_alloc_one_event_buffer(dwc, length);
362 if (IS_ERR(evt)) {
363 dev_err(dwc->dev, "can't allocate event buffer\n");
364 return PTR_ERR(evt);
365 }
366 dwc->ev_buf = evt;
367
368 return 0;
369}
370
371/**
372 * dwc3_event_buffers_setup - setup our allocated event buffers
373 * @dwc: pointer to our controller context structure
374 *
375 * Returns 0 on success otherwise negative errno.
376 */
377int dwc3_event_buffers_setup(struct dwc3 *dwc)
378{
379 struct dwc3_event_buffer *evt;
380
381 evt = dwc->ev_buf;
382 evt->lpos = 0;
383 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
384 lower_32_bits(evt->dma));
385 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
386 upper_32_bits(evt->dma));
387 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
388 DWC3_GEVNTSIZ_SIZE(evt->length));
389 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
390
391 return 0;
392}
393
394void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
395{
396 struct dwc3_event_buffer *evt;
397
398 evt = dwc->ev_buf;
399
400 evt->lpos = 0;
401
402 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
403 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
404 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
405 | DWC3_GEVNTSIZ_SIZE(0));
406 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
407}
408
409static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
410{
411 if (!dwc->has_hibernation)
412 return 0;
413
414 if (!dwc->nr_scratch)
415 return 0;
416
417 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
418 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
419 if (!dwc->scratchbuf)
420 return -ENOMEM;
421
422 return 0;
423}
424
425static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
426{
427 dma_addr_t scratch_addr;
428 u32 param;
429 int ret;
430
431 if (!dwc->has_hibernation)
432 return 0;
433
434 if (!dwc->nr_scratch)
435 return 0;
436
437 /* should never fall here */
438 if (!WARN_ON(dwc->scratchbuf))
439 return 0;
440
441 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
442 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
443 DMA_BIDIRECTIONAL);
444 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
445 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
446 ret = -EFAULT;
447 goto err0;
448 }
449
450 dwc->scratch_addr = scratch_addr;
451
452 param = lower_32_bits(scratch_addr);
453
454 ret = dwc3_send_gadget_generic_command(dwc,
455 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
456 if (ret < 0)
457 goto err1;
458
459 param = upper_32_bits(scratch_addr);
460
461 ret = dwc3_send_gadget_generic_command(dwc,
462 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
463 if (ret < 0)
464 goto err1;
465
466 return 0;
467
468err1:
469 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
470 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
471
472err0:
473 return ret;
474}
475
476static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
477{
478 if (!dwc->has_hibernation)
479 return;
480
481 if (!dwc->nr_scratch)
482 return;
483
484 /* should never fall here */
485 if (!WARN_ON(dwc->scratchbuf))
486 return;
487
488 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
489 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
490 kfree(dwc->scratchbuf);
491}
492
493static void dwc3_core_num_eps(struct dwc3 *dwc)
494{
495 struct dwc3_hwparams *parms = &dwc->hwparams;
496
497 dwc->num_eps = DWC3_NUM_EPS(parms);
498}
499
500static void dwc3_cache_hwparams(struct dwc3 *dwc)
501{
502 struct dwc3_hwparams *parms = &dwc->hwparams;
503
504 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
505 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
506 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
507 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
508 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
509 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
510 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
511 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
512 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
513}
514
515static int dwc3_core_ulpi_init(struct dwc3 *dwc)
516{
517 int intf;
518 int ret = 0;
519
520 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
521
522 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
523 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
524 dwc->hsphy_interface &&
525 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
526 ret = dwc3_ulpi_init(dwc);
527
528 return ret;
529}
530
531/**
532 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
533 * @dwc: Pointer to our controller context structure
534 *
535 * Returns 0 on success. The USB PHY interfaces are configured but not
536 * initialized. The PHY interfaces and the PHYs get initialized together with
537 * the core in dwc3_core_init.
538 */
539static int dwc3_phy_setup(struct dwc3 *dwc)
540{
541 u32 reg;
542
543 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
544
545 /*
546 * Make sure UX_EXIT_PX is cleared as that causes issues with some
547 * PHYs. Also, this bit is not supposed to be used in normal operation.
548 */
549 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
550
551 /*
552 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
553 * to '0' during coreConsultant configuration. So default value
554 * will be '0' when the core is reset. Application needs to set it
555 * to '1' after the core initialization is completed.
556 */
557 if (dwc->revision > DWC3_REVISION_194A)
558 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
559
560 if (dwc->u2ss_inp3_quirk)
561 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
562
563 if (dwc->dis_rxdet_inp3_quirk)
564 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
565
566 if (dwc->req_p1p2p3_quirk)
567 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
568
569 if (dwc->del_p1p2p3_quirk)
570 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
571
572 if (dwc->del_phy_power_chg_quirk)
573 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
574
575 if (dwc->lfps_filter_quirk)
576 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
577
578 if (dwc->rx_detect_poll_quirk)
579 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
580
581 if (dwc->tx_de_emphasis_quirk)
582 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
583
584 if (dwc->dis_u3_susphy_quirk)
585 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
586
587 if (dwc->dis_del_phy_power_chg_quirk)
588 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
589
590 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
591
592 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
593
594 /* Select the HS PHY interface */
595 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
596 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
597 if (dwc->hsphy_interface &&
598 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
599 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
600 break;
601 } else if (dwc->hsphy_interface &&
602 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
603 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
604 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
605 } else {
606 /* Relying on default value. */
607 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
608 break;
609 }
610 /* FALLTHROUGH */
611 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
612 /* FALLTHROUGH */
613 default:
614 break;
615 }
616
617 switch (dwc->hsphy_mode) {
618 case USBPHY_INTERFACE_MODE_UTMI:
619 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
620 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
621 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
622 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
623 break;
624 case USBPHY_INTERFACE_MODE_UTMIW:
625 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
626 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
627 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
628 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
629 break;
630 default:
631 break;
632 }
633
634 /*
635 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
636 * '0' during coreConsultant configuration. So default value will
637 * be '0' when the core is reset. Application needs to set it to
638 * '1' after the core initialization is completed.
639 */
640 if (dwc->revision > DWC3_REVISION_194A)
641 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
642
643 if (dwc->dis_u2_susphy_quirk)
644 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
645
646 if (dwc->dis_enblslpm_quirk)
647 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
648
649 if (dwc->dis_u2_freeclk_exists_quirk)
650 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
651
652 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
653
654 return 0;
655}
656
657static void dwc3_core_exit(struct dwc3 *dwc)
658{
659 dwc3_event_buffers_cleanup(dwc);
660
661 usb_phy_shutdown(dwc->usb2_phy);
662 usb_phy_shutdown(dwc->usb3_phy);
663 phy_exit(dwc->usb2_generic_phy);
664 phy_exit(dwc->usb3_generic_phy);
665
666 usb_phy_set_suspend(dwc->usb2_phy, 1);
667 usb_phy_set_suspend(dwc->usb3_phy, 1);
668 phy_power_off(dwc->usb2_generic_phy);
669 phy_power_off(dwc->usb3_generic_phy);
670}
671
672static bool dwc3_core_is_valid(struct dwc3 *dwc)
673{
674 u32 reg;
675
676 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
677
678 /* This should read as U3 followed by revision number */
679 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
680 /* Detected DWC_usb3 IP */
681 dwc->revision = reg;
682 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
683 /* Detected DWC_usb31 IP */
684 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
685 dwc->revision |= DWC3_REVISION_IS_DWC31;
686 } else {
687 return false;
688 }
689
690 return true;
691}
692
693static void dwc3_core_setup_global_control(struct dwc3 *dwc)
694{
695 u32 hwparams4 = dwc->hwparams.hwparams4;
696 u32 reg;
697
698 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
699 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
700
701 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
702 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
703 /**
704 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
705 * issue which would cause xHCI compliance tests to fail.
706 *
707 * Because of that we cannot enable clock gating on such
708 * configurations.
709 *
710 * Refers to:
711 *
712 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
713 * SOF/ITP Mode Used
714 */
715 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
716 dwc->dr_mode == USB_DR_MODE_OTG) &&
717 (dwc->revision >= DWC3_REVISION_210A &&
718 dwc->revision <= DWC3_REVISION_250A))
719 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
720 else
721 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
722 break;
723 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
724 /* enable hibernation here */
725 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
726
727 /*
728 * REVISIT Enabling this bit so that host-mode hibernation
729 * will work. Device-mode hibernation is not yet implemented.
730 */
731 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
732 break;
733 default:
734 /* nothing */
735 break;
736 }
737
738 /* check if current dwc3 is on simulation board */
739 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
740 dev_info(dwc->dev, "Running with FPGA optmizations\n");
741 dwc->is_fpga = true;
742 }
743
744 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
745 "disable_scramble cannot be used on non-FPGA builds\n");
746
747 if (dwc->disable_scramble_quirk && dwc->is_fpga)
748 reg |= DWC3_GCTL_DISSCRAMBLE;
749 else
750 reg &= ~DWC3_GCTL_DISSCRAMBLE;
751
752 if (dwc->u2exit_lfps_quirk)
753 reg |= DWC3_GCTL_U2EXIT_LFPS;
754
755 /*
756 * WORKAROUND: DWC3 revisions <1.90a have a bug
757 * where the device can fail to connect at SuperSpeed
758 * and falls back to high-speed mode which causes
759 * the device to enter a Connect/Disconnect loop
760 */
761 if (dwc->revision < DWC3_REVISION_190A)
762 reg |= DWC3_GCTL_U2RSTECN;
763
764 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
765}
766
767static int dwc3_core_get_phy(struct dwc3 *dwc);
768static int dwc3_core_ulpi_init(struct dwc3 *dwc);
769
770/**
771 * dwc3_core_init - Low-level initialization of DWC3 Core
772 * @dwc: Pointer to our controller context structure
773 *
774 * Returns 0 on success otherwise negative errno.
775 */
776static int dwc3_core_init(struct dwc3 *dwc)
777{
778 u32 reg;
779 int ret;
780
781 if (!dwc3_core_is_valid(dwc)) {
782 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
783 ret = -ENODEV;
784 goto err0;
785 }
786
787 /*
788 * Write Linux Version Code to our GUID register so it's easy to figure
789 * out which kernel version a bug was found.
790 */
791 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
792
793 /* Handle USB2.0-only core configuration */
794 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
795 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
796 if (dwc->maximum_speed == USB_SPEED_SUPER)
797 dwc->maximum_speed = USB_SPEED_HIGH;
798 }
799
800 ret = dwc3_phy_setup(dwc);
801 if (ret)
802 goto err0;
803
804 if (!dwc->ulpi_ready) {
805 ret = dwc3_core_ulpi_init(dwc);
806 if (ret)
807 goto err0;
808 dwc->ulpi_ready = true;
809 }
810
811 if (!dwc->phys_ready) {
812 ret = dwc3_core_get_phy(dwc);
813 if (ret)
814 goto err0a;
815 dwc->phys_ready = true;
816 }
817
818 ret = dwc3_core_soft_reset(dwc);
819 if (ret)
820 goto err0a;
821
822 dwc3_core_setup_global_control(dwc);
823 dwc3_core_num_eps(dwc);
824
825 ret = dwc3_setup_scratch_buffers(dwc);
826 if (ret)
827 goto err1;
828
829 /* Adjust Frame Length */
830 dwc3_frame_length_adjustment(dwc);
831
832 usb_phy_set_suspend(dwc->usb2_phy, 0);
833 usb_phy_set_suspend(dwc->usb3_phy, 0);
834 ret = phy_power_on(dwc->usb2_generic_phy);
835 if (ret < 0)
836 goto err2;
837
838 ret = phy_power_on(dwc->usb3_generic_phy);
839 if (ret < 0)
840 goto err3;
841
842 ret = dwc3_event_buffers_setup(dwc);
843 if (ret) {
844 dev_err(dwc->dev, "failed to setup event buffers\n");
845 goto err4;
846 }
847
848 /*
849 * ENDXFER polling is available on version 3.10a and later of
850 * the DWC_usb3 controller. It is NOT available in the
851 * DWC_usb31 controller.
852 */
853 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
854 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
855 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
856 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
857 }
858
859 if (dwc->revision >= DWC3_REVISION_250A) {
860 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
861
862 /*
863 * Enable hardware control of sending remote wakeup
864 * in HS when the device is in the L1 state.
865 */
866 if (dwc->revision >= DWC3_REVISION_290A)
867 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
868
869 if (dwc->dis_tx_ipgap_linecheck_quirk)
870 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
871
872 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
873 }
874
875 /*
876 * Must config both number of packets and max burst settings to enable
877 * RX and/or TX threshold.
878 */
879 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
880 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
881 u8 rx_maxburst = dwc->rx_max_burst_prd;
882 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
883 u8 tx_maxburst = dwc->tx_max_burst_prd;
884
885 if (rx_thr_num && rx_maxburst) {
886 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
887 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
888
889 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
890 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
891
892 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
893 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
894
895 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
896 }
897
898 if (tx_thr_num && tx_maxburst) {
899 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
900 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
901
902 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
903 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
904
905 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
906 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
907
908 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
909 }
910 }
911
912 return 0;
913
914err4:
915 phy_power_off(dwc->usb3_generic_phy);
916
917err3:
918 phy_power_off(dwc->usb2_generic_phy);
919
920err2:
921 usb_phy_set_suspend(dwc->usb2_phy, 1);
922 usb_phy_set_suspend(dwc->usb3_phy, 1);
923
924err1:
925 usb_phy_shutdown(dwc->usb2_phy);
926 usb_phy_shutdown(dwc->usb3_phy);
927 phy_exit(dwc->usb2_generic_phy);
928 phy_exit(dwc->usb3_generic_phy);
929
930err0a:
931 dwc3_ulpi_exit(dwc);
932
933err0:
934 return ret;
935}
936
937static int dwc3_core_get_phy(struct dwc3 *dwc)
938{
939 struct device *dev = dwc->dev;
940 struct device_node *node = dev->of_node;
941 int ret;
942
943 if (node) {
944 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
945 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
946 } else {
947 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
948 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
949 }
950
951 if (IS_ERR(dwc->usb2_phy)) {
952 ret = PTR_ERR(dwc->usb2_phy);
953 if (ret == -ENXIO || ret == -ENODEV) {
954 dwc->usb2_phy = NULL;
955 } else if (ret == -EPROBE_DEFER) {
956 return ret;
957 } else {
958 dev_err(dev, "no usb2 phy configured\n");
959 return ret;
960 }
961 }
962
963 if (IS_ERR(dwc->usb3_phy)) {
964 ret = PTR_ERR(dwc->usb3_phy);
965 if (ret == -ENXIO || ret == -ENODEV) {
966 dwc->usb3_phy = NULL;
967 } else if (ret == -EPROBE_DEFER) {
968 return ret;
969 } else {
970 dev_err(dev, "no usb3 phy configured\n");
971 return ret;
972 }
973 }
974
975 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
976 if (IS_ERR(dwc->usb2_generic_phy)) {
977 ret = PTR_ERR(dwc->usb2_generic_phy);
978 if (ret == -ENOSYS || ret == -ENODEV) {
979 dwc->usb2_generic_phy = NULL;
980 } else if (ret == -EPROBE_DEFER) {
981 return ret;
982 } else {
983 dev_err(dev, "no usb2 phy configured\n");
984 return ret;
985 }
986 }
987
988 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
989 if (IS_ERR(dwc->usb3_generic_phy)) {
990 ret = PTR_ERR(dwc->usb3_generic_phy);
991 if (ret == -ENOSYS || ret == -ENODEV) {
992 dwc->usb3_generic_phy = NULL;
993 } else if (ret == -EPROBE_DEFER) {
994 return ret;
995 } else {
996 dev_err(dev, "no usb3 phy configured\n");
997 return ret;
998 }
999 }
1000
1001 return 0;
1002}
1003
1004static int dwc3_core_init_mode(struct dwc3 *dwc)
1005{
1006 struct device *dev = dwc->dev;
1007 int ret;
1008
1009 switch (dwc->dr_mode) {
1010 case USB_DR_MODE_PERIPHERAL:
1011 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1012
1013 if (dwc->usb2_phy)
1014 otg_set_vbus(dwc->usb2_phy->otg, false);
1015 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1016 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1017
1018 ret = dwc3_gadget_init(dwc);
1019 if (ret) {
1020 if (ret != -EPROBE_DEFER)
1021 dev_err(dev, "failed to initialize gadget\n");
1022 return ret;
1023 }
1024 break;
1025 case USB_DR_MODE_HOST:
1026 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1027
1028 if (dwc->usb2_phy)
1029 otg_set_vbus(dwc->usb2_phy->otg, true);
1030 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1031 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1032
1033 ret = dwc3_host_init(dwc);
1034 if (ret) {
1035 if (ret != -EPROBE_DEFER)
1036 dev_err(dev, "failed to initialize host\n");
1037 return ret;
1038 }
1039 phy_calibrate(dwc->usb2_generic_phy);
1040 break;
1041 case USB_DR_MODE_OTG:
1042 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1043 ret = dwc3_drd_init(dwc);
1044 if (ret) {
1045 if (ret != -EPROBE_DEFER)
1046 dev_err(dev, "failed to initialize dual-role\n");
1047 return ret;
1048 }
1049 break;
1050 default:
1051 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1052 return -EINVAL;
1053 }
1054
1055 return 0;
1056}
1057
1058static void dwc3_core_exit_mode(struct dwc3 *dwc)
1059{
1060 switch (dwc->dr_mode) {
1061 case USB_DR_MODE_PERIPHERAL:
1062 dwc3_gadget_exit(dwc);
1063 break;
1064 case USB_DR_MODE_HOST:
1065 dwc3_host_exit(dwc);
1066 break;
1067 case USB_DR_MODE_OTG:
1068 dwc3_drd_exit(dwc);
1069 break;
1070 default:
1071 /* do nothing */
1072 break;
1073 }
1074}
1075
1076static void dwc3_get_properties(struct dwc3 *dwc)
1077{
1078 struct device *dev = dwc->dev;
1079 u8 lpm_nyet_threshold;
1080 u8 tx_de_emphasis;
1081 u8 hird_threshold;
1082 u8 rx_thr_num_pkt_prd;
1083 u8 rx_max_burst_prd;
1084 u8 tx_thr_num_pkt_prd;
1085 u8 tx_max_burst_prd;
1086
1087 /* default to highest possible threshold */
1088 lpm_nyet_threshold = 0xff;
1089
1090 /* default to -3.5dB de-emphasis */
1091 tx_de_emphasis = 1;
1092
1093 /*
1094 * default to assert utmi_sleep_n and use maximum allowed HIRD
1095 * threshold value of 0b1100
1096 */
1097 hird_threshold = 12;
1098
1099 dwc->maximum_speed = usb_get_maximum_speed(dev);
1100 dwc->dr_mode = usb_get_dr_mode(dev);
1101 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1102
1103 dwc->sysdev_is_parent = device_property_read_bool(dev,
1104 "linux,sysdev_is_parent");
1105 if (dwc->sysdev_is_parent)
1106 dwc->sysdev = dwc->dev->parent;
1107 else
1108 dwc->sysdev = dwc->dev;
1109
1110 dwc->has_lpm_erratum = device_property_read_bool(dev,
1111 "snps,has-lpm-erratum");
1112 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1113 &lpm_nyet_threshold);
1114 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1115 "snps,is-utmi-l1-suspend");
1116 device_property_read_u8(dev, "snps,hird-threshold",
1117 &hird_threshold);
1118 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1119 "snps,usb3_lpm_capable");
1120 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1121 &rx_thr_num_pkt_prd);
1122 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1123 &rx_max_burst_prd);
1124 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1125 &tx_thr_num_pkt_prd);
1126 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1127 &tx_max_burst_prd);
1128
1129 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1130 "snps,disable_scramble_quirk");
1131 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1132 "snps,u2exit_lfps_quirk");
1133 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1134 "snps,u2ss_inp3_quirk");
1135 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1136 "snps,req_p1p2p3_quirk");
1137 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1138 "snps,del_p1p2p3_quirk");
1139 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1140 "snps,del_phy_power_chg_quirk");
1141 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1142 "snps,lfps_filter_quirk");
1143 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1144 "snps,rx_detect_poll_quirk");
1145 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1146 "snps,dis_u3_susphy_quirk");
1147 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1148 "snps,dis_u2_susphy_quirk");
1149 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1150 "snps,dis_enblslpm_quirk");
1151 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1152 "snps,dis_rxdet_inp3_quirk");
1153 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1154 "snps,dis-u2-freeclk-exists-quirk");
1155 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1156 "snps,dis-del-phy-power-chg-quirk");
1157 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1158 "snps,dis-tx-ipgap-linecheck-quirk");
1159
1160 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1161 "snps,tx_de_emphasis_quirk");
1162 device_property_read_u8(dev, "snps,tx_de_emphasis",
1163 &tx_de_emphasis);
1164 device_property_read_string(dev, "snps,hsphy_interface",
1165 &dwc->hsphy_interface);
1166 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1167 &dwc->fladj);
1168
1169 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1170 "snps,dis_metastability_quirk");
1171
1172 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1173 dwc->tx_de_emphasis = tx_de_emphasis;
1174
1175 dwc->hird_threshold = hird_threshold
1176 | (dwc->is_utmi_l1_suspend << 4);
1177
1178 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1179 dwc->rx_max_burst_prd = rx_max_burst_prd;
1180
1181 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1182 dwc->tx_max_burst_prd = tx_max_burst_prd;
1183
1184 dwc->imod_interval = 0;
1185}
1186
1187/* check whether the core supports IMOD */
1188bool dwc3_has_imod(struct dwc3 *dwc)
1189{
1190 return ((dwc3_is_usb3(dwc) &&
1191 dwc->revision >= DWC3_REVISION_300A) ||
1192 (dwc3_is_usb31(dwc) &&
1193 dwc->revision >= DWC3_USB31_REVISION_120A));
1194}
1195
1196static void dwc3_check_params(struct dwc3 *dwc)
1197{
1198 struct device *dev = dwc->dev;
1199
1200 /* Check for proper value of imod_interval */
1201 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1202 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1203 dwc->imod_interval = 0;
1204 }
1205
1206 /*
1207 * Workaround for STAR 9000961433 which affects only version
1208 * 3.00a of the DWC_usb3 core. This prevents the controller
1209 * interrupt from being masked while handling events. IMOD
1210 * allows us to work around this issue. Enable it for the
1211 * affected version.
1212 */
1213 if (!dwc->imod_interval &&
1214 (dwc->revision == DWC3_REVISION_300A))
1215 dwc->imod_interval = 1;
1216
1217 /* Check the maximum_speed parameter */
1218 switch (dwc->maximum_speed) {
1219 case USB_SPEED_LOW:
1220 case USB_SPEED_FULL:
1221 case USB_SPEED_HIGH:
1222 case USB_SPEED_SUPER:
1223 case USB_SPEED_SUPER_PLUS:
1224 break;
1225 default:
1226 dev_err(dev, "invalid maximum_speed parameter %d\n",
1227 dwc->maximum_speed);
1228 /* fall through */
1229 case USB_SPEED_UNKNOWN:
1230 /* default to superspeed */
1231 dwc->maximum_speed = USB_SPEED_SUPER;
1232
1233 /*
1234 * default to superspeed plus if we are capable.
1235 */
1236 if (dwc3_is_usb31(dwc) &&
1237 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1238 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1239 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1240
1241 break;
1242 }
1243}
1244
1245static int dwc3_probe(struct platform_device *pdev)
1246{
1247 struct device *dev = &pdev->dev;
1248 struct resource *res;
1249 struct dwc3 *dwc;
1250
1251 int ret;
1252
1253 void __iomem *regs;
1254
1255 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1256 if (!dwc)
1257 return -ENOMEM;
1258
1259 dwc->dev = dev;
1260
1261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262 if (!res) {
1263 dev_err(dev, "missing memory resource\n");
1264 return -ENODEV;
1265 }
1266
1267 dwc->xhci_resources[0].start = res->start;
1268 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1269 DWC3_XHCI_REGS_END;
1270 dwc->xhci_resources[0].flags = res->flags;
1271 dwc->xhci_resources[0].name = res->name;
1272
1273 res->start += DWC3_GLOBALS_REGS_START;
1274
1275 /*
1276 * Request memory region but exclude xHCI regs,
1277 * since it will be requested by the xhci-plat driver.
1278 */
1279 regs = devm_ioremap_resource(dev, res);
1280 if (IS_ERR(regs)) {
1281 ret = PTR_ERR(regs);
1282 goto err0;
1283 }
1284
1285 dwc->regs = regs;
1286 dwc->regs_size = resource_size(res);
1287
1288 dwc3_get_properties(dwc);
1289
1290 platform_set_drvdata(pdev, dwc);
1291 dwc3_cache_hwparams(dwc);
1292
1293 spin_lock_init(&dwc->lock);
1294
1295 pm_runtime_set_active(dev);
1296 pm_runtime_use_autosuspend(dev);
1297 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1298 pm_runtime_enable(dev);
1299 ret = pm_runtime_get_sync(dev);
1300 if (ret < 0)
1301 goto err1;
1302
1303 pm_runtime_forbid(dev);
1304
1305 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1306 if (ret) {
1307 dev_err(dwc->dev, "failed to allocate event buffers\n");
1308 ret = -ENOMEM;
1309 goto err2;
1310 }
1311
1312 ret = dwc3_get_dr_mode(dwc);
1313 if (ret)
1314 goto err3;
1315
1316 ret = dwc3_alloc_scratch_buffers(dwc);
1317 if (ret)
1318 goto err3;
1319
1320 ret = dwc3_core_init(dwc);
1321 if (ret) {
1322 dev_err(dev, "failed to initialize core\n");
1323 goto err4;
1324 }
1325
1326 dwc3_check_params(dwc);
1327
1328 ret = dwc3_core_init_mode(dwc);
1329 if (ret)
1330 goto err5;
1331
1332 dwc3_debugfs_init(dwc);
1333 pm_runtime_put(dev);
1334
1335 return 0;
1336
1337err5:
1338 dwc3_event_buffers_cleanup(dwc);
1339
1340err4:
1341 dwc3_free_scratch_buffers(dwc);
1342
1343err3:
1344 dwc3_free_event_buffers(dwc);
1345
1346err2:
1347 pm_runtime_allow(&pdev->dev);
1348
1349err1:
1350 pm_runtime_put_sync(&pdev->dev);
1351 pm_runtime_disable(&pdev->dev);
1352
1353err0:
1354 /*
1355 * restore res->start back to its original value so that, in case the
1356 * probe is deferred, we don't end up getting error in request the
1357 * memory region the next time probe is called.
1358 */
1359 res->start -= DWC3_GLOBALS_REGS_START;
1360
1361 return ret;
1362}
1363
1364static int dwc3_remove(struct platform_device *pdev)
1365{
1366 struct dwc3 *dwc = platform_get_drvdata(pdev);
1367 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1368
1369 pm_runtime_get_sync(&pdev->dev);
1370 /*
1371 * restore res->start back to its original value so that, in case the
1372 * probe is deferred, we don't end up getting error in request the
1373 * memory region the next time probe is called.
1374 */
1375 res->start -= DWC3_GLOBALS_REGS_START;
1376
1377 dwc3_debugfs_exit(dwc);
1378 dwc3_core_exit_mode(dwc);
1379
1380 dwc3_core_exit(dwc);
1381 dwc3_ulpi_exit(dwc);
1382
1383 pm_runtime_put_sync(&pdev->dev);
1384 pm_runtime_allow(&pdev->dev);
1385 pm_runtime_disable(&pdev->dev);
1386
1387 dwc3_free_event_buffers(dwc);
1388 dwc3_free_scratch_buffers(dwc);
1389
1390 return 0;
1391}
1392
1393#ifdef CONFIG_PM
1394static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1395{
1396 unsigned long flags;
1397
1398 switch (dwc->current_dr_role) {
1399 case DWC3_GCTL_PRTCAP_DEVICE:
1400 spin_lock_irqsave(&dwc->lock, flags);
1401 dwc3_gadget_suspend(dwc);
1402 spin_unlock_irqrestore(&dwc->lock, flags);
1403 dwc3_core_exit(dwc);
1404 break;
1405 case DWC3_GCTL_PRTCAP_HOST:
1406 /* do nothing during host runtime_suspend */
1407 if (!PMSG_IS_AUTO(msg))
1408 dwc3_core_exit(dwc);
1409 break;
1410 case DWC3_GCTL_PRTCAP_OTG:
1411 /* do nothing during runtime_suspend */
1412 if (PMSG_IS_AUTO(msg))
1413 break;
1414
1415 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1416 spin_lock_irqsave(&dwc->lock, flags);
1417 dwc3_gadget_suspend(dwc);
1418 spin_unlock_irqrestore(&dwc->lock, flags);
1419 }
1420
1421 dwc3_otg_exit(dwc);
1422 dwc3_core_exit(dwc);
1423 break;
1424 default:
1425 /* do nothing */
1426 break;
1427 }
1428
1429 return 0;
1430}
1431
1432static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1433{
1434 unsigned long flags;
1435 int ret;
1436
1437 switch (dwc->current_dr_role) {
1438 case DWC3_GCTL_PRTCAP_DEVICE:
1439 ret = dwc3_core_init(dwc);
1440 if (ret)
1441 return ret;
1442
1443 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1444 spin_lock_irqsave(&dwc->lock, flags);
1445 dwc3_gadget_resume(dwc);
1446 spin_unlock_irqrestore(&dwc->lock, flags);
1447 break;
1448 case DWC3_GCTL_PRTCAP_HOST:
1449 /* nothing to do on host runtime_resume */
1450 if (!PMSG_IS_AUTO(msg)) {
1451 ret = dwc3_core_init(dwc);
1452 if (ret)
1453 return ret;
1454 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1455 }
1456 break;
1457 case DWC3_GCTL_PRTCAP_OTG:
1458 /* nothing to do on runtime_resume */
1459 if (PMSG_IS_AUTO(msg))
1460 break;
1461
1462 ret = dwc3_core_init(dwc);
1463 if (ret)
1464 return ret;
1465
1466 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1467
1468 dwc3_otg_init(dwc);
1469 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1470 dwc3_otg_host_init(dwc);
1471 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1472 spin_lock_irqsave(&dwc->lock, flags);
1473 dwc3_gadget_resume(dwc);
1474 spin_unlock_irqrestore(&dwc->lock, flags);
1475 }
1476
1477 break;
1478 default:
1479 /* do nothing */
1480 break;
1481 }
1482
1483 return 0;
1484}
1485
1486static int dwc3_runtime_checks(struct dwc3 *dwc)
1487{
1488 switch (dwc->current_dr_role) {
1489 case DWC3_GCTL_PRTCAP_DEVICE:
1490 if (dwc->connected)
1491 return -EBUSY;
1492 break;
1493 case DWC3_GCTL_PRTCAP_HOST:
1494 default:
1495 /* do nothing */
1496 break;
1497 }
1498
1499 return 0;
1500}
1501
1502static int dwc3_runtime_suspend(struct device *dev)
1503{
1504 struct dwc3 *dwc = dev_get_drvdata(dev);
1505 int ret;
1506
1507 if (dwc3_runtime_checks(dwc))
1508 return -EBUSY;
1509
1510 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1511 if (ret)
1512 return ret;
1513
1514 device_init_wakeup(dev, true);
1515
1516 return 0;
1517}
1518
1519static int dwc3_runtime_resume(struct device *dev)
1520{
1521 struct dwc3 *dwc = dev_get_drvdata(dev);
1522 int ret;
1523
1524 device_init_wakeup(dev, false);
1525
1526 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1527 if (ret)
1528 return ret;
1529
1530 switch (dwc->current_dr_role) {
1531 case DWC3_GCTL_PRTCAP_DEVICE:
1532 dwc3_gadget_process_pending_events(dwc);
1533 break;
1534 case DWC3_GCTL_PRTCAP_HOST:
1535 default:
1536 /* do nothing */
1537 break;
1538 }
1539
1540 pm_runtime_mark_last_busy(dev);
1541
1542 return 0;
1543}
1544
1545static int dwc3_runtime_idle(struct device *dev)
1546{
1547 struct dwc3 *dwc = dev_get_drvdata(dev);
1548
1549 switch (dwc->current_dr_role) {
1550 case DWC3_GCTL_PRTCAP_DEVICE:
1551 if (dwc3_runtime_checks(dwc))
1552 return -EBUSY;
1553 break;
1554 case DWC3_GCTL_PRTCAP_HOST:
1555 default:
1556 /* do nothing */
1557 break;
1558 }
1559
1560 pm_runtime_mark_last_busy(dev);
1561 pm_runtime_autosuspend(dev);
1562
1563 return 0;
1564}
1565#endif /* CONFIG_PM */
1566
1567#ifdef CONFIG_PM_SLEEP
1568static int dwc3_suspend(struct device *dev)
1569{
1570 struct dwc3 *dwc = dev_get_drvdata(dev);
1571 int ret;
1572
1573 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1574 if (ret)
1575 return ret;
1576
1577 pinctrl_pm_select_sleep_state(dev);
1578
1579 return 0;
1580}
1581
1582static int dwc3_resume(struct device *dev)
1583{
1584 struct dwc3 *dwc = dev_get_drvdata(dev);
1585 int ret;
1586
1587 pinctrl_pm_select_default_state(dev);
1588
1589 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1590 if (ret)
1591 return ret;
1592
1593 pm_runtime_disable(dev);
1594 pm_runtime_set_active(dev);
1595 pm_runtime_enable(dev);
1596
1597 return 0;
1598}
1599#endif /* CONFIG_PM_SLEEP */
1600
1601static const struct dev_pm_ops dwc3_dev_pm_ops = {
1602 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1603 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1604 dwc3_runtime_idle)
1605};
1606
1607#ifdef CONFIG_OF
1608static const struct of_device_id of_dwc3_match[] = {
1609 {
1610 .compatible = "snps,dwc3"
1611 },
1612 {
1613 .compatible = "synopsys,dwc3"
1614 },
1615 { },
1616};
1617MODULE_DEVICE_TABLE(of, of_dwc3_match);
1618#endif
1619
1620#ifdef CONFIG_ACPI
1621
1622#define ACPI_ID_INTEL_BSW "808622B7"
1623
1624static const struct acpi_device_id dwc3_acpi_match[] = {
1625 { ACPI_ID_INTEL_BSW, 0 },
1626 { },
1627};
1628MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1629#endif
1630
1631static struct platform_driver dwc3_driver = {
1632 .probe = dwc3_probe,
1633 .remove = dwc3_remove,
1634 .driver = {
1635 .name = "dwc3",
1636 .of_match_table = of_match_ptr(of_dwc3_match),
1637 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1638 .pm = &dwc3_dev_pm_ops,
1639 },
1640};
1641
1642module_platform_driver(dwc3_driver);
1643
1644MODULE_ALIAS("platform:dwc3");
1645MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1646MODULE_LICENSE("GPL v2");
1647MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/of_graph.h>
27#include <linux/acpi.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/reset.h>
30#include <linux/bitfield.h>
31
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
34#include <linux/usb/of.h>
35#include <linux/usb/otg.h>
36
37#include "core.h"
38#include "gadget.h"
39#include "io.h"
40
41#include "debug.h"
42
43#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45/**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
49static int dwc3_get_dr_mode(struct dwc3 *dwc)
50{
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105}
106
107void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
108{
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
112 if (enable && !dwc->dis_u3_susphy_quirk)
113 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
114 else
115 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
116
117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
118
119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
120 if (enable && !dwc->dis_u2_susphy_quirk)
121 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
122 else
123 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
124
125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
126}
127
128void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
129{
130 u32 reg;
131
132 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
133 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
134 reg |= DWC3_GCTL_PRTCAPDIR(mode);
135 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
136
137 dwc->current_dr_role = mode;
138}
139
140static void __dwc3_set_mode(struct work_struct *work)
141{
142 struct dwc3 *dwc = work_to_dwc(work);
143 unsigned long flags;
144 int ret;
145 u32 reg;
146 u32 desired_dr_role;
147
148 mutex_lock(&dwc->mutex);
149 spin_lock_irqsave(&dwc->lock, flags);
150 desired_dr_role = dwc->desired_dr_role;
151 spin_unlock_irqrestore(&dwc->lock, flags);
152
153 pm_runtime_get_sync(dwc->dev);
154
155 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
156 dwc3_otg_update(dwc, 0);
157
158 if (!desired_dr_role)
159 goto out;
160
161 if (desired_dr_role == dwc->current_dr_role)
162 goto out;
163
164 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
165 goto out;
166
167 switch (dwc->current_dr_role) {
168 case DWC3_GCTL_PRTCAP_HOST:
169 dwc3_host_exit(dwc);
170 break;
171 case DWC3_GCTL_PRTCAP_DEVICE:
172 dwc3_gadget_exit(dwc);
173 dwc3_event_buffers_cleanup(dwc);
174 break;
175 case DWC3_GCTL_PRTCAP_OTG:
176 dwc3_otg_exit(dwc);
177 spin_lock_irqsave(&dwc->lock, flags);
178 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
179 spin_unlock_irqrestore(&dwc->lock, flags);
180 dwc3_otg_update(dwc, 1);
181 break;
182 default:
183 break;
184 }
185
186 /*
187 * When current_dr_role is not set, there's no role switching.
188 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
189 */
190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
191 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
192 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
193 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
194 reg |= DWC3_GCTL_CORESOFTRESET;
195 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
196
197 /*
198 * Wait for internal clocks to synchronized. DWC_usb31 and
199 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
200 * keep it consistent across different IPs, let's wait up to
201 * 100ms before clearing GCTL.CORESOFTRESET.
202 */
203 msleep(100);
204
205 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
206 reg &= ~DWC3_GCTL_CORESOFTRESET;
207 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 }
209
210 spin_lock_irqsave(&dwc->lock, flags);
211
212 dwc3_set_prtcap(dwc, desired_dr_role);
213
214 spin_unlock_irqrestore(&dwc->lock, flags);
215
216 switch (desired_dr_role) {
217 case DWC3_GCTL_PRTCAP_HOST:
218 ret = dwc3_host_init(dwc);
219 if (ret) {
220 dev_err(dwc->dev, "failed to initialize host\n");
221 } else {
222 if (dwc->usb2_phy)
223 otg_set_vbus(dwc->usb2_phy->otg, true);
224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
226 if (dwc->dis_split_quirk) {
227 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
228 reg |= DWC3_GUCTL3_SPLITDISABLE;
229 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
230 }
231 }
232 break;
233 case DWC3_GCTL_PRTCAP_DEVICE:
234 dwc3_core_soft_reset(dwc);
235
236 dwc3_event_buffers_setup(dwc);
237
238 if (dwc->usb2_phy)
239 otg_set_vbus(dwc->usb2_phy->otg, false);
240 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
241 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
242
243 ret = dwc3_gadget_init(dwc);
244 if (ret)
245 dev_err(dwc->dev, "failed to initialize peripheral\n");
246 break;
247 case DWC3_GCTL_PRTCAP_OTG:
248 dwc3_otg_init(dwc);
249 dwc3_otg_update(dwc, 0);
250 break;
251 default:
252 break;
253 }
254
255out:
256 pm_runtime_mark_last_busy(dwc->dev);
257 pm_runtime_put_autosuspend(dwc->dev);
258 mutex_unlock(&dwc->mutex);
259}
260
261void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
262{
263 unsigned long flags;
264
265 if (dwc->dr_mode != USB_DR_MODE_OTG)
266 return;
267
268 spin_lock_irqsave(&dwc->lock, flags);
269 dwc->desired_dr_role = mode;
270 spin_unlock_irqrestore(&dwc->lock, flags);
271
272 queue_work(system_freezable_wq, &dwc->drd_work);
273}
274
275u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
276{
277 struct dwc3 *dwc = dep->dwc;
278 u32 reg;
279
280 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
281 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
282 DWC3_GDBGFIFOSPACE_TYPE(type));
283
284 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
285
286 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
287}
288
289/**
290 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
291 * @dwc: pointer to our context structure
292 */
293int dwc3_core_soft_reset(struct dwc3 *dwc)
294{
295 u32 reg;
296 int retries = 1000;
297
298 /*
299 * We're resetting only the device side because, if we're in host mode,
300 * XHCI driver will reset the host block. If dwc3 was configured for
301 * host-only mode, then we can return early.
302 */
303 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
304 return 0;
305
306 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
307 reg |= DWC3_DCTL_CSFTRST;
308 reg &= ~DWC3_DCTL_RUN_STOP;
309 dwc3_gadget_dctl_write_safe(dwc, reg);
310
311 /*
312 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
313 * is cleared only after all the clocks are synchronized. This can
314 * take a little more than 50ms. Set the polling rate at 20ms
315 * for 10 times instead.
316 */
317 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
318 retries = 10;
319
320 do {
321 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
322 if (!(reg & DWC3_DCTL_CSFTRST))
323 goto done;
324
325 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
326 msleep(20);
327 else
328 udelay(1);
329 } while (--retries);
330
331 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
332 return -ETIMEDOUT;
333
334done:
335 /*
336 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
337 * is cleared, we must wait at least 50ms before accessing the PHY
338 * domain (synchronization delay).
339 */
340 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
341 msleep(50);
342
343 return 0;
344}
345
346/*
347 * dwc3_frame_length_adjustment - Adjusts frame length if required
348 * @dwc3: Pointer to our controller context structure
349 */
350static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
351{
352 u32 reg;
353 u32 dft;
354
355 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
356 return;
357
358 if (dwc->fladj == 0)
359 return;
360
361 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
362 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
363 if (dft != dwc->fladj) {
364 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
365 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
366 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
367 }
368}
369
370/**
371 * dwc3_ref_clk_period - Reference clock period configuration
372 * Default reference clock period depends on hardware
373 * configuration. For systems with reference clock that differs
374 * from the default, this will set clock period in DWC3_GUCTL
375 * register.
376 * @dwc: Pointer to our controller context structure
377 */
378static void dwc3_ref_clk_period(struct dwc3 *dwc)
379{
380 unsigned long period;
381 unsigned long fladj;
382 unsigned long decr;
383 unsigned long rate;
384 u32 reg;
385
386 if (dwc->ref_clk) {
387 rate = clk_get_rate(dwc->ref_clk);
388 if (!rate)
389 return;
390 period = NSEC_PER_SEC / rate;
391 } else if (dwc->ref_clk_per) {
392 period = dwc->ref_clk_per;
393 rate = NSEC_PER_SEC / period;
394 } else {
395 return;
396 }
397
398 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
399 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
400 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
401 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
402
403 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
404 return;
405
406 /*
407 * The calculation below is
408 *
409 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
410 *
411 * but rearranged for fixed-point arithmetic. The division must be
412 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
413 * neither does rate * period).
414 *
415 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
416 * nanoseconds of error caused by the truncation which happened during
417 * the division when calculating rate or period (whichever one was
418 * derived from the other). We first calculate the relative error, then
419 * scale it to units of 8 ppm.
420 */
421 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
422 fladj -= 125000;
423
424 /*
425 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
426 */
427 decr = 480000000 / rate;
428
429 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
430 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
431 & ~DWC3_GFLADJ_240MHZDECR
432 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
433 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
434 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
435 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
436
437 if (dwc->gfladj_refclk_lpm_sel)
438 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
439
440 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
441}
442
443/**
444 * dwc3_free_one_event_buffer - Frees one event buffer
445 * @dwc: Pointer to our controller context structure
446 * @evt: Pointer to event buffer to be freed
447 */
448static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
449 struct dwc3_event_buffer *evt)
450{
451 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
452}
453
454/**
455 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
456 * @dwc: Pointer to our controller context structure
457 * @length: size of the event buffer
458 *
459 * Returns a pointer to the allocated event buffer structure on success
460 * otherwise ERR_PTR(errno).
461 */
462static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
463 unsigned int length)
464{
465 struct dwc3_event_buffer *evt;
466
467 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
468 if (!evt)
469 return ERR_PTR(-ENOMEM);
470
471 evt->dwc = dwc;
472 evt->length = length;
473 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
474 if (!evt->cache)
475 return ERR_PTR(-ENOMEM);
476
477 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
478 &evt->dma, GFP_KERNEL);
479 if (!evt->buf)
480 return ERR_PTR(-ENOMEM);
481
482 return evt;
483}
484
485/**
486 * dwc3_free_event_buffers - frees all allocated event buffers
487 * @dwc: Pointer to our controller context structure
488 */
489static void dwc3_free_event_buffers(struct dwc3 *dwc)
490{
491 struct dwc3_event_buffer *evt;
492
493 evt = dwc->ev_buf;
494 if (evt)
495 dwc3_free_one_event_buffer(dwc, evt);
496}
497
498/**
499 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
500 * @dwc: pointer to our controller context structure
501 * @length: size of event buffer
502 *
503 * Returns 0 on success otherwise negative errno. In the error case, dwc
504 * may contain some buffers allocated but not all which were requested.
505 */
506static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
507{
508 struct dwc3_event_buffer *evt;
509
510 evt = dwc3_alloc_one_event_buffer(dwc, length);
511 if (IS_ERR(evt)) {
512 dev_err(dwc->dev, "can't allocate event buffer\n");
513 return PTR_ERR(evt);
514 }
515 dwc->ev_buf = evt;
516
517 return 0;
518}
519
520/**
521 * dwc3_event_buffers_setup - setup our allocated event buffers
522 * @dwc: pointer to our controller context structure
523 *
524 * Returns 0 on success otherwise negative errno.
525 */
526int dwc3_event_buffers_setup(struct dwc3 *dwc)
527{
528 struct dwc3_event_buffer *evt;
529
530 evt = dwc->ev_buf;
531 evt->lpos = 0;
532 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
533 lower_32_bits(evt->dma));
534 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
535 upper_32_bits(evt->dma));
536 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
537 DWC3_GEVNTSIZ_SIZE(evt->length));
538 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
539
540 return 0;
541}
542
543void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
544{
545 struct dwc3_event_buffer *evt;
546
547 evt = dwc->ev_buf;
548
549 evt->lpos = 0;
550
551 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
552 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
553 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
554 | DWC3_GEVNTSIZ_SIZE(0));
555 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
556}
557
558static void dwc3_core_num_eps(struct dwc3 *dwc)
559{
560 struct dwc3_hwparams *parms = &dwc->hwparams;
561
562 dwc->num_eps = DWC3_NUM_EPS(parms);
563}
564
565static void dwc3_cache_hwparams(struct dwc3 *dwc)
566{
567 struct dwc3_hwparams *parms = &dwc->hwparams;
568
569 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
570 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
571 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
572 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
573 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
574 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
575 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
576 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
577 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
578
579 if (DWC3_IP_IS(DWC32))
580 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
581}
582
583static int dwc3_core_ulpi_init(struct dwc3 *dwc)
584{
585 int intf;
586 int ret = 0;
587
588 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
589
590 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
591 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
592 dwc->hsphy_interface &&
593 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
594 ret = dwc3_ulpi_init(dwc);
595
596 return ret;
597}
598
599/**
600 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
601 * @dwc: Pointer to our controller context structure
602 *
603 * Returns 0 on success. The USB PHY interfaces are configured but not
604 * initialized. The PHY interfaces and the PHYs get initialized together with
605 * the core in dwc3_core_init.
606 */
607static int dwc3_phy_setup(struct dwc3 *dwc)
608{
609 u32 reg;
610
611 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
612
613 /*
614 * Make sure UX_EXIT_PX is cleared as that causes issues with some
615 * PHYs. Also, this bit is not supposed to be used in normal operation.
616 */
617 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
618
619 /*
620 * Above DWC_usb3.0 1.94a, it is recommended to set
621 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
622 * So default value will be '0' when the core is reset. Application
623 * needs to set it to '1' after the core initialization is completed.
624 *
625 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
626 * cleared after power-on reset, and it can be set after core
627 * initialization.
628 */
629 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
630
631 if (dwc->u2ss_inp3_quirk)
632 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
633
634 if (dwc->dis_rxdet_inp3_quirk)
635 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
636
637 if (dwc->req_p1p2p3_quirk)
638 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
639
640 if (dwc->del_p1p2p3_quirk)
641 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
642
643 if (dwc->del_phy_power_chg_quirk)
644 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
645
646 if (dwc->lfps_filter_quirk)
647 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
648
649 if (dwc->rx_detect_poll_quirk)
650 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
651
652 if (dwc->tx_de_emphasis_quirk)
653 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
654
655 if (dwc->dis_del_phy_power_chg_quirk)
656 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
657
658 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
659
660 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
661
662 /* Select the HS PHY interface */
663 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
664 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
665 if (dwc->hsphy_interface &&
666 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
667 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
668 break;
669 } else if (dwc->hsphy_interface &&
670 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
671 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
672 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
673 } else {
674 /* Relying on default value. */
675 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
676 break;
677 }
678 fallthrough;
679 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
680 default:
681 break;
682 }
683
684 switch (dwc->hsphy_mode) {
685 case USBPHY_INTERFACE_MODE_UTMI:
686 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
687 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
688 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
689 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
690 break;
691 case USBPHY_INTERFACE_MODE_UTMIW:
692 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
693 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
694 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
695 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
696 break;
697 default:
698 break;
699 }
700
701 /*
702 * Above DWC_usb3.0 1.94a, it is recommended to set
703 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
704 * So default value will be '0' when the core is reset. Application
705 * needs to set it to '1' after the core initialization is completed.
706 *
707 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
708 * after power-on reset, and it can be set after core initialization.
709 */
710 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
711
712 if (dwc->dis_enblslpm_quirk)
713 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
714 else
715 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
716
717 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
718 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
719
720 /*
721 * Some ULPI USB PHY does not support internal VBUS supply, to drive
722 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
723 * bit of OTG_CTRL register. Controller configures the USB2 PHY
724 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
725 * with an external supply.
726 */
727 if (dwc->ulpi_ext_vbus_drv)
728 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
729
730 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
731
732 return 0;
733}
734
735static int dwc3_phy_init(struct dwc3 *dwc)
736{
737 int ret;
738
739 usb_phy_init(dwc->usb2_phy);
740 usb_phy_init(dwc->usb3_phy);
741
742 ret = phy_init(dwc->usb2_generic_phy);
743 if (ret < 0)
744 goto err_shutdown_usb3_phy;
745
746 ret = phy_init(dwc->usb3_generic_phy);
747 if (ret < 0)
748 goto err_exit_usb2_phy;
749
750 return 0;
751
752err_exit_usb2_phy:
753 phy_exit(dwc->usb2_generic_phy);
754err_shutdown_usb3_phy:
755 usb_phy_shutdown(dwc->usb3_phy);
756 usb_phy_shutdown(dwc->usb2_phy);
757
758 return ret;
759}
760
761static void dwc3_phy_exit(struct dwc3 *dwc)
762{
763 phy_exit(dwc->usb3_generic_phy);
764 phy_exit(dwc->usb2_generic_phy);
765
766 usb_phy_shutdown(dwc->usb3_phy);
767 usb_phy_shutdown(dwc->usb2_phy);
768}
769
770static int dwc3_phy_power_on(struct dwc3 *dwc)
771{
772 int ret;
773
774 usb_phy_set_suspend(dwc->usb2_phy, 0);
775 usb_phy_set_suspend(dwc->usb3_phy, 0);
776
777 ret = phy_power_on(dwc->usb2_generic_phy);
778 if (ret < 0)
779 goto err_suspend_usb3_phy;
780
781 ret = phy_power_on(dwc->usb3_generic_phy);
782 if (ret < 0)
783 goto err_power_off_usb2_phy;
784
785 return 0;
786
787err_power_off_usb2_phy:
788 phy_power_off(dwc->usb2_generic_phy);
789err_suspend_usb3_phy:
790 usb_phy_set_suspend(dwc->usb3_phy, 1);
791 usb_phy_set_suspend(dwc->usb2_phy, 1);
792
793 return ret;
794}
795
796static void dwc3_phy_power_off(struct dwc3 *dwc)
797{
798 phy_power_off(dwc->usb3_generic_phy);
799 phy_power_off(dwc->usb2_generic_phy);
800
801 usb_phy_set_suspend(dwc->usb3_phy, 1);
802 usb_phy_set_suspend(dwc->usb2_phy, 1);
803}
804
805static int dwc3_clk_enable(struct dwc3 *dwc)
806{
807 int ret;
808
809 ret = clk_prepare_enable(dwc->bus_clk);
810 if (ret)
811 return ret;
812
813 ret = clk_prepare_enable(dwc->ref_clk);
814 if (ret)
815 goto disable_bus_clk;
816
817 ret = clk_prepare_enable(dwc->susp_clk);
818 if (ret)
819 goto disable_ref_clk;
820
821 ret = clk_prepare_enable(dwc->utmi_clk);
822 if (ret)
823 goto disable_susp_clk;
824
825 ret = clk_prepare_enable(dwc->pipe_clk);
826 if (ret)
827 goto disable_utmi_clk;
828
829 return 0;
830
831disable_utmi_clk:
832 clk_disable_unprepare(dwc->utmi_clk);
833disable_susp_clk:
834 clk_disable_unprepare(dwc->susp_clk);
835disable_ref_clk:
836 clk_disable_unprepare(dwc->ref_clk);
837disable_bus_clk:
838 clk_disable_unprepare(dwc->bus_clk);
839 return ret;
840}
841
842static void dwc3_clk_disable(struct dwc3 *dwc)
843{
844 clk_disable_unprepare(dwc->pipe_clk);
845 clk_disable_unprepare(dwc->utmi_clk);
846 clk_disable_unprepare(dwc->susp_clk);
847 clk_disable_unprepare(dwc->ref_clk);
848 clk_disable_unprepare(dwc->bus_clk);
849}
850
851static void dwc3_core_exit(struct dwc3 *dwc)
852{
853 dwc3_event_buffers_cleanup(dwc);
854 dwc3_phy_power_off(dwc);
855 dwc3_phy_exit(dwc);
856 dwc3_clk_disable(dwc);
857 reset_control_assert(dwc->reset);
858}
859
860static bool dwc3_core_is_valid(struct dwc3 *dwc)
861{
862 u32 reg;
863
864 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
865 dwc->ip = DWC3_GSNPS_ID(reg);
866
867 /* This should read as U3 followed by revision number */
868 if (DWC3_IP_IS(DWC3)) {
869 dwc->revision = reg;
870 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
871 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
872 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
873 } else {
874 return false;
875 }
876
877 return true;
878}
879
880static void dwc3_core_setup_global_control(struct dwc3 *dwc)
881{
882 u32 reg;
883
884 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
885 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
886
887 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
888 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
889 /**
890 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
891 * issue which would cause xHCI compliance tests to fail.
892 *
893 * Because of that we cannot enable clock gating on such
894 * configurations.
895 *
896 * Refers to:
897 *
898 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
899 * SOF/ITP Mode Used
900 */
901 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
902 dwc->dr_mode == USB_DR_MODE_OTG) &&
903 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
904 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
905 else
906 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
907 break;
908 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
909 /*
910 * REVISIT Enabling this bit so that host-mode hibernation
911 * will work. Device-mode hibernation is not yet implemented.
912 */
913 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
914 break;
915 default:
916 /* nothing */
917 break;
918 }
919
920 /* check if current dwc3 is on simulation board */
921 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
922 dev_info(dwc->dev, "Running with FPGA optimizations\n");
923 dwc->is_fpga = true;
924 }
925
926 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
927 "disable_scramble cannot be used on non-FPGA builds\n");
928
929 if (dwc->disable_scramble_quirk && dwc->is_fpga)
930 reg |= DWC3_GCTL_DISSCRAMBLE;
931 else
932 reg &= ~DWC3_GCTL_DISSCRAMBLE;
933
934 if (dwc->u2exit_lfps_quirk)
935 reg |= DWC3_GCTL_U2EXIT_LFPS;
936
937 /*
938 * WORKAROUND: DWC3 revisions <1.90a have a bug
939 * where the device can fail to connect at SuperSpeed
940 * and falls back to high-speed mode which causes
941 * the device to enter a Connect/Disconnect loop
942 */
943 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
944 reg |= DWC3_GCTL_U2RSTECN;
945
946 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
947}
948
949static int dwc3_core_get_phy(struct dwc3 *dwc);
950static int dwc3_core_ulpi_init(struct dwc3 *dwc);
951
952/* set global incr burst type configuration registers */
953static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
954{
955 struct device *dev = dwc->dev;
956 /* incrx_mode : for INCR burst type. */
957 bool incrx_mode;
958 /* incrx_size : for size of INCRX burst. */
959 u32 incrx_size;
960 u32 *vals;
961 u32 cfg;
962 int ntype;
963 int ret;
964 int i;
965
966 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
967
968 /*
969 * Handle property "snps,incr-burst-type-adjustment".
970 * Get the number of value from this property:
971 * result <= 0, means this property is not supported.
972 * result = 1, means INCRx burst mode supported.
973 * result > 1, means undefined length burst mode supported.
974 */
975 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
976 if (ntype <= 0)
977 return;
978
979 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
980 if (!vals)
981 return;
982
983 /* Get INCR burst type, and parse it */
984 ret = device_property_read_u32_array(dev,
985 "snps,incr-burst-type-adjustment", vals, ntype);
986 if (ret) {
987 kfree(vals);
988 dev_err(dev, "Error to get property\n");
989 return;
990 }
991
992 incrx_size = *vals;
993
994 if (ntype > 1) {
995 /* INCRX (undefined length) burst mode */
996 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
997 for (i = 1; i < ntype; i++) {
998 if (vals[i] > incrx_size)
999 incrx_size = vals[i];
1000 }
1001 } else {
1002 /* INCRX burst mode */
1003 incrx_mode = INCRX_BURST_MODE;
1004 }
1005
1006 kfree(vals);
1007
1008 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1009 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1010 if (incrx_mode)
1011 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1012 switch (incrx_size) {
1013 case 256:
1014 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1015 break;
1016 case 128:
1017 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1018 break;
1019 case 64:
1020 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1021 break;
1022 case 32:
1023 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1024 break;
1025 case 16:
1026 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1027 break;
1028 case 8:
1029 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1030 break;
1031 case 4:
1032 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1033 break;
1034 case 1:
1035 break;
1036 default:
1037 dev_err(dev, "Invalid property\n");
1038 break;
1039 }
1040
1041 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1042}
1043
1044static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1045{
1046 u32 scale;
1047 u32 reg;
1048
1049 if (!dwc->susp_clk)
1050 return;
1051
1052 /*
1053 * The power down scale field specifies how many suspend_clk
1054 * periods fit into a 16KHz clock period. When performing
1055 * the division, round up the remainder.
1056 *
1057 * The power down scale value is calculated using the fastest
1058 * frequency of the suspend_clk. If it isn't fixed (but within
1059 * the accuracy requirement), the driver may not know the max
1060 * rate of the suspend_clk, so only update the power down scale
1061 * if the default is less than the calculated value from
1062 * clk_get_rate() or if the default is questionably high
1063 * (3x or more) to be within the requirement.
1064 */
1065 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1066 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1067 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1068 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1069 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1070 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1071 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1072 }
1073}
1074
1075static void dwc3_config_threshold(struct dwc3 *dwc)
1076{
1077 u32 reg;
1078 u8 rx_thr_num;
1079 u8 rx_maxburst;
1080 u8 tx_thr_num;
1081 u8 tx_maxburst;
1082
1083 /*
1084 * Must config both number of packets and max burst settings to enable
1085 * RX and/or TX threshold.
1086 */
1087 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1088 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1089 rx_maxburst = dwc->rx_max_burst_prd;
1090 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1091 tx_maxburst = dwc->tx_max_burst_prd;
1092
1093 if (rx_thr_num && rx_maxburst) {
1094 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1095 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1096
1097 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1098 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1099
1100 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1101 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1102
1103 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1104 }
1105
1106 if (tx_thr_num && tx_maxburst) {
1107 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1108 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1109
1110 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1111 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1112
1113 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1114 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1115
1116 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1117 }
1118 }
1119
1120 rx_thr_num = dwc->rx_thr_num_pkt;
1121 rx_maxburst = dwc->rx_max_burst;
1122 tx_thr_num = dwc->tx_thr_num_pkt;
1123 tx_maxburst = dwc->tx_max_burst;
1124
1125 if (DWC3_IP_IS(DWC3)) {
1126 if (rx_thr_num && rx_maxburst) {
1127 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1128 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1129
1130 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1131 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1132
1133 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1134 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1135
1136 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1137 }
1138
1139 if (tx_thr_num && tx_maxburst) {
1140 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1141 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1142
1143 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1144 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1145
1146 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1147 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1148
1149 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1150 }
1151 } else {
1152 if (rx_thr_num && rx_maxburst) {
1153 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1154 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1155
1156 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1157 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1158
1159 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1160 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1161
1162 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1163 }
1164
1165 if (tx_thr_num && tx_maxburst) {
1166 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1167 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1168
1169 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1170 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1171
1172 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1173 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1174
1175 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1176 }
1177 }
1178}
1179
1180/**
1181 * dwc3_core_init - Low-level initialization of DWC3 Core
1182 * @dwc: Pointer to our controller context structure
1183 *
1184 * Returns 0 on success otherwise negative errno.
1185 */
1186static int dwc3_core_init(struct dwc3 *dwc)
1187{
1188 unsigned int hw_mode;
1189 u32 reg;
1190 int ret;
1191
1192 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1193
1194 /*
1195 * Write Linux Version Code to our GUID register so it's easy to figure
1196 * out which kernel version a bug was found.
1197 */
1198 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1199
1200 ret = dwc3_phy_setup(dwc);
1201 if (ret)
1202 return ret;
1203
1204 if (!dwc->ulpi_ready) {
1205 ret = dwc3_core_ulpi_init(dwc);
1206 if (ret) {
1207 if (ret == -ETIMEDOUT) {
1208 dwc3_core_soft_reset(dwc);
1209 ret = -EPROBE_DEFER;
1210 }
1211 return ret;
1212 }
1213 dwc->ulpi_ready = true;
1214 }
1215
1216 if (!dwc->phys_ready) {
1217 ret = dwc3_core_get_phy(dwc);
1218 if (ret)
1219 goto err_exit_ulpi;
1220 dwc->phys_ready = true;
1221 }
1222
1223 ret = dwc3_phy_init(dwc);
1224 if (ret)
1225 goto err_exit_ulpi;
1226
1227 ret = dwc3_core_soft_reset(dwc);
1228 if (ret)
1229 goto err_exit_phy;
1230
1231 dwc3_core_setup_global_control(dwc);
1232 dwc3_core_num_eps(dwc);
1233
1234 /* Set power down scale of suspend_clk */
1235 dwc3_set_power_down_clk_scale(dwc);
1236
1237 /* Adjust Frame Length */
1238 dwc3_frame_length_adjustment(dwc);
1239
1240 /* Adjust Reference Clock Period */
1241 dwc3_ref_clk_period(dwc);
1242
1243 dwc3_set_incr_burst_type(dwc);
1244
1245 ret = dwc3_phy_power_on(dwc);
1246 if (ret)
1247 goto err_exit_phy;
1248
1249 ret = dwc3_event_buffers_setup(dwc);
1250 if (ret) {
1251 dev_err(dwc->dev, "failed to setup event buffers\n");
1252 goto err_power_off_phy;
1253 }
1254
1255 /*
1256 * ENDXFER polling is available on version 3.10a and later of
1257 * the DWC_usb3 controller. It is NOT available in the
1258 * DWC_usb31 controller.
1259 */
1260 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1261 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1262 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1263 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1264 }
1265
1266 /*
1267 * When configured in HOST mode, after issuing U3/L2 exit controller
1268 * fails to send proper CRC checksum in CRC5 feild. Because of this
1269 * behaviour Transaction Error is generated, resulting in reset and
1270 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1271 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1272 * will correct this problem. This option is to support certain
1273 * legacy ULPI PHYs.
1274 */
1275 if (dwc->resume_hs_terminations) {
1276 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1277 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1278 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1279 }
1280
1281 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1282 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1283
1284 /*
1285 * Enable hardware control of sending remote wakeup
1286 * in HS when the device is in the L1 state.
1287 */
1288 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1289 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1290
1291 /*
1292 * Decouple USB 2.0 L1 & L2 events which will allow for
1293 * gadget driver to only receive U3/L2 suspend & wakeup
1294 * events and prevent the more frequent L1 LPM transitions
1295 * from interrupting the driver.
1296 */
1297 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1298 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1299
1300 if (dwc->dis_tx_ipgap_linecheck_quirk)
1301 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1302
1303 if (dwc->parkmode_disable_ss_quirk)
1304 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1305
1306 if (dwc->parkmode_disable_hs_quirk)
1307 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1308
1309 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1310 (dwc->maximum_speed == USB_SPEED_HIGH ||
1311 dwc->maximum_speed == USB_SPEED_FULL))
1312 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1313
1314 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1315 }
1316
1317 dwc3_config_threshold(dwc);
1318
1319 /*
1320 * Modify this for all supported Super Speed ports when
1321 * multiport support is added.
1322 */
1323 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1324 (DWC3_IP_IS(DWC31)) &&
1325 dwc->maximum_speed == USB_SPEED_SUPER) {
1326 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL);
1327 reg |= DWC3_LLUCTL_FORCE_GEN1;
1328 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg);
1329 }
1330
1331 return 0;
1332
1333err_power_off_phy:
1334 dwc3_phy_power_off(dwc);
1335err_exit_phy:
1336 dwc3_phy_exit(dwc);
1337err_exit_ulpi:
1338 dwc3_ulpi_exit(dwc);
1339
1340 return ret;
1341}
1342
1343static int dwc3_core_get_phy(struct dwc3 *dwc)
1344{
1345 struct device *dev = dwc->dev;
1346 struct device_node *node = dev->of_node;
1347 int ret;
1348
1349 if (node) {
1350 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1351 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1352 } else {
1353 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1354 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1355 }
1356
1357 if (IS_ERR(dwc->usb2_phy)) {
1358 ret = PTR_ERR(dwc->usb2_phy);
1359 if (ret == -ENXIO || ret == -ENODEV)
1360 dwc->usb2_phy = NULL;
1361 else
1362 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1363 }
1364
1365 if (IS_ERR(dwc->usb3_phy)) {
1366 ret = PTR_ERR(dwc->usb3_phy);
1367 if (ret == -ENXIO || ret == -ENODEV)
1368 dwc->usb3_phy = NULL;
1369 else
1370 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1371 }
1372
1373 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1374 if (IS_ERR(dwc->usb2_generic_phy)) {
1375 ret = PTR_ERR(dwc->usb2_generic_phy);
1376 if (ret == -ENOSYS || ret == -ENODEV)
1377 dwc->usb2_generic_phy = NULL;
1378 else
1379 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1380 }
1381
1382 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1383 if (IS_ERR(dwc->usb3_generic_phy)) {
1384 ret = PTR_ERR(dwc->usb3_generic_phy);
1385 if (ret == -ENOSYS || ret == -ENODEV)
1386 dwc->usb3_generic_phy = NULL;
1387 else
1388 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1389 }
1390
1391 return 0;
1392}
1393
1394static int dwc3_core_init_mode(struct dwc3 *dwc)
1395{
1396 struct device *dev = dwc->dev;
1397 int ret;
1398
1399 switch (dwc->dr_mode) {
1400 case USB_DR_MODE_PERIPHERAL:
1401 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1402
1403 if (dwc->usb2_phy)
1404 otg_set_vbus(dwc->usb2_phy->otg, false);
1405 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1406 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1407
1408 ret = dwc3_gadget_init(dwc);
1409 if (ret)
1410 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1411 break;
1412 case USB_DR_MODE_HOST:
1413 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1414
1415 if (dwc->usb2_phy)
1416 otg_set_vbus(dwc->usb2_phy->otg, true);
1417 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1418 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1419
1420 ret = dwc3_host_init(dwc);
1421 if (ret)
1422 return dev_err_probe(dev, ret, "failed to initialize host\n");
1423 break;
1424 case USB_DR_MODE_OTG:
1425 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1426 ret = dwc3_drd_init(dwc);
1427 if (ret)
1428 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1429 break;
1430 default:
1431 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1432 return -EINVAL;
1433 }
1434
1435 return 0;
1436}
1437
1438static void dwc3_core_exit_mode(struct dwc3 *dwc)
1439{
1440 switch (dwc->dr_mode) {
1441 case USB_DR_MODE_PERIPHERAL:
1442 dwc3_gadget_exit(dwc);
1443 break;
1444 case USB_DR_MODE_HOST:
1445 dwc3_host_exit(dwc);
1446 break;
1447 case USB_DR_MODE_OTG:
1448 dwc3_drd_exit(dwc);
1449 break;
1450 default:
1451 /* do nothing */
1452 break;
1453 }
1454
1455 /* de-assert DRVVBUS for HOST and OTG mode */
1456 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1457}
1458
1459static void dwc3_get_properties(struct dwc3 *dwc)
1460{
1461 struct device *dev = dwc->dev;
1462 u8 lpm_nyet_threshold;
1463 u8 tx_de_emphasis;
1464 u8 hird_threshold;
1465 u8 rx_thr_num_pkt = 0;
1466 u8 rx_max_burst = 0;
1467 u8 tx_thr_num_pkt = 0;
1468 u8 tx_max_burst = 0;
1469 u8 rx_thr_num_pkt_prd = 0;
1470 u8 rx_max_burst_prd = 0;
1471 u8 tx_thr_num_pkt_prd = 0;
1472 u8 tx_max_burst_prd = 0;
1473 u8 tx_fifo_resize_max_num;
1474 const char *usb_psy_name;
1475 int ret;
1476
1477 /* default to highest possible threshold */
1478 lpm_nyet_threshold = 0xf;
1479
1480 /* default to -3.5dB de-emphasis */
1481 tx_de_emphasis = 1;
1482
1483 /*
1484 * default to assert utmi_sleep_n and use maximum allowed HIRD
1485 * threshold value of 0b1100
1486 */
1487 hird_threshold = 12;
1488
1489 /*
1490 * default to a TXFIFO size large enough to fit 6 max packets. This
1491 * allows for systems with larger bus latencies to have some headroom
1492 * for endpoints that have a large bMaxBurst value.
1493 */
1494 tx_fifo_resize_max_num = 6;
1495
1496 dwc->maximum_speed = usb_get_maximum_speed(dev);
1497 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1498 dwc->dr_mode = usb_get_dr_mode(dev);
1499 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1500
1501 dwc->sysdev_is_parent = device_property_read_bool(dev,
1502 "linux,sysdev_is_parent");
1503 if (dwc->sysdev_is_parent)
1504 dwc->sysdev = dwc->dev->parent;
1505 else
1506 dwc->sysdev = dwc->dev;
1507
1508 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1509
1510 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1511 if (ret >= 0) {
1512 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1513 if (!dwc->usb_psy)
1514 dev_err(dev, "couldn't get usb power supply\n");
1515 }
1516
1517 dwc->has_lpm_erratum = device_property_read_bool(dev,
1518 "snps,has-lpm-erratum");
1519 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1520 &lpm_nyet_threshold);
1521 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1522 "snps,is-utmi-l1-suspend");
1523 device_property_read_u8(dev, "snps,hird-threshold",
1524 &hird_threshold);
1525 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1526 "snps,dis-start-transfer-quirk");
1527 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1528 "snps,usb3_lpm_capable");
1529 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1530 "snps,usb2-lpm-disable");
1531 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1532 "snps,usb2-gadget-lpm-disable");
1533 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1534 &rx_thr_num_pkt);
1535 device_property_read_u8(dev, "snps,rx-max-burst",
1536 &rx_max_burst);
1537 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1538 &tx_thr_num_pkt);
1539 device_property_read_u8(dev, "snps,tx-max-burst",
1540 &tx_max_burst);
1541 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1542 &rx_thr_num_pkt_prd);
1543 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1544 &rx_max_burst_prd);
1545 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1546 &tx_thr_num_pkt_prd);
1547 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1548 &tx_max_burst_prd);
1549 dwc->do_fifo_resize = device_property_read_bool(dev,
1550 "tx-fifo-resize");
1551 if (dwc->do_fifo_resize)
1552 device_property_read_u8(dev, "tx-fifo-max-num",
1553 &tx_fifo_resize_max_num);
1554
1555 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1556 "snps,disable_scramble_quirk");
1557 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1558 "snps,u2exit_lfps_quirk");
1559 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1560 "snps,u2ss_inp3_quirk");
1561 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1562 "snps,req_p1p2p3_quirk");
1563 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1564 "snps,del_p1p2p3_quirk");
1565 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1566 "snps,del_phy_power_chg_quirk");
1567 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1568 "snps,lfps_filter_quirk");
1569 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1570 "snps,rx_detect_poll_quirk");
1571 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1572 "snps,dis_u3_susphy_quirk");
1573 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1574 "snps,dis_u2_susphy_quirk");
1575 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1576 "snps,dis_enblslpm_quirk");
1577 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1578 "snps,dis-u1-entry-quirk");
1579 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1580 "snps,dis-u2-entry-quirk");
1581 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1582 "snps,dis_rxdet_inp3_quirk");
1583 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1584 "snps,dis-u2-freeclk-exists-quirk");
1585 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1586 "snps,dis-del-phy-power-chg-quirk");
1587 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1588 "snps,dis-tx-ipgap-linecheck-quirk");
1589 dwc->resume_hs_terminations = device_property_read_bool(dev,
1590 "snps,resume-hs-terminations");
1591 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1592 "snps,ulpi-ext-vbus-drv");
1593 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1594 "snps,parkmode-disable-ss-quirk");
1595 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1596 "snps,parkmode-disable-hs-quirk");
1597 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1598 "snps,gfladj-refclk-lpm-sel-quirk");
1599
1600 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1601 "snps,tx_de_emphasis_quirk");
1602 device_property_read_u8(dev, "snps,tx_de_emphasis",
1603 &tx_de_emphasis);
1604 device_property_read_string(dev, "snps,hsphy_interface",
1605 &dwc->hsphy_interface);
1606 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1607 &dwc->fladj);
1608 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1609 &dwc->ref_clk_per);
1610
1611 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1612 "snps,dis_metastability_quirk");
1613
1614 dwc->dis_split_quirk = device_property_read_bool(dev,
1615 "snps,dis-split-quirk");
1616
1617 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1618 dwc->tx_de_emphasis = tx_de_emphasis;
1619
1620 dwc->hird_threshold = hird_threshold;
1621
1622 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1623 dwc->rx_max_burst = rx_max_burst;
1624
1625 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1626 dwc->tx_max_burst = tx_max_burst;
1627
1628 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1629 dwc->rx_max_burst_prd = rx_max_burst_prd;
1630
1631 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1632 dwc->tx_max_burst_prd = tx_max_burst_prd;
1633
1634 dwc->imod_interval = 0;
1635
1636 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1637}
1638
1639/* check whether the core supports IMOD */
1640bool dwc3_has_imod(struct dwc3 *dwc)
1641{
1642 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1643 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1644 DWC3_IP_IS(DWC32);
1645}
1646
1647static void dwc3_check_params(struct dwc3 *dwc)
1648{
1649 struct device *dev = dwc->dev;
1650 unsigned int hwparam_gen =
1651 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1652
1653 /* Check for proper value of imod_interval */
1654 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1655 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1656 dwc->imod_interval = 0;
1657 }
1658
1659 /*
1660 * Workaround for STAR 9000961433 which affects only version
1661 * 3.00a of the DWC_usb3 core. This prevents the controller
1662 * interrupt from being masked while handling events. IMOD
1663 * allows us to work around this issue. Enable it for the
1664 * affected version.
1665 */
1666 if (!dwc->imod_interval &&
1667 DWC3_VER_IS(DWC3, 300A))
1668 dwc->imod_interval = 1;
1669
1670 /* Check the maximum_speed parameter */
1671 switch (dwc->maximum_speed) {
1672 case USB_SPEED_FULL:
1673 case USB_SPEED_HIGH:
1674 break;
1675 case USB_SPEED_SUPER:
1676 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1677 dev_warn(dev, "UDC doesn't support Gen 1\n");
1678 break;
1679 case USB_SPEED_SUPER_PLUS:
1680 if ((DWC3_IP_IS(DWC32) &&
1681 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1682 (!DWC3_IP_IS(DWC32) &&
1683 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1684 dev_warn(dev, "UDC doesn't support SSP\n");
1685 break;
1686 default:
1687 dev_err(dev, "invalid maximum_speed parameter %d\n",
1688 dwc->maximum_speed);
1689 fallthrough;
1690 case USB_SPEED_UNKNOWN:
1691 switch (hwparam_gen) {
1692 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1693 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1694 break;
1695 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1696 if (DWC3_IP_IS(DWC32))
1697 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1698 else
1699 dwc->maximum_speed = USB_SPEED_SUPER;
1700 break;
1701 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1702 dwc->maximum_speed = USB_SPEED_HIGH;
1703 break;
1704 default:
1705 dwc->maximum_speed = USB_SPEED_SUPER;
1706 break;
1707 }
1708 break;
1709 }
1710
1711 /*
1712 * Currently the controller does not have visibility into the HW
1713 * parameter to determine the maximum number of lanes the HW supports.
1714 * If the number of lanes is not specified in the device property, then
1715 * set the default to support dual-lane for DWC_usb32 and single-lane
1716 * for DWC_usb31 for super-speed-plus.
1717 */
1718 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1719 switch (dwc->max_ssp_rate) {
1720 case USB_SSP_GEN_2x1:
1721 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1722 dev_warn(dev, "UDC only supports Gen 1\n");
1723 break;
1724 case USB_SSP_GEN_1x2:
1725 case USB_SSP_GEN_2x2:
1726 if (DWC3_IP_IS(DWC31))
1727 dev_warn(dev, "UDC only supports single lane\n");
1728 break;
1729 case USB_SSP_GEN_UNKNOWN:
1730 default:
1731 switch (hwparam_gen) {
1732 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1733 if (DWC3_IP_IS(DWC32))
1734 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1735 else
1736 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1737 break;
1738 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1739 if (DWC3_IP_IS(DWC32))
1740 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1741 break;
1742 }
1743 break;
1744 }
1745 }
1746}
1747
1748static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1749{
1750 struct device *dev = dwc->dev;
1751 struct device_node *np_phy;
1752 struct extcon_dev *edev = NULL;
1753 const char *name;
1754
1755 if (device_property_read_bool(dev, "extcon"))
1756 return extcon_get_edev_by_phandle(dev, 0);
1757
1758 /*
1759 * Device tree platforms should get extcon via phandle.
1760 * On ACPI platforms, we get the name from a device property.
1761 * This device property is for kernel internal use only and
1762 * is expected to be set by the glue code.
1763 */
1764 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1765 return extcon_get_extcon_dev(name);
1766
1767 /*
1768 * Check explicitly if "usb-role-switch" is used since
1769 * extcon_find_edev_by_node() can not be used to check the absence of
1770 * an extcon device. In the absence of an device it will always return
1771 * EPROBE_DEFER.
1772 */
1773 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1774 device_property_read_bool(dev, "usb-role-switch"))
1775 return NULL;
1776
1777 /*
1778 * Try to get an extcon device from the USB PHY controller's "port"
1779 * node. Check if it has the "port" node first, to avoid printing the
1780 * error message from underlying code, as it's a valid case: extcon
1781 * device (and "port" node) may be missing in case of "usb-role-switch"
1782 * or OTG mode.
1783 */
1784 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1785 if (of_graph_is_present(np_phy)) {
1786 struct device_node *np_conn;
1787
1788 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1789 if (np_conn)
1790 edev = extcon_find_edev_by_node(np_conn);
1791 of_node_put(np_conn);
1792 }
1793 of_node_put(np_phy);
1794
1795 return edev;
1796}
1797
1798static int dwc3_get_clocks(struct dwc3 *dwc)
1799{
1800 struct device *dev = dwc->dev;
1801
1802 if (!dev->of_node)
1803 return 0;
1804
1805 /*
1806 * Clocks are optional, but new DT platforms should support all clocks
1807 * as required by the DT-binding.
1808 * Some devices have different clock names in legacy device trees,
1809 * check for them to retain backwards compatibility.
1810 */
1811 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1812 if (IS_ERR(dwc->bus_clk)) {
1813 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1814 "could not get bus clock\n");
1815 }
1816
1817 if (dwc->bus_clk == NULL) {
1818 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1819 if (IS_ERR(dwc->bus_clk)) {
1820 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1821 "could not get bus clock\n");
1822 }
1823 }
1824
1825 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1826 if (IS_ERR(dwc->ref_clk)) {
1827 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1828 "could not get ref clock\n");
1829 }
1830
1831 if (dwc->ref_clk == NULL) {
1832 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1833 if (IS_ERR(dwc->ref_clk)) {
1834 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1835 "could not get ref clock\n");
1836 }
1837 }
1838
1839 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1840 if (IS_ERR(dwc->susp_clk)) {
1841 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1842 "could not get suspend clock\n");
1843 }
1844
1845 if (dwc->susp_clk == NULL) {
1846 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1847 if (IS_ERR(dwc->susp_clk)) {
1848 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1849 "could not get suspend clock\n");
1850 }
1851 }
1852
1853 /* specific to Rockchip RK3588 */
1854 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
1855 if (IS_ERR(dwc->utmi_clk)) {
1856 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
1857 "could not get utmi clock\n");
1858 }
1859
1860 /* specific to Rockchip RK3588 */
1861 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
1862 if (IS_ERR(dwc->pipe_clk)) {
1863 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
1864 "could not get pipe clock\n");
1865 }
1866
1867 return 0;
1868}
1869
1870static int dwc3_probe(struct platform_device *pdev)
1871{
1872 struct device *dev = &pdev->dev;
1873 struct resource *res, dwc_res;
1874 void __iomem *regs;
1875 struct dwc3 *dwc;
1876 int ret;
1877
1878 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1879 if (!dwc)
1880 return -ENOMEM;
1881
1882 dwc->dev = dev;
1883
1884 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1885 if (!res) {
1886 dev_err(dev, "missing memory resource\n");
1887 return -ENODEV;
1888 }
1889
1890 dwc->xhci_resources[0].start = res->start;
1891 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1892 DWC3_XHCI_REGS_END;
1893 dwc->xhci_resources[0].flags = res->flags;
1894 dwc->xhci_resources[0].name = res->name;
1895
1896 /*
1897 * Request memory region but exclude xHCI regs,
1898 * since it will be requested by the xhci-plat driver.
1899 */
1900 dwc_res = *res;
1901 dwc_res.start += DWC3_GLOBALS_REGS_START;
1902
1903 if (dev->of_node) {
1904 struct device_node *parent = of_get_parent(dev->of_node);
1905
1906 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1907 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1908 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1909 }
1910
1911 of_node_put(parent);
1912 }
1913
1914 regs = devm_ioremap_resource(dev, &dwc_res);
1915 if (IS_ERR(regs))
1916 return PTR_ERR(regs);
1917
1918 dwc->regs = regs;
1919 dwc->regs_size = resource_size(&dwc_res);
1920
1921 dwc3_get_properties(dwc);
1922
1923 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1924 if (IS_ERR(dwc->reset)) {
1925 ret = PTR_ERR(dwc->reset);
1926 goto err_put_psy;
1927 }
1928
1929 ret = dwc3_get_clocks(dwc);
1930 if (ret)
1931 goto err_put_psy;
1932
1933 ret = reset_control_deassert(dwc->reset);
1934 if (ret)
1935 goto err_put_psy;
1936
1937 ret = dwc3_clk_enable(dwc);
1938 if (ret)
1939 goto err_assert_reset;
1940
1941 if (!dwc3_core_is_valid(dwc)) {
1942 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1943 ret = -ENODEV;
1944 goto err_disable_clks;
1945 }
1946
1947 platform_set_drvdata(pdev, dwc);
1948 dwc3_cache_hwparams(dwc);
1949
1950 if (!dwc->sysdev_is_parent &&
1951 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1952 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1953 if (ret)
1954 goto err_disable_clks;
1955 }
1956
1957 spin_lock_init(&dwc->lock);
1958 mutex_init(&dwc->mutex);
1959
1960 pm_runtime_get_noresume(dev);
1961 pm_runtime_set_active(dev);
1962 pm_runtime_use_autosuspend(dev);
1963 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1964 pm_runtime_enable(dev);
1965
1966 pm_runtime_forbid(dev);
1967
1968 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1969 if (ret) {
1970 dev_err(dwc->dev, "failed to allocate event buffers\n");
1971 ret = -ENOMEM;
1972 goto err_allow_rpm;
1973 }
1974
1975 dwc->edev = dwc3_get_extcon(dwc);
1976 if (IS_ERR(dwc->edev)) {
1977 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1978 goto err_free_event_buffers;
1979 }
1980
1981 ret = dwc3_get_dr_mode(dwc);
1982 if (ret)
1983 goto err_free_event_buffers;
1984
1985 ret = dwc3_core_init(dwc);
1986 if (ret) {
1987 dev_err_probe(dev, ret, "failed to initialize core\n");
1988 goto err_free_event_buffers;
1989 }
1990
1991 dwc3_check_params(dwc);
1992 dwc3_debugfs_init(dwc);
1993
1994 ret = dwc3_core_init_mode(dwc);
1995 if (ret)
1996 goto err_exit_debugfs;
1997
1998 pm_runtime_put(dev);
1999
2000 dma_set_max_seg_size(dev, UINT_MAX);
2001
2002 return 0;
2003
2004err_exit_debugfs:
2005 dwc3_debugfs_exit(dwc);
2006 dwc3_event_buffers_cleanup(dwc);
2007 dwc3_phy_power_off(dwc);
2008 dwc3_phy_exit(dwc);
2009 dwc3_ulpi_exit(dwc);
2010err_free_event_buffers:
2011 dwc3_free_event_buffers(dwc);
2012err_allow_rpm:
2013 pm_runtime_allow(dev);
2014 pm_runtime_disable(dev);
2015 pm_runtime_dont_use_autosuspend(dev);
2016 pm_runtime_set_suspended(dev);
2017 pm_runtime_put_noidle(dev);
2018err_disable_clks:
2019 dwc3_clk_disable(dwc);
2020err_assert_reset:
2021 reset_control_assert(dwc->reset);
2022err_put_psy:
2023 if (dwc->usb_psy)
2024 power_supply_put(dwc->usb_psy);
2025
2026 return ret;
2027}
2028
2029static void dwc3_remove(struct platform_device *pdev)
2030{
2031 struct dwc3 *dwc = platform_get_drvdata(pdev);
2032
2033 pm_runtime_get_sync(&pdev->dev);
2034
2035 dwc3_core_exit_mode(dwc);
2036 dwc3_debugfs_exit(dwc);
2037
2038 dwc3_core_exit(dwc);
2039 dwc3_ulpi_exit(dwc);
2040
2041 pm_runtime_allow(&pdev->dev);
2042 pm_runtime_disable(&pdev->dev);
2043 pm_runtime_dont_use_autosuspend(&pdev->dev);
2044 pm_runtime_put_noidle(&pdev->dev);
2045 /*
2046 * HACK: Clear the driver data, which is currently accessed by parent
2047 * glue drivers, before allowing the parent to suspend.
2048 */
2049 platform_set_drvdata(pdev, NULL);
2050 pm_runtime_set_suspended(&pdev->dev);
2051
2052 dwc3_free_event_buffers(dwc);
2053
2054 if (dwc->usb_psy)
2055 power_supply_put(dwc->usb_psy);
2056}
2057
2058#ifdef CONFIG_PM
2059static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2060{
2061 int ret;
2062
2063 ret = reset_control_deassert(dwc->reset);
2064 if (ret)
2065 return ret;
2066
2067 ret = dwc3_clk_enable(dwc);
2068 if (ret)
2069 goto assert_reset;
2070
2071 ret = dwc3_core_init(dwc);
2072 if (ret)
2073 goto disable_clks;
2074
2075 return 0;
2076
2077disable_clks:
2078 dwc3_clk_disable(dwc);
2079assert_reset:
2080 reset_control_assert(dwc->reset);
2081
2082 return ret;
2083}
2084
2085static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2086{
2087 unsigned long flags;
2088 u32 reg;
2089
2090 switch (dwc->current_dr_role) {
2091 case DWC3_GCTL_PRTCAP_DEVICE:
2092 if (pm_runtime_suspended(dwc->dev))
2093 break;
2094 dwc3_gadget_suspend(dwc);
2095 synchronize_irq(dwc->irq_gadget);
2096 dwc3_core_exit(dwc);
2097 break;
2098 case DWC3_GCTL_PRTCAP_HOST:
2099 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2100 dwc3_core_exit(dwc);
2101 break;
2102 }
2103
2104 /* Let controller to suspend HSPHY before PHY driver suspends */
2105 if (dwc->dis_u2_susphy_quirk ||
2106 dwc->dis_enblslpm_quirk) {
2107 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2108 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2109 DWC3_GUSB2PHYCFG_SUSPHY;
2110 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2111
2112 /* Give some time for USB2 PHY to suspend */
2113 usleep_range(5000, 6000);
2114 }
2115
2116 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2117 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2118 break;
2119 case DWC3_GCTL_PRTCAP_OTG:
2120 /* do nothing during runtime_suspend */
2121 if (PMSG_IS_AUTO(msg))
2122 break;
2123
2124 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2125 spin_lock_irqsave(&dwc->lock, flags);
2126 dwc3_gadget_suspend(dwc);
2127 spin_unlock_irqrestore(&dwc->lock, flags);
2128 synchronize_irq(dwc->irq_gadget);
2129 }
2130
2131 dwc3_otg_exit(dwc);
2132 dwc3_core_exit(dwc);
2133 break;
2134 default:
2135 /* do nothing */
2136 break;
2137 }
2138
2139 return 0;
2140}
2141
2142static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2143{
2144 unsigned long flags;
2145 int ret;
2146 u32 reg;
2147
2148 switch (dwc->current_dr_role) {
2149 case DWC3_GCTL_PRTCAP_DEVICE:
2150 ret = dwc3_core_init_for_resume(dwc);
2151 if (ret)
2152 return ret;
2153
2154 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2155 dwc3_gadget_resume(dwc);
2156 break;
2157 case DWC3_GCTL_PRTCAP_HOST:
2158 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2159 ret = dwc3_core_init_for_resume(dwc);
2160 if (ret)
2161 return ret;
2162 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2163 break;
2164 }
2165 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2166 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2167 if (dwc->dis_u2_susphy_quirk)
2168 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2169
2170 if (dwc->dis_enblslpm_quirk)
2171 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2172
2173 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2174
2175 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2176 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2177 break;
2178 case DWC3_GCTL_PRTCAP_OTG:
2179 /* nothing to do on runtime_resume */
2180 if (PMSG_IS_AUTO(msg))
2181 break;
2182
2183 ret = dwc3_core_init_for_resume(dwc);
2184 if (ret)
2185 return ret;
2186
2187 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2188
2189 dwc3_otg_init(dwc);
2190 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2191 dwc3_otg_host_init(dwc);
2192 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2193 spin_lock_irqsave(&dwc->lock, flags);
2194 dwc3_gadget_resume(dwc);
2195 spin_unlock_irqrestore(&dwc->lock, flags);
2196 }
2197
2198 break;
2199 default:
2200 /* do nothing */
2201 break;
2202 }
2203
2204 return 0;
2205}
2206
2207static int dwc3_runtime_checks(struct dwc3 *dwc)
2208{
2209 switch (dwc->current_dr_role) {
2210 case DWC3_GCTL_PRTCAP_DEVICE:
2211 if (dwc->connected)
2212 return -EBUSY;
2213 break;
2214 case DWC3_GCTL_PRTCAP_HOST:
2215 default:
2216 /* do nothing */
2217 break;
2218 }
2219
2220 return 0;
2221}
2222
2223static int dwc3_runtime_suspend(struct device *dev)
2224{
2225 struct dwc3 *dwc = dev_get_drvdata(dev);
2226 int ret;
2227
2228 if (dwc3_runtime_checks(dwc))
2229 return -EBUSY;
2230
2231 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2232 if (ret)
2233 return ret;
2234
2235 return 0;
2236}
2237
2238static int dwc3_runtime_resume(struct device *dev)
2239{
2240 struct dwc3 *dwc = dev_get_drvdata(dev);
2241 int ret;
2242
2243 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2244 if (ret)
2245 return ret;
2246
2247 switch (dwc->current_dr_role) {
2248 case DWC3_GCTL_PRTCAP_DEVICE:
2249 dwc3_gadget_process_pending_events(dwc);
2250 break;
2251 case DWC3_GCTL_PRTCAP_HOST:
2252 default:
2253 /* do nothing */
2254 break;
2255 }
2256
2257 pm_runtime_mark_last_busy(dev);
2258
2259 return 0;
2260}
2261
2262static int dwc3_runtime_idle(struct device *dev)
2263{
2264 struct dwc3 *dwc = dev_get_drvdata(dev);
2265
2266 switch (dwc->current_dr_role) {
2267 case DWC3_GCTL_PRTCAP_DEVICE:
2268 if (dwc3_runtime_checks(dwc))
2269 return -EBUSY;
2270 break;
2271 case DWC3_GCTL_PRTCAP_HOST:
2272 default:
2273 /* do nothing */
2274 break;
2275 }
2276
2277 pm_runtime_mark_last_busy(dev);
2278 pm_runtime_autosuspend(dev);
2279
2280 return 0;
2281}
2282#endif /* CONFIG_PM */
2283
2284#ifdef CONFIG_PM_SLEEP
2285static int dwc3_suspend(struct device *dev)
2286{
2287 struct dwc3 *dwc = dev_get_drvdata(dev);
2288 int ret;
2289
2290 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2291 if (ret)
2292 return ret;
2293
2294 pinctrl_pm_select_sleep_state(dev);
2295
2296 return 0;
2297}
2298
2299static int dwc3_resume(struct device *dev)
2300{
2301 struct dwc3 *dwc = dev_get_drvdata(dev);
2302 int ret;
2303
2304 pinctrl_pm_select_default_state(dev);
2305
2306 pm_runtime_disable(dev);
2307 pm_runtime_set_active(dev);
2308
2309 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2310 if (ret) {
2311 pm_runtime_set_suspended(dev);
2312 return ret;
2313 }
2314
2315 pm_runtime_enable(dev);
2316
2317 return 0;
2318}
2319
2320static void dwc3_complete(struct device *dev)
2321{
2322 struct dwc3 *dwc = dev_get_drvdata(dev);
2323 u32 reg;
2324
2325 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2326 dwc->dis_split_quirk) {
2327 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2328 reg |= DWC3_GUCTL3_SPLITDISABLE;
2329 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2330 }
2331}
2332#else
2333#define dwc3_complete NULL
2334#endif /* CONFIG_PM_SLEEP */
2335
2336static const struct dev_pm_ops dwc3_dev_pm_ops = {
2337 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2338 .complete = dwc3_complete,
2339 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2340 dwc3_runtime_idle)
2341};
2342
2343#ifdef CONFIG_OF
2344static const struct of_device_id of_dwc3_match[] = {
2345 {
2346 .compatible = "snps,dwc3"
2347 },
2348 {
2349 .compatible = "synopsys,dwc3"
2350 },
2351 { },
2352};
2353MODULE_DEVICE_TABLE(of, of_dwc3_match);
2354#endif
2355
2356#ifdef CONFIG_ACPI
2357
2358#define ACPI_ID_INTEL_BSW "808622B7"
2359
2360static const struct acpi_device_id dwc3_acpi_match[] = {
2361 { ACPI_ID_INTEL_BSW, 0 },
2362 { },
2363};
2364MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2365#endif
2366
2367static struct platform_driver dwc3_driver = {
2368 .probe = dwc3_probe,
2369 .remove_new = dwc3_remove,
2370 .driver = {
2371 .name = "dwc3",
2372 .of_match_table = of_match_ptr(of_dwc3_match),
2373 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2374 .pm = &dwc3_dev_pm_ops,
2375 },
2376};
2377
2378module_platform_driver(dwc3_driver);
2379
2380MODULE_ALIAS("platform:dwc3");
2381MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2382MODULE_LICENSE("GPL v2");
2383MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");