1/*
  2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 and
  6 * only version 2 as published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 *
 13 */
 14
 15#include "phy-qcom-ufs-qmp-14nm.h"
 16
 17#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
 18#define UFS_PHY_VDDA_PHY_UV	(925000)
 19
 20static
 21int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
 22					bool is_rate_B)
 23{
 24	int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
 25	int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
 26	int err;
 27
 28	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
 29		tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
 30
 31	if (err)
 32		dev_err(ufs_qcom_phy->dev,
 33			"%s: ufs_qcom_phy_calibrate() failed %d\n",
 34			__func__, err);
 35	return err;
 36}
 37
 38static
 39void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
 40{
 41	phy_common->quirks =
 42		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
 43}
 44
 45static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
 46{
 47	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 48	bool is_rate_B = false;
 49	int ret;
 50
 51	if (phy_common->mode == PHY_MODE_UFS_HS_B)
 52		is_rate_B = true;
 53
 54	ret = ufs_qcom_phy_qmp_14nm_phy_calibrate(phy_common, is_rate_B);
 55	if (!ret)
 56		/* phy calibrated, but yet to be started */
 57		phy_common->is_started = false;
 58
 59	return ret;
 60}
 61
 62static int ufs_qcom_phy_qmp_14nm_exit(struct phy *generic_phy)
 63{
 64	return 0;
 65}
 66
 67static
 68int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy, enum phy_mode mode)
 69{
 70	struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 71
 72	phy_common->mode = PHY_MODE_INVALID;
 73
 74	if (mode > 0)
 75		phy_common->mode = mode;
 76
 77	return 0;
 78}
 79
 80static
 81void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
 82{
 83	writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
 84	/*
 85	 * Before any transactions involving PHY, ensure PHY knows
 86	 * that it's analog rail is powered ON (or OFF).
 87	 */
 88	mb();
 89}
 90
 91static inline
 92void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
 93{
 94	/*
 95	 * 14nm PHY does not have TX_LANE_ENABLE register.
 96	 * Implement this function so as not to propagate error to caller.
 97	 */
 98}
 99
100static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
101{
102	u32 tmp;
103
104	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
105	tmp &= ~MASK_SERDES_START;
106	tmp |= (1 << OFFSET_SERDES_START);
107	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
108	/* Ensure register value is committed */
109	mb();
110}
111
112static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
113{
114	int err = 0;
115	u32 val;
116
117	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
118		val, (val & MASK_PCS_READY), 10, 1000000);
119	if (err)
120		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
121			__func__, err);
122	return err;
123}
124
125static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
126	.init		= ufs_qcom_phy_qmp_14nm_init,
127	.exit		= ufs_qcom_phy_qmp_14nm_exit,
128	.power_on	= ufs_qcom_phy_power_on,
129	.power_off	= ufs_qcom_phy_power_off,
130	.set_mode	= ufs_qcom_phy_qmp_14nm_set_mode,
131	.owner		= THIS_MODULE,
132};
133
134static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
135	.start_serdes		= ufs_qcom_phy_qmp_14nm_start_serdes,
136	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
137	.set_tx_lane_enable	= ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
138	.power_control		= ufs_qcom_phy_qmp_14nm_power_control,
139};
140
141static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
142{
143	struct device *dev = &pdev->dev;
144	struct phy *generic_phy;
145	struct ufs_qcom_phy_qmp_14nm *phy;
146	struct ufs_qcom_phy *phy_common;
147	int err = 0;
148
149	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
150	if (!phy) {
151		err = -ENOMEM;
152		goto out;
153	}
154	phy_common = &phy->common_cfg;
155
156	generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
157				&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
158
159	if (!generic_phy) {
160		err = -EIO;
161		goto out;
162	}
163
164	err = ufs_qcom_phy_init_clks(phy_common);
165	if (err)
166		goto out;
167
168	err = ufs_qcom_phy_init_vregulators(phy_common);
169	if (err)
170		goto out;
171
172	phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
173	phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
174
175	ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
176
177	phy_set_drvdata(generic_phy, phy);
178
179	strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
180
181out:
182	return err;
183}
184
185static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
186	{.compatible = "qcom,ufs-phy-qmp-14nm"},
187	{.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},
188	{},
189};
190MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
191
192static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
193	.probe = ufs_qcom_phy_qmp_14nm_probe,
194	.driver = {
195		.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
196		.name = "ufs_qcom_phy_qmp_14nm",
197	},
198};
199
200module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
201
202MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
203MODULE_LICENSE("GPL v2");