Loading...
1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
17
18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
19*******************************************************************************/
20
21#ifndef __COMMON_H__
22#define __COMMON_H__
23
24#include <linux/etherdevice.h>
25#include <linux/netdevice.h>
26#include <linux/stmmac.h>
27#include <linux/phy.h>
28#include <linux/module.h>
29#if IS_ENABLED(CONFIG_VLAN_8021Q)
30#define STMMAC_VLAN_TAG_USED
31#include <linux/if_vlan.h>
32#endif
33
34#include "descs.h"
35#include "mmc.h"
36
37/* Synopsys Core versions */
38#define DWMAC_CORE_3_40 0x34
39#define DWMAC_CORE_3_50 0x35
40#define DWMAC_CORE_4_00 0x40
41#define DWMAC_CORE_5_00 0x50
42#define DWMAC_CORE_5_10 0x51
43#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
44
45/* These need to be power of two, and >= 4 */
46#define DMA_TX_SIZE 512
47#define DMA_RX_SIZE 512
48#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
49
50#undef FRAME_FILTER_DEBUG
51/* #define FRAME_FILTER_DEBUG */
52
53/* Extra statistic and debug information exposed by ethtool */
54struct stmmac_extra_stats {
55 /* Transmit errors */
56 unsigned long tx_underflow ____cacheline_aligned;
57 unsigned long tx_carrier;
58 unsigned long tx_losscarrier;
59 unsigned long vlan_tag;
60 unsigned long tx_deferred;
61 unsigned long tx_vlan;
62 unsigned long tx_jabber;
63 unsigned long tx_frame_flushed;
64 unsigned long tx_payload_error;
65 unsigned long tx_ip_header_error;
66 /* Receive errors */
67 unsigned long rx_desc;
68 unsigned long sa_filter_fail;
69 unsigned long overflow_error;
70 unsigned long ipc_csum_error;
71 unsigned long rx_collision;
72 unsigned long rx_crc_errors;
73 unsigned long dribbling_bit;
74 unsigned long rx_length;
75 unsigned long rx_mii;
76 unsigned long rx_multicast;
77 unsigned long rx_gmac_overflow;
78 unsigned long rx_watchdog;
79 unsigned long da_rx_filter_fail;
80 unsigned long sa_rx_filter_fail;
81 unsigned long rx_missed_cntr;
82 unsigned long rx_overflow_cntr;
83 unsigned long rx_vlan;
84 /* Tx/Rx IRQ error info */
85 unsigned long tx_undeflow_irq;
86 unsigned long tx_process_stopped_irq;
87 unsigned long tx_jabber_irq;
88 unsigned long rx_overflow_irq;
89 unsigned long rx_buf_unav_irq;
90 unsigned long rx_process_stopped_irq;
91 unsigned long rx_watchdog_irq;
92 unsigned long tx_early_irq;
93 unsigned long fatal_bus_error_irq;
94 /* Tx/Rx IRQ Events */
95 unsigned long rx_early_irq;
96 unsigned long threshold;
97 unsigned long tx_pkt_n;
98 unsigned long rx_pkt_n;
99 unsigned long normal_irq_n;
100 unsigned long rx_normal_irq_n;
101 unsigned long napi_poll;
102 unsigned long tx_normal_irq_n;
103 unsigned long tx_clean;
104 unsigned long tx_set_ic_bit;
105 unsigned long irq_receive_pmt_irq_n;
106 /* MMC info */
107 unsigned long mmc_tx_irq_n;
108 unsigned long mmc_rx_irq_n;
109 unsigned long mmc_rx_csum_offload_irq_n;
110 /* EEE */
111 unsigned long irq_tx_path_in_lpi_mode_n;
112 unsigned long irq_tx_path_exit_lpi_mode_n;
113 unsigned long irq_rx_path_in_lpi_mode_n;
114 unsigned long irq_rx_path_exit_lpi_mode_n;
115 unsigned long phy_eee_wakeup_error_n;
116 /* Extended RDES status */
117 unsigned long ip_hdr_err;
118 unsigned long ip_payload_err;
119 unsigned long ip_csum_bypassed;
120 unsigned long ipv4_pkt_rcvd;
121 unsigned long ipv6_pkt_rcvd;
122 unsigned long no_ptp_rx_msg_type_ext;
123 unsigned long ptp_rx_msg_type_sync;
124 unsigned long ptp_rx_msg_type_follow_up;
125 unsigned long ptp_rx_msg_type_delay_req;
126 unsigned long ptp_rx_msg_type_delay_resp;
127 unsigned long ptp_rx_msg_type_pdelay_req;
128 unsigned long ptp_rx_msg_type_pdelay_resp;
129 unsigned long ptp_rx_msg_type_pdelay_follow_up;
130 unsigned long ptp_rx_msg_type_announce;
131 unsigned long ptp_rx_msg_type_management;
132 unsigned long ptp_rx_msg_pkt_reserved_type;
133 unsigned long ptp_frame_type;
134 unsigned long ptp_ver;
135 unsigned long timestamp_dropped;
136 unsigned long av_pkt_rcvd;
137 unsigned long av_tagged_pkt_rcvd;
138 unsigned long vlan_tag_priority_val;
139 unsigned long l3_filter_match;
140 unsigned long l4_filter_match;
141 unsigned long l3_l4_filter_no_match;
142 /* PCS */
143 unsigned long irq_pcs_ane_n;
144 unsigned long irq_pcs_link_n;
145 unsigned long irq_rgmii_n;
146 unsigned long pcs_link;
147 unsigned long pcs_duplex;
148 unsigned long pcs_speed;
149 /* debug register */
150 unsigned long mtl_tx_status_fifo_full;
151 unsigned long mtl_tx_fifo_not_empty;
152 unsigned long mmtl_fifo_ctrl;
153 unsigned long mtl_tx_fifo_read_ctrl_write;
154 unsigned long mtl_tx_fifo_read_ctrl_wait;
155 unsigned long mtl_tx_fifo_read_ctrl_read;
156 unsigned long mtl_tx_fifo_read_ctrl_idle;
157 unsigned long mac_tx_in_pause;
158 unsigned long mac_tx_frame_ctrl_xfer;
159 unsigned long mac_tx_frame_ctrl_idle;
160 unsigned long mac_tx_frame_ctrl_wait;
161 unsigned long mac_tx_frame_ctrl_pause;
162 unsigned long mac_gmii_tx_proto_engine;
163 unsigned long mtl_rx_fifo_fill_level_full;
164 unsigned long mtl_rx_fifo_fill_above_thresh;
165 unsigned long mtl_rx_fifo_fill_below_thresh;
166 unsigned long mtl_rx_fifo_fill_level_empty;
167 unsigned long mtl_rx_fifo_read_ctrl_flush;
168 unsigned long mtl_rx_fifo_read_ctrl_read_data;
169 unsigned long mtl_rx_fifo_read_ctrl_status;
170 unsigned long mtl_rx_fifo_read_ctrl_idle;
171 unsigned long mtl_rx_fifo_ctrl_active;
172 unsigned long mac_rx_frame_ctrl_fifo;
173 unsigned long mac_gmii_rx_proto_engine;
174 /* TSO */
175 unsigned long tx_tso_frames;
176 unsigned long tx_tso_nfrags;
177};
178
179/* Safety Feature statistics exposed by ethtool */
180struct stmmac_safety_stats {
181 unsigned long mac_errors[32];
182 unsigned long mtl_errors[32];
183 unsigned long dma_errors[32];
184};
185
186/* Number of fields in Safety Stats */
187#define STMMAC_SAFETY_FEAT_SIZE \
188 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
189
190/* CSR Frequency Access Defines*/
191#define CSR_F_35M 35000000
192#define CSR_F_60M 60000000
193#define CSR_F_100M 100000000
194#define CSR_F_150M 150000000
195#define CSR_F_250M 250000000
196#define CSR_F_300M 300000000
197
198#define MAC_CSR_H_FRQ_MASK 0x20
199
200#define HASH_TABLE_SIZE 64
201#define PAUSE_TIME 0xffff
202
203/* Flow Control defines */
204#define FLOW_OFF 0
205#define FLOW_RX 1
206#define FLOW_TX 2
207#define FLOW_AUTO (FLOW_TX | FLOW_RX)
208
209/* PCS defines */
210#define STMMAC_PCS_RGMII (1 << 0)
211#define STMMAC_PCS_SGMII (1 << 1)
212#define STMMAC_PCS_TBI (1 << 2)
213#define STMMAC_PCS_RTBI (1 << 3)
214
215#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
216
217/* DAM HW feature register fields */
218#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
219#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
220#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
221#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
222#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
223#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
224#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
225#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
226#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
227#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
228#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
229#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
230#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
231#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
232#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
233#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
234#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
235#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
236#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
237#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
238#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
239#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
240#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
241/* Timestamping with Internal System Time */
242#define DMA_HW_FEAT_INTTSEN 0x02000000
243#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
244#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
245#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
246#define DEFAULT_DMA_PBL 8
247
248/* PCS status and mask defines */
249#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
250#define PCS_LINK_IRQ BIT(1) /* PCS Link */
251#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
252
253/* Max/Min RI Watchdog Timer count value */
254#define MAX_DMA_RIWT 0xff
255#define MIN_DMA_RIWT 0x20
256/* Tx coalesce parameters */
257#define STMMAC_COAL_TX_TIMER 40000
258#define STMMAC_MAX_COAL_TX_TICK 100000
259#define STMMAC_TX_MAX_FRAMES 256
260#define STMMAC_TX_FRAMES 64
261
262/* Packets types */
263enum packets_types {
264 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
265 PACKET_PTPQ = 0x2, /* PTP Packets */
266 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
267 PACKET_UPQ = 0x4, /* Untagged Packets */
268 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
269};
270
271/* Rx IPC status */
272enum rx_frame_status {
273 good_frame = 0x0,
274 discard_frame = 0x1,
275 csum_none = 0x2,
276 llc_snap = 0x4,
277 dma_own = 0x8,
278 rx_not_ls = 0x10,
279};
280
281/* Tx status */
282enum tx_frame_status {
283 tx_done = 0x0,
284 tx_not_ls = 0x1,
285 tx_err = 0x2,
286 tx_dma_own = 0x4,
287};
288
289enum dma_irq_status {
290 tx_hard_error = 0x1,
291 tx_hard_error_bump_tc = 0x2,
292 handle_rx = 0x4,
293 handle_tx = 0x8,
294};
295
296/* EEE and LPI defines */
297#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
298#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
299#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
300#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
301
302#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
303
304/* Physical Coding Sublayer */
305struct rgmii_adv {
306 unsigned int pause;
307 unsigned int duplex;
308 unsigned int lp_pause;
309 unsigned int lp_duplex;
310};
311
312#define STMMAC_PCS_PAUSE 1
313#define STMMAC_PCS_ASYM_PAUSE 2
314
315/* DMA HW capabilities */
316struct dma_features {
317 unsigned int mbps_10_100;
318 unsigned int mbps_1000;
319 unsigned int half_duplex;
320 unsigned int hash_filter;
321 unsigned int multi_addr;
322 unsigned int pcs;
323 unsigned int sma_mdio;
324 unsigned int pmt_remote_wake_up;
325 unsigned int pmt_magic_frame;
326 unsigned int rmon;
327 /* IEEE 1588-2002 */
328 unsigned int time_stamp;
329 /* IEEE 1588-2008 */
330 unsigned int atime_stamp;
331 /* 802.3az - Energy-Efficient Ethernet (EEE) */
332 unsigned int eee;
333 unsigned int av;
334 unsigned int tsoen;
335 /* TX and RX csum */
336 unsigned int tx_coe;
337 unsigned int rx_coe;
338 unsigned int rx_coe_type1;
339 unsigned int rx_coe_type2;
340 unsigned int rxfifo_over_2048;
341 /* TX and RX number of channels */
342 unsigned int number_rx_channel;
343 unsigned int number_tx_channel;
344 /* TX and RX number of queues */
345 unsigned int number_rx_queues;
346 unsigned int number_tx_queues;
347 /* Alternate (enhanced) DESC mode */
348 unsigned int enh_desc;
349 /* TX and RX FIFO sizes */
350 unsigned int tx_fifo_size;
351 unsigned int rx_fifo_size;
352 /* Automotive Safety Package */
353 unsigned int asp;
354};
355
356/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
357#define BUF_SIZE_16KiB 16384
358#define BUF_SIZE_8KiB 8192
359#define BUF_SIZE_4KiB 4096
360#define BUF_SIZE_2KiB 2048
361
362/* Power Down and WOL */
363#define PMT_NOT_SUPPORTED 0
364#define PMT_SUPPORTED 1
365
366/* Common MAC defines */
367#define MAC_CTRL_REG 0x00000000 /* MAC Control */
368#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
369#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
370
371/* Default LPI timers */
372#define STMMAC_DEFAULT_LIT_LS 0x3E8
373#define STMMAC_DEFAULT_TWT_LS 0x1E
374
375#define STMMAC_CHAIN_MODE 0x1
376#define STMMAC_RING_MODE 0x2
377
378#define JUMBO_LEN 9000
379
380/* Descriptors helpers */
381struct stmmac_desc_ops {
382 /* DMA RX descriptor ring initialization */
383 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
384 int end);
385 /* DMA TX descriptor ring initialization */
386 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
387
388 /* Invoked by the xmit function to prepare the tx descriptor */
389 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
390 bool csum_flag, int mode, bool tx_own,
391 bool ls, unsigned int tot_pkt_len);
392 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
393 int len2, bool tx_own, bool ls,
394 unsigned int tcphdrlen,
395 unsigned int tcppayloadlen);
396 /* Set/get the owner of the descriptor */
397 void (*set_tx_owner) (struct dma_desc *p);
398 int (*get_tx_owner) (struct dma_desc *p);
399 /* Clean the tx descriptor as soon as the tx irq is received */
400 void (*release_tx_desc) (struct dma_desc *p, int mode);
401 /* Clear interrupt on tx frame completion. When this bit is
402 * set an interrupt happens as soon as the frame is transmitted */
403 void (*set_tx_ic)(struct dma_desc *p);
404 /* Last tx segment reports the transmit status */
405 int (*get_tx_ls) (struct dma_desc *p);
406 /* Return the transmit status looking at the TDES1 */
407 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
408 struct dma_desc *p, void __iomem *ioaddr);
409 /* Get the buffer size from the descriptor */
410 int (*get_tx_len) (struct dma_desc *p);
411 /* Handle extra events on specific interrupts hw dependent */
412 void (*set_rx_owner) (struct dma_desc *p);
413 /* Get the receive frame size */
414 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
415 /* Return the reception status looking at the RDES1 */
416 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
417 struct dma_desc *p);
418 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
419 struct dma_extended_desc *p);
420 /* Set tx timestamp enable bit */
421 void (*enable_tx_timestamp) (struct dma_desc *p);
422 /* get tx timestamp status */
423 int (*get_tx_timestamp_status) (struct dma_desc *p);
424 /* get timestamp value */
425 u64(*get_timestamp) (void *desc, u32 ats);
426 /* get rx timestamp status */
427 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
428 /* Display ring */
429 void (*display_ring)(void *head, unsigned int size, bool rx);
430 /* set MSS via context descriptor */
431 void (*set_mss)(struct dma_desc *p, unsigned int mss);
432};
433
434extern const struct stmmac_desc_ops enh_desc_ops;
435extern const struct stmmac_desc_ops ndesc_ops;
436
437/* Specific DMA helpers */
438struct stmmac_dma_ops {
439 /* DMA core initialization */
440 int (*reset)(void __iomem *ioaddr);
441 void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
442 u32 dma_tx, u32 dma_rx, int atds);
443 void (*init_chan)(void __iomem *ioaddr,
444 struct stmmac_dma_cfg *dma_cfg, u32 chan);
445 void (*init_rx_chan)(void __iomem *ioaddr,
446 struct stmmac_dma_cfg *dma_cfg,
447 u32 dma_rx_phy, u32 chan);
448 void (*init_tx_chan)(void __iomem *ioaddr,
449 struct stmmac_dma_cfg *dma_cfg,
450 u32 dma_tx_phy, u32 chan);
451 /* Configure the AXI Bus Mode Register */
452 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
453 /* Dump DMA registers */
454 void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
455 /* Set tx/rx threshold in the csr6 register
456 * An invalid value enables the store-and-forward mode */
457 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
458 int rxfifosz);
459 void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,
460 int fifosz, u8 qmode);
461 void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel,
462 int fifosz, u8 qmode);
463 /* To track extra statistic (if supported) */
464 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
465 void __iomem *ioaddr);
466 void (*enable_dma_transmission) (void __iomem *ioaddr);
467 void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
468 void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
469 void (*start_tx)(void __iomem *ioaddr, u32 chan);
470 void (*stop_tx)(void __iomem *ioaddr, u32 chan);
471 void (*start_rx)(void __iomem *ioaddr, u32 chan);
472 void (*stop_rx)(void __iomem *ioaddr, u32 chan);
473 int (*dma_interrupt) (void __iomem *ioaddr,
474 struct stmmac_extra_stats *x, u32 chan);
475 /* If supported then get the optional core features */
476 void (*get_hw_feature)(void __iomem *ioaddr,
477 struct dma_features *dma_cap);
478 /* Program the HW RX Watchdog */
479 void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt, u32 number_chan);
480 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
481 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len, u32 chan);
482 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
483 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
484 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
485};
486
487struct mac_device_info;
488
489/* Helpers to program the MAC core */
490struct stmmac_ops {
491 /* MAC core initialization */
492 void (*core_init)(struct mac_device_info *hw, struct net_device *dev);
493 /* Enable the MAC RX/TX */
494 void (*set_mac)(void __iomem *ioaddr, bool enable);
495 /* Enable and verify that the IPC module is supported */
496 int (*rx_ipc)(struct mac_device_info *hw);
497 /* Enable RX Queues */
498 void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
499 /* RX Queues Priority */
500 void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
501 /* TX Queues Priority */
502 void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
503 /* RX Queues Routing */
504 void (*rx_queue_routing)(struct mac_device_info *hw, u8 packet,
505 u32 queue);
506 /* Program RX Algorithms */
507 void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
508 /* Program TX Algorithms */
509 void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
510 /* Set MTL TX queues weight */
511 void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
512 u32 weight, u32 queue);
513 /* RX MTL queue to RX dma mapping */
514 void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
515 /* Configure AV Algorithm */
516 void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
517 u32 idle_slope, u32 high_credit, u32 low_credit,
518 u32 queue);
519 /* Dump MAC registers */
520 void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
521 /* Handle extra events on specific interrupts hw dependent */
522 int (*host_irq_status)(struct mac_device_info *hw,
523 struct stmmac_extra_stats *x);
524 /* Handle MTL interrupts */
525 int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
526 /* Multicast filter setting */
527 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
528 /* Flow control setting */
529 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
530 unsigned int fc, unsigned int pause_time, u32 tx_cnt);
531 /* Set power management mode (e.g. magic frame) */
532 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
533 /* Set/Get Unicast MAC addresses */
534 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
535 unsigned int reg_n);
536 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
537 unsigned int reg_n);
538 void (*set_eee_mode)(struct mac_device_info *hw,
539 bool en_tx_lpi_clockgating);
540 void (*reset_eee_mode)(struct mac_device_info *hw);
541 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
542 void (*set_eee_pls)(struct mac_device_info *hw, int link);
543 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
544 u32 rx_queues, u32 tx_queues);
545 /* PCS calls */
546 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
547 bool loopback);
548 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
549 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
550 /* Safety Features */
551 int (*safety_feat_config)(void __iomem *ioaddr, unsigned int asp);
552 bool (*safety_feat_irq_status)(struct net_device *ndev,
553 void __iomem *ioaddr, unsigned int asp,
554 struct stmmac_safety_stats *stats);
555 const char *(*safety_feat_dump)(struct stmmac_safety_stats *stats,
556 int index, unsigned long *count);
557};
558
559/* PTP and HW Timer helpers */
560struct stmmac_hwtimestamp {
561 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
562 u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
563 int gmac4);
564 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
565 int (*config_addend) (void __iomem *ioaddr, u32 addend);
566 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
567 int add_sub, int gmac4);
568 u64(*get_systime) (void __iomem *ioaddr);
569};
570
571extern const struct stmmac_hwtimestamp stmmac_ptp;
572extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
573
574struct mac_link {
575 u32 speed_mask;
576 u32 speed10;
577 u32 speed100;
578 u32 speed1000;
579 u32 duplex;
580};
581
582struct mii_regs {
583 unsigned int addr; /* MII Address */
584 unsigned int data; /* MII Data */
585 unsigned int addr_shift; /* MII address shift */
586 unsigned int reg_shift; /* MII reg shift */
587 unsigned int addr_mask; /* MII address mask */
588 unsigned int reg_mask; /* MII reg mask */
589 unsigned int clk_csr_shift;
590 unsigned int clk_csr_mask;
591};
592
593/* Helpers to manage the descriptors for chain and ring modes */
594struct stmmac_mode_ops {
595 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
596 unsigned int extend_desc);
597 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
598 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
599 int (*set_16kib_bfsize)(int mtu);
600 void (*init_desc3)(struct dma_desc *p);
601 void (*refill_desc3) (void *priv, struct dma_desc *p);
602 void (*clean_desc3) (void *priv, struct dma_desc *p);
603};
604
605struct mac_device_info {
606 const struct stmmac_ops *mac;
607 const struct stmmac_desc_ops *desc;
608 const struct stmmac_dma_ops *dma;
609 const struct stmmac_mode_ops *mode;
610 const struct stmmac_hwtimestamp *ptp;
611 struct mii_regs mii; /* MII register Addresses */
612 struct mac_link link;
613 void __iomem *pcsr; /* vpointer to device CSRs */
614 int multicast_filter_bins;
615 int unicast_filter_entries;
616 int mcast_bits_log2;
617 unsigned int rx_csum;
618 unsigned int pcs;
619 unsigned int pmt;
620 unsigned int ps;
621};
622
623struct stmmac_rx_routing {
624 u32 reg_mask;
625 u32 reg_shift;
626};
627
628struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
629 int perfect_uc_entries,
630 int *synopsys_id);
631struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
632struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
633 int perfect_uc_entries, int *synopsys_id);
634
635void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
636 unsigned int high, unsigned int low);
637void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
638 unsigned int high, unsigned int low);
639void stmmac_set_mac(void __iomem *ioaddr, bool enable);
640
641void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
642 unsigned int high, unsigned int low);
643void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
644 unsigned int high, unsigned int low);
645void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
646
647void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
648
649extern const struct stmmac_mode_ops ring_mode_ops;
650extern const struct stmmac_mode_ops chain_mode_ops;
651extern const struct stmmac_desc_ops dwmac4_desc_ops;
652
653/**
654 * stmmac_get_synopsys_id - return the SYINID.
655 * @priv: driver private structure
656 * Description: this simple function is to decode and return the SYINID
657 * starting from the HW core register.
658 */
659static inline u32 stmmac_get_synopsys_id(u32 hwid)
660{
661 /* Check Synopsys Id (not available on old chips) */
662 if (likely(hwid)) {
663 u32 uid = ((hwid & 0x0000ff00) >> 8);
664 u32 synid = (hwid & 0x000000ff);
665
666 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
667 uid, synid);
668
669 return synid;
670 }
671 return 0;
672}
673#endif /* __COMMON_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __COMMON_H__
12#define __COMMON_H__
13
14#include <linux/etherdevice.h>
15#include <linux/netdevice.h>
16#include <linux/stmmac.h>
17#include <linux/phy.h>
18#include <linux/pcs/pcs-xpcs.h>
19#include <linux/module.h>
20#if IS_ENABLED(CONFIG_VLAN_8021Q)
21#define STMMAC_VLAN_TAG_USED
22#include <linux/if_vlan.h>
23#endif
24
25#include "descs.h"
26#include "hwif.h"
27#include "mmc.h"
28
29/* Synopsys Core versions */
30#define DWMAC_CORE_3_40 0x34
31#define DWMAC_CORE_3_50 0x35
32#define DWMAC_CORE_4_00 0x40
33#define DWMAC_CORE_4_10 0x41
34#define DWMAC_CORE_5_00 0x50
35#define DWMAC_CORE_5_10 0x51
36#define DWMAC_CORE_5_20 0x52
37#define DWXGMAC_CORE_2_10 0x21
38#define DWXGMAC_CORE_2_20 0x22
39#define DWXLGMAC_CORE_2_00 0x20
40
41/* Device ID */
42#define DWXGMAC_ID 0x76
43#define DWXLGMAC_ID 0x27
44
45#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
46
47/* TX and RX Descriptor Length, these need to be power of two.
48 * TX descriptor length less than 64 may cause transmit queue timed out error.
49 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
50 */
51#define DMA_MIN_TX_SIZE 64
52#define DMA_MAX_TX_SIZE 1024
53#define DMA_DEFAULT_TX_SIZE 512
54#define DMA_MIN_RX_SIZE 64
55#define DMA_MAX_RX_SIZE 1024
56#define DMA_DEFAULT_RX_SIZE 512
57#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
58
59#undef FRAME_FILTER_DEBUG
60/* #define FRAME_FILTER_DEBUG */
61
62struct stmmac_q_tx_stats {
63 u64_stats_t tx_bytes;
64 u64_stats_t tx_set_ic_bit;
65 u64_stats_t tx_tso_frames;
66 u64_stats_t tx_tso_nfrags;
67};
68
69struct stmmac_napi_tx_stats {
70 u64_stats_t tx_packets;
71 u64_stats_t tx_pkt_n;
72 u64_stats_t poll;
73 u64_stats_t tx_clean;
74 u64_stats_t tx_set_ic_bit;
75};
76
77struct stmmac_txq_stats {
78 /* Updates protected by tx queue lock. */
79 struct u64_stats_sync q_syncp;
80 struct stmmac_q_tx_stats q;
81
82 /* Updates protected by NAPI poll logic. */
83 struct u64_stats_sync napi_syncp;
84 struct stmmac_napi_tx_stats napi;
85} ____cacheline_aligned_in_smp;
86
87struct stmmac_napi_rx_stats {
88 u64_stats_t rx_bytes;
89 u64_stats_t rx_packets;
90 u64_stats_t rx_pkt_n;
91 u64_stats_t poll;
92};
93
94struct stmmac_rxq_stats {
95 /* Updates protected by NAPI poll logic. */
96 struct u64_stats_sync napi_syncp;
97 struct stmmac_napi_rx_stats napi;
98} ____cacheline_aligned_in_smp;
99
100/* Updates on each CPU protected by not allowing nested irqs. */
101struct stmmac_pcpu_stats {
102 struct u64_stats_sync syncp;
103 u64_stats_t rx_normal_irq_n[MTL_MAX_TX_QUEUES];
104 u64_stats_t tx_normal_irq_n[MTL_MAX_RX_QUEUES];
105};
106
107/* Extra statistic and debug information exposed by ethtool */
108struct stmmac_extra_stats {
109 /* Transmit errors */
110 unsigned long tx_underflow ____cacheline_aligned;
111 unsigned long tx_carrier;
112 unsigned long tx_losscarrier;
113 unsigned long vlan_tag;
114 unsigned long tx_deferred;
115 unsigned long tx_vlan;
116 unsigned long tx_jabber;
117 unsigned long tx_frame_flushed;
118 unsigned long tx_payload_error;
119 unsigned long tx_ip_header_error;
120 unsigned long tx_collision;
121 /* Receive errors */
122 unsigned long rx_desc;
123 unsigned long sa_filter_fail;
124 unsigned long overflow_error;
125 unsigned long ipc_csum_error;
126 unsigned long rx_collision;
127 unsigned long rx_crc_errors;
128 unsigned long dribbling_bit;
129 unsigned long rx_length;
130 unsigned long rx_mii;
131 unsigned long rx_multicast;
132 unsigned long rx_gmac_overflow;
133 unsigned long rx_watchdog;
134 unsigned long da_rx_filter_fail;
135 unsigned long sa_rx_filter_fail;
136 unsigned long rx_missed_cntr;
137 unsigned long rx_overflow_cntr;
138 unsigned long rx_vlan;
139 unsigned long rx_split_hdr_pkt_n;
140 /* Tx/Rx IRQ error info */
141 unsigned long tx_undeflow_irq;
142 unsigned long tx_process_stopped_irq;
143 unsigned long tx_jabber_irq;
144 unsigned long rx_overflow_irq;
145 unsigned long rx_buf_unav_irq;
146 unsigned long rx_process_stopped_irq;
147 unsigned long rx_watchdog_irq;
148 unsigned long tx_early_irq;
149 unsigned long fatal_bus_error_irq;
150 /* Tx/Rx IRQ Events */
151 unsigned long rx_early_irq;
152 unsigned long threshold;
153 unsigned long irq_receive_pmt_irq_n;
154 /* MMC info */
155 unsigned long mmc_tx_irq_n;
156 unsigned long mmc_rx_irq_n;
157 unsigned long mmc_rx_csum_offload_irq_n;
158 /* EEE */
159 unsigned long irq_tx_path_in_lpi_mode_n;
160 unsigned long irq_tx_path_exit_lpi_mode_n;
161 unsigned long irq_rx_path_in_lpi_mode_n;
162 unsigned long irq_rx_path_exit_lpi_mode_n;
163 unsigned long phy_eee_wakeup_error_n;
164 /* Extended RDES status */
165 unsigned long ip_hdr_err;
166 unsigned long ip_payload_err;
167 unsigned long ip_csum_bypassed;
168 unsigned long ipv4_pkt_rcvd;
169 unsigned long ipv6_pkt_rcvd;
170 unsigned long no_ptp_rx_msg_type_ext;
171 unsigned long ptp_rx_msg_type_sync;
172 unsigned long ptp_rx_msg_type_follow_up;
173 unsigned long ptp_rx_msg_type_delay_req;
174 unsigned long ptp_rx_msg_type_delay_resp;
175 unsigned long ptp_rx_msg_type_pdelay_req;
176 unsigned long ptp_rx_msg_type_pdelay_resp;
177 unsigned long ptp_rx_msg_type_pdelay_follow_up;
178 unsigned long ptp_rx_msg_type_announce;
179 unsigned long ptp_rx_msg_type_management;
180 unsigned long ptp_rx_msg_pkt_reserved_type;
181 unsigned long ptp_frame_type;
182 unsigned long ptp_ver;
183 unsigned long timestamp_dropped;
184 unsigned long av_pkt_rcvd;
185 unsigned long av_tagged_pkt_rcvd;
186 unsigned long vlan_tag_priority_val;
187 unsigned long l3_filter_match;
188 unsigned long l4_filter_match;
189 unsigned long l3_l4_filter_no_match;
190 /* PCS */
191 unsigned long irq_pcs_ane_n;
192 unsigned long irq_pcs_link_n;
193 unsigned long irq_rgmii_n;
194 unsigned long pcs_link;
195 unsigned long pcs_duplex;
196 unsigned long pcs_speed;
197 /* debug register */
198 unsigned long mtl_tx_status_fifo_full;
199 unsigned long mtl_tx_fifo_not_empty;
200 unsigned long mmtl_fifo_ctrl;
201 unsigned long mtl_tx_fifo_read_ctrl_write;
202 unsigned long mtl_tx_fifo_read_ctrl_wait;
203 unsigned long mtl_tx_fifo_read_ctrl_read;
204 unsigned long mtl_tx_fifo_read_ctrl_idle;
205 unsigned long mac_tx_in_pause;
206 unsigned long mac_tx_frame_ctrl_xfer;
207 unsigned long mac_tx_frame_ctrl_idle;
208 unsigned long mac_tx_frame_ctrl_wait;
209 unsigned long mac_tx_frame_ctrl_pause;
210 unsigned long mac_gmii_tx_proto_engine;
211 unsigned long mtl_rx_fifo_fill_level_full;
212 unsigned long mtl_rx_fifo_fill_above_thresh;
213 unsigned long mtl_rx_fifo_fill_below_thresh;
214 unsigned long mtl_rx_fifo_fill_level_empty;
215 unsigned long mtl_rx_fifo_read_ctrl_flush;
216 unsigned long mtl_rx_fifo_read_ctrl_read_data;
217 unsigned long mtl_rx_fifo_read_ctrl_status;
218 unsigned long mtl_rx_fifo_read_ctrl_idle;
219 unsigned long mtl_rx_fifo_ctrl_active;
220 unsigned long mac_rx_frame_ctrl_fifo;
221 unsigned long mac_gmii_rx_proto_engine;
222 /* EST */
223 unsigned long mtl_est_cgce;
224 unsigned long mtl_est_hlbs;
225 unsigned long mtl_est_hlbf;
226 unsigned long mtl_est_btre;
227 unsigned long mtl_est_btrlm;
228 unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES];
229 unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES];
230 /* per queue statistics */
231 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
232 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
233 struct stmmac_pcpu_stats __percpu *pcpu_stats;
234 unsigned long rx_dropped;
235 unsigned long rx_errors;
236 unsigned long tx_dropped;
237 unsigned long tx_errors;
238};
239
240/* Safety Feature statistics exposed by ethtool */
241struct stmmac_safety_stats {
242 unsigned long mac_errors[32];
243 unsigned long mtl_errors[32];
244 unsigned long dma_errors[32];
245 unsigned long dma_dpp_errors[32];
246};
247
248/* Number of fields in Safety Stats */
249#define STMMAC_SAFETY_FEAT_SIZE \
250 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
251
252/* CSR Frequency Access Defines*/
253#define CSR_F_35M 35000000
254#define CSR_F_60M 60000000
255#define CSR_F_100M 100000000
256#define CSR_F_150M 150000000
257#define CSR_F_250M 250000000
258#define CSR_F_300M 300000000
259
260#define MAC_CSR_H_FRQ_MASK 0x20
261
262#define HASH_TABLE_SIZE 64
263#define PAUSE_TIME 0xffff
264
265/* Flow Control defines */
266#define FLOW_OFF 0
267#define FLOW_RX 1
268#define FLOW_TX 2
269#define FLOW_AUTO (FLOW_TX | FLOW_RX)
270
271/* PCS defines */
272#define STMMAC_PCS_RGMII (1 << 0)
273#define STMMAC_PCS_SGMII (1 << 1)
274#define STMMAC_PCS_TBI (1 << 2)
275#define STMMAC_PCS_RTBI (1 << 3)
276
277#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
278
279/* DMA HW feature register fields */
280#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
281#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
282#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
283#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
284#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
285#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
286#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
287#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
288#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
289#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
290#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
291#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
292#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
293#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
294#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
295#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
296#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
297#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
298#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
299#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
300#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
301#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
302#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
303/* Timestamping with Internal System Time */
304#define DMA_HW_FEAT_INTTSEN 0x02000000
305#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
306#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
307#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
308#define DEFAULT_DMA_PBL 8
309
310/* MSI defines */
311#define STMMAC_MSI_VEC_MAX 32
312
313/* PCS status and mask defines */
314#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
315#define PCS_LINK_IRQ BIT(1) /* PCS Link */
316#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
317
318/* Max/Min RI Watchdog Timer count value */
319#define MAX_DMA_RIWT 0xff
320#define MIN_DMA_RIWT 0x10
321#define DEF_DMA_RIWT 0xa0
322/* Tx coalesce parameters */
323#define STMMAC_COAL_TX_TIMER 5000
324#define STMMAC_MAX_COAL_TX_TICK 100000
325#define STMMAC_TX_MAX_FRAMES 256
326#define STMMAC_TX_FRAMES 25
327#define STMMAC_RX_FRAMES 0
328
329/* Packets types */
330enum packets_types {
331 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
332 PACKET_PTPQ = 0x2, /* PTP Packets */
333 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
334 PACKET_UPQ = 0x4, /* Untagged Packets */
335 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
336};
337
338/* Rx IPC status */
339enum rx_frame_status {
340 good_frame = 0x0,
341 discard_frame = 0x1,
342 csum_none = 0x2,
343 llc_snap = 0x4,
344 dma_own = 0x8,
345 rx_not_ls = 0x10,
346};
347
348/* Tx status */
349enum tx_frame_status {
350 tx_done = 0x0,
351 tx_not_ls = 0x1,
352 tx_err = 0x2,
353 tx_dma_own = 0x4,
354 tx_err_bump_tc = 0x8,
355};
356
357enum dma_irq_status {
358 tx_hard_error = 0x1,
359 tx_hard_error_bump_tc = 0x2,
360 handle_rx = 0x4,
361 handle_tx = 0x8,
362};
363
364enum dma_irq_dir {
365 DMA_DIR_RX = 0x1,
366 DMA_DIR_TX = 0x2,
367 DMA_DIR_RXTX = 0x3,
368};
369
370enum request_irq_err {
371 REQ_IRQ_ERR_ALL,
372 REQ_IRQ_ERR_TX,
373 REQ_IRQ_ERR_RX,
374 REQ_IRQ_ERR_SFTY,
375 REQ_IRQ_ERR_SFTY_UE,
376 REQ_IRQ_ERR_SFTY_CE,
377 REQ_IRQ_ERR_LPI,
378 REQ_IRQ_ERR_WOL,
379 REQ_IRQ_ERR_MAC,
380 REQ_IRQ_ERR_NO,
381};
382
383/* EEE and LPI defines */
384#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
385#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
386#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
387#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
388
389/* FPE defines */
390#define FPE_EVENT_UNKNOWN 0
391#define FPE_EVENT_TRSP BIT(0)
392#define FPE_EVENT_TVER BIT(1)
393#define FPE_EVENT_RRSP BIT(2)
394#define FPE_EVENT_RVER BIT(3)
395
396#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
397
398/* Physical Coding Sublayer */
399struct rgmii_adv {
400 unsigned int pause;
401 unsigned int duplex;
402 unsigned int lp_pause;
403 unsigned int lp_duplex;
404};
405
406#define STMMAC_PCS_PAUSE 1
407#define STMMAC_PCS_ASYM_PAUSE 2
408
409/* DMA HW capabilities */
410struct dma_features {
411 unsigned int mbps_10_100;
412 unsigned int mbps_1000;
413 unsigned int half_duplex;
414 unsigned int hash_filter;
415 unsigned int multi_addr;
416 unsigned int pcs;
417 unsigned int sma_mdio;
418 unsigned int pmt_remote_wake_up;
419 unsigned int pmt_magic_frame;
420 unsigned int rmon;
421 /* IEEE 1588-2002 */
422 unsigned int time_stamp;
423 /* IEEE 1588-2008 */
424 unsigned int atime_stamp;
425 /* 802.3az - Energy-Efficient Ethernet (EEE) */
426 unsigned int eee;
427 unsigned int av;
428 unsigned int hash_tb_sz;
429 unsigned int tsoen;
430 /* TX and RX csum */
431 unsigned int tx_coe;
432 unsigned int rx_coe;
433 unsigned int rx_coe_type1;
434 unsigned int rx_coe_type2;
435 unsigned int rxfifo_over_2048;
436 /* TX and RX number of channels */
437 unsigned int number_rx_channel;
438 unsigned int number_tx_channel;
439 /* TX and RX number of queues */
440 unsigned int number_rx_queues;
441 unsigned int number_tx_queues;
442 /* PPS output */
443 unsigned int pps_out_num;
444 /* Number of Traffic Classes */
445 unsigned int numtc;
446 /* DCB Feature Enable */
447 unsigned int dcben;
448 /* IEEE 1588 High Word Register Enable */
449 unsigned int advthword;
450 /* PTP Offload Enable */
451 unsigned int ptoen;
452 /* One-Step Timestamping Enable */
453 unsigned int osten;
454 /* Priority-Based Flow Control Enable */
455 unsigned int pfcen;
456 /* Alternate (enhanced) DESC mode */
457 unsigned int enh_desc;
458 /* TX and RX FIFO sizes */
459 unsigned int tx_fifo_size;
460 unsigned int rx_fifo_size;
461 /* Automotive Safety Package */
462 unsigned int asp;
463 /* RX Parser */
464 unsigned int frpsel;
465 unsigned int frpbs;
466 unsigned int frpes;
467 unsigned int addr64;
468 unsigned int host_dma_width;
469 unsigned int rssen;
470 unsigned int vlhash;
471 unsigned int sphen;
472 unsigned int vlins;
473 unsigned int dvlan;
474 unsigned int l3l4fnum;
475 unsigned int arpoffsel;
476 /* One Step for PTP over UDP/IP Feature Enable */
477 unsigned int pou_ost_en;
478 /* Tx Timestamp FIFO Depth */
479 unsigned int ttsfd;
480 /* Queue/Channel-Based VLAN tag insertion on Tx */
481 unsigned int cbtisel;
482 /* Supported Parallel Instruction Processor Engines */
483 unsigned int frppipe_num;
484 /* Number of Extended VLAN Tag Filters */
485 unsigned int nrvf_num;
486 /* TSN Features */
487 unsigned int estwid;
488 unsigned int estdep;
489 unsigned int estsel;
490 unsigned int fpesel;
491 unsigned int tbssel;
492 /* Number of DMA channels enabled for TBS */
493 unsigned int tbs_ch_num;
494 /* Per-Stream Filtering Enable */
495 unsigned int sgfsel;
496 /* Numbers of Auxiliary Snapshot Inputs */
497 unsigned int aux_snapshot_n;
498 /* Timestamp System Time Source */
499 unsigned int tssrc;
500 /* Enhanced DMA Enable */
501 unsigned int edma;
502 /* Different Descriptor Cache Enable */
503 unsigned int ediffc;
504 /* VxLAN/NVGRE Enable */
505 unsigned int vxn;
506 /* Debug Memory Interface Enable */
507 unsigned int dbgmem;
508 /* Number of Policing Counters */
509 unsigned int pcsel;
510};
511
512/* RX Buffer size must be multiple of 4/8/16 bytes */
513#define BUF_SIZE_16KiB 16368
514#define BUF_SIZE_8KiB 8188
515#define BUF_SIZE_4KiB 4096
516#define BUF_SIZE_2KiB 2048
517
518/* Power Down and WOL */
519#define PMT_NOT_SUPPORTED 0
520#define PMT_SUPPORTED 1
521
522/* Common MAC defines */
523#define MAC_CTRL_REG 0x00000000 /* MAC Control */
524#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
525#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
526
527/* Default LPI timers */
528#define STMMAC_DEFAULT_LIT_LS 0x3E8
529#define STMMAC_DEFAULT_TWT_LS 0x1E
530#define STMMAC_ET_MAX 0xFFFFF
531
532#define STMMAC_CHAIN_MODE 0x1
533#define STMMAC_RING_MODE 0x2
534
535#define JUMBO_LEN 9000
536
537/* Receive Side Scaling */
538#define STMMAC_RSS_HASH_KEY_SIZE 40
539#define STMMAC_RSS_MAX_TABLE_SIZE 256
540
541/* VLAN */
542#define STMMAC_VLAN_NONE 0x0
543#define STMMAC_VLAN_REMOVE 0x1
544#define STMMAC_VLAN_INSERT 0x2
545#define STMMAC_VLAN_REPLACE 0x3
546
547extern const struct stmmac_desc_ops enh_desc_ops;
548extern const struct stmmac_desc_ops ndesc_ops;
549
550struct mac_device_info;
551
552extern const struct stmmac_hwtimestamp stmmac_ptp;
553extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
554
555struct mac_link {
556 u32 caps;
557 u32 speed_mask;
558 u32 speed10;
559 u32 speed100;
560 u32 speed1000;
561 u32 speed2500;
562 u32 duplex;
563 struct {
564 u32 speed2500;
565 u32 speed5000;
566 u32 speed10000;
567 } xgmii;
568 struct {
569 u32 speed25000;
570 u32 speed40000;
571 u32 speed50000;
572 u32 speed100000;
573 } xlgmii;
574};
575
576struct mii_regs {
577 unsigned int addr; /* MII Address */
578 unsigned int data; /* MII Data */
579 unsigned int addr_shift; /* MII address shift */
580 unsigned int reg_shift; /* MII reg shift */
581 unsigned int addr_mask; /* MII address mask */
582 unsigned int reg_mask; /* MII reg mask */
583 unsigned int clk_csr_shift;
584 unsigned int clk_csr_mask;
585};
586
587struct mac_device_info {
588 const struct stmmac_ops *mac;
589 const struct stmmac_desc_ops *desc;
590 const struct stmmac_dma_ops *dma;
591 const struct stmmac_mode_ops *mode;
592 const struct stmmac_hwtimestamp *ptp;
593 const struct stmmac_tc_ops *tc;
594 const struct stmmac_mmc_ops *mmc;
595 const struct stmmac_est_ops *est;
596 struct dw_xpcs *xpcs;
597 struct phylink_pcs *lynx_pcs; /* Lynx external PCS */
598 struct mii_regs mii; /* MII register Addresses */
599 struct mac_link link;
600 void __iomem *pcsr; /* vpointer to device CSRs */
601 unsigned int multicast_filter_bins;
602 unsigned int unicast_filter_entries;
603 unsigned int mcast_bits_log2;
604 unsigned int rx_csum;
605 unsigned int pcs;
606 unsigned int pmt;
607 unsigned int ps;
608 unsigned int xlgmac;
609 unsigned int num_vlan;
610 u32 vlan_filter[32];
611 bool vlan_fail_q_en;
612 u8 vlan_fail_q;
613 bool hw_vlan_en;
614};
615
616struct stmmac_rx_routing {
617 u32 reg_mask;
618 u32 reg_shift;
619};
620
621int dwmac100_setup(struct stmmac_priv *priv);
622int dwmac1000_setup(struct stmmac_priv *priv);
623int dwmac4_setup(struct stmmac_priv *priv);
624int dwxgmac2_setup(struct stmmac_priv *priv);
625int dwxlgmac2_setup(struct stmmac_priv *priv);
626
627void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
628 unsigned int high, unsigned int low);
629void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
630 unsigned int high, unsigned int low);
631void stmmac_set_mac(void __iomem *ioaddr, bool enable);
632
633void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
634 unsigned int high, unsigned int low);
635void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
636 unsigned int high, unsigned int low);
637void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
638
639void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
640
641extern const struct stmmac_mode_ops ring_mode_ops;
642extern const struct stmmac_mode_ops chain_mode_ops;
643extern const struct stmmac_desc_ops dwmac4_desc_ops;
644
645#endif /* __COMMON_H__ */