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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * hypersparc.S: High speed Hypersparc mmu/cache operations.
4 *
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#include <asm/ptrace.h>
9#include <asm/psr.h>
10#include <asm/asm-offsets.h>
11#include <asm/asi.h>
12#include <asm/page.h>
13#include <asm/pgtsrmmu.h>
14#include <linux/init.h>
15
16 .text
17 .align 4
18
19 .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
20 .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
21 .globl hypersparc_flush_page_to_ram
22 .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
23 .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
24 .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
25
26hypersparc_flush_cache_all:
27 WINDOW_FLUSH(%g4, %g5)
28 sethi %hi(vac_cache_size), %g4
29 ld [%g4 + %lo(vac_cache_size)], %g5
30 sethi %hi(vac_line_size), %g1
31 ld [%g1 + %lo(vac_line_size)], %g2
321:
33 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
34 bne 1b
35 sta %g0, [%g5] ASI_M_FLUSH_CTX
36 retl
37 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
38
39 /* We expand the window flush to get maximum performance. */
40hypersparc_flush_cache_mm:
41#ifndef CONFIG_SMP
42 ld [%o0 + AOFF_mm_context], %g1
43 cmp %g1, -1
44 be hypersparc_flush_cache_mm_out
45#endif
46 WINDOW_FLUSH(%g4, %g5)
47
48 sethi %hi(vac_line_size), %g1
49 ld [%g1 + %lo(vac_line_size)], %o1
50 sethi %hi(vac_cache_size), %g2
51 ld [%g2 + %lo(vac_cache_size)], %o0
52 add %o1, %o1, %g1
53 add %o1, %g1, %g2
54 add %o1, %g2, %g3
55 add %o1, %g3, %g4
56 add %o1, %g4, %g5
57 add %o1, %g5, %o4
58 add %o1, %o4, %o5
59
60 /* BLAMMO! */
611:
62 subcc %o0, %o5, %o0 ! hyper_flush_cache_user
63 sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
64 sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
65 sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
66 sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
67 sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
68 sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
69 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
70 bne 1b
71 sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
72hypersparc_flush_cache_mm_out:
73 retl
74 nop
75
76 /* The things we do for performance... */
77hypersparc_flush_cache_range:
78 ld [%o0 + VMA_VM_MM], %o0
79#ifndef CONFIG_SMP
80 ld [%o0 + AOFF_mm_context], %g1
81 cmp %g1, -1
82 be hypersparc_flush_cache_range_out
83#endif
84 WINDOW_FLUSH(%g4, %g5)
85
86 sethi %hi(vac_line_size), %g1
87 ld [%g1 + %lo(vac_line_size)], %o4
88 sethi %hi(vac_cache_size), %g2
89 ld [%g2 + %lo(vac_cache_size)], %o3
90
91 /* Here comes the fun part... */
92 add %o2, (PAGE_SIZE - 1), %o2
93 andn %o1, (PAGE_SIZE - 1), %o1
94 add %o4, %o4, %o5
95 andn %o2, (PAGE_SIZE - 1), %o2
96 add %o4, %o5, %g1
97 sub %o2, %o1, %g4
98 add %o4, %g1, %g2
99 sll %o3, 2, %g5
100 add %o4, %g2, %g3
101 cmp %g4, %g5
102 add %o4, %g3, %g4
103 blu 0f
104 add %o4, %g4, %g5
105 add %o4, %g5, %g7
106
107 /* Flush entire user space, believe it or not this is quicker
108 * than page at a time flushings for range > (cache_size<<2).
109 */
1101:
111 subcc %o3, %g7, %o3
112 sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
113 sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
114 sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
115 sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
116 sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
117 sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
118 sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
119 bne 1b
120 sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
121 retl
122 nop
123
124 /* Below our threshold, flush one page at a time. */
1250:
126 ld [%o0 + AOFF_mm_context], %o0
127 mov SRMMU_CTX_REG, %g7
128 lda [%g7] ASI_M_MMUREGS, %o3
129 sta %o0, [%g7] ASI_M_MMUREGS
130 add %o2, -PAGE_SIZE, %o0
1311:
132 or %o0, 0x400, %g7
133 lda [%g7] ASI_M_FLUSH_PROBE, %g7
134 orcc %g7, 0, %g0
135 be,a 3f
136 mov %o0, %o2
137 add %o4, %g5, %g7
1382:
139 sub %o2, %g7, %o2
140 sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
141 sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
142 sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
143 sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
144 sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
145 sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
146 andcc %o2, 0xffc, %g0
147 sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
148 bne 2b
149 sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
1503:
151 cmp %o2, %o1
152 bne 1b
153 add %o2, -PAGE_SIZE, %o0
154 mov SRMMU_FAULT_STATUS, %g5
155 lda [%g5] ASI_M_MMUREGS, %g0
156 mov SRMMU_CTX_REG, %g7
157 sta %o3, [%g7] ASI_M_MMUREGS
158hypersparc_flush_cache_range_out:
159 retl
160 nop
161
162 /* HyperSparc requires a valid mapping where we are about to flush
163 * in order to check for a physical tag match during the flush.
164 */
165 /* Verified, my ass... */
166hypersparc_flush_cache_page:
167 ld [%o0 + VMA_VM_MM], %o0
168 ld [%o0 + AOFF_mm_context], %g2
169#ifndef CONFIG_SMP
170 cmp %g2, -1
171 be hypersparc_flush_cache_page_out
172#endif
173 WINDOW_FLUSH(%g4, %g5)
174
175 sethi %hi(vac_line_size), %g1
176 ld [%g1 + %lo(vac_line_size)], %o4
177 mov SRMMU_CTX_REG, %o3
178 andn %o1, (PAGE_SIZE - 1), %o1
179 lda [%o3] ASI_M_MMUREGS, %o2
180 sta %g2, [%o3] ASI_M_MMUREGS
181 or %o1, 0x400, %o5
182 lda [%o5] ASI_M_FLUSH_PROBE, %g1
183 orcc %g0, %g1, %g0
184 be 2f
185 add %o4, %o4, %o5
186 sub %o1, -PAGE_SIZE, %o1
187 add %o4, %o5, %g1
188 add %o4, %g1, %g2
189 add %o4, %g2, %g3
190 add %o4, %g3, %g4
191 add %o4, %g4, %g5
192 add %o4, %g5, %g7
193
194 /* BLAMMO! */
1951:
196 sub %o1, %g7, %o1
197 sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
198 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
203 andcc %o1, 0xffc, %g0
204 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
205 bne 1b
206 sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
2072:
208 mov SRMMU_FAULT_STATUS, %g7
209 mov SRMMU_CTX_REG, %g4
210 lda [%g7] ASI_M_MMUREGS, %g0
211 sta %o2, [%g4] ASI_M_MMUREGS
212hypersparc_flush_cache_page_out:
213 retl
214 nop
215
216hypersparc_flush_sig_insns:
217 flush %o1
218 retl
219 flush %o1 + 4
220
221 /* HyperSparc is copy-back. */
222hypersparc_flush_page_to_ram:
223 sethi %hi(vac_line_size), %g1
224 ld [%g1 + %lo(vac_line_size)], %o4
225 andn %o0, (PAGE_SIZE - 1), %o0
226 add %o4, %o4, %o5
227 or %o0, 0x400, %g7
228 lda [%g7] ASI_M_FLUSH_PROBE, %g5
229 add %o4, %o5, %g1
230 orcc %g5, 0, %g0
231 be 2f
232 add %o4, %g1, %g2
233 add %o4, %g2, %g3
234 sub %o0, -PAGE_SIZE, %o0
235 add %o4, %g3, %g4
236 add %o4, %g4, %g5
237 add %o4, %g5, %g7
238
239 /* BLAMMO! */
2401:
241 sub %o0, %g7, %o0
242 sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
243 sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
244 sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
245 sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
246 sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
247 sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
248 andcc %o0, 0xffc, %g0
249 sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
250 bne 1b
251 sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
2522:
253 mov SRMMU_FAULT_STATUS, %g1
254 retl
255 lda [%g1] ASI_M_MMUREGS, %g0
256
257 /* HyperSparc is IO cache coherent. */
258hypersparc_flush_page_for_dma:
259 retl
260 nop
261
262 /* It was noted that at boot time a TLB flush all in a delay slot
263 * can deliver an illegal instruction to the processor if the timing
264 * is just right...
265 */
266hypersparc_flush_tlb_all:
267 mov 0x400, %g1
268 sta %g0, [%g1] ASI_M_FLUSH_PROBE
269 retl
270 nop
271
272hypersparc_flush_tlb_mm:
273 mov SRMMU_CTX_REG, %g1
274 ld [%o0 + AOFF_mm_context], %o1
275 lda [%g1] ASI_M_MMUREGS, %g5
276#ifndef CONFIG_SMP
277 cmp %o1, -1
278 be hypersparc_flush_tlb_mm_out
279#endif
280 mov 0x300, %g2
281 sta %o1, [%g1] ASI_M_MMUREGS
282 sta %g0, [%g2] ASI_M_FLUSH_PROBE
283hypersparc_flush_tlb_mm_out:
284 retl
285 sta %g5, [%g1] ASI_M_MMUREGS
286
287hypersparc_flush_tlb_range:
288 ld [%o0 + VMA_VM_MM], %o0
289 mov SRMMU_CTX_REG, %g1
290 ld [%o0 + AOFF_mm_context], %o3
291 lda [%g1] ASI_M_MMUREGS, %g5
292#ifndef CONFIG_SMP
293 cmp %o3, -1
294 be hypersparc_flush_tlb_range_out
295#endif
296 sethi %hi(~((1 << SRMMU_PGDIR_SHIFT) - 1)), %o4
297 sta %o3, [%g1] ASI_M_MMUREGS
298 and %o1, %o4, %o1
299 add %o1, 0x200, %o1
300 sta %g0, [%o1] ASI_M_FLUSH_PROBE
3011:
302 sub %o1, %o4, %o1
303 cmp %o1, %o2
304 blu,a 1b
305 sta %g0, [%o1] ASI_M_FLUSH_PROBE
306hypersparc_flush_tlb_range_out:
307 retl
308 sta %g5, [%g1] ASI_M_MMUREGS
309
310hypersparc_flush_tlb_page:
311 ld [%o0 + VMA_VM_MM], %o0
312 mov SRMMU_CTX_REG, %g1
313 ld [%o0 + AOFF_mm_context], %o3
314 andn %o1, (PAGE_SIZE - 1), %o1
315#ifndef CONFIG_SMP
316 cmp %o3, -1
317 be hypersparc_flush_tlb_page_out
318#endif
319 lda [%g1] ASI_M_MMUREGS, %g5
320 sta %o3, [%g1] ASI_M_MMUREGS
321 sta %g0, [%o1] ASI_M_FLUSH_PROBE
322hypersparc_flush_tlb_page_out:
323 retl
324 sta %g5, [%g1] ASI_M_MMUREGS
325
326 __INIT
327
328 /* High speed page clear/copy. */
329hypersparc_bzero_1page:
330/* NOTE: This routine has to be shorter than 40insns --jj */
331 clr %g1
332 mov 32, %g2
333 mov 64, %g3
334 mov 96, %g4
335 mov 128, %g5
336 mov 160, %g7
337 mov 192, %o2
338 mov 224, %o3
339 mov 16, %o1
3401:
341 stda %g0, [%o0 + %g0] ASI_M_BFILL
342 stda %g0, [%o0 + %g2] ASI_M_BFILL
343 stda %g0, [%o0 + %g3] ASI_M_BFILL
344 stda %g0, [%o0 + %g4] ASI_M_BFILL
345 stda %g0, [%o0 + %g5] ASI_M_BFILL
346 stda %g0, [%o0 + %g7] ASI_M_BFILL
347 stda %g0, [%o0 + %o2] ASI_M_BFILL
348 stda %g0, [%o0 + %o3] ASI_M_BFILL
349 subcc %o1, 1, %o1
350 bne 1b
351 add %o0, 256, %o0
352
353 retl
354 nop
355
356hypersparc_copy_1page:
357/* NOTE: This routine has to be shorter than 70insns --jj */
358 sub %o1, %o0, %o2 ! difference
359 mov 16, %g1
3601:
361 sta %o0, [%o0 + %o2] ASI_M_BCOPY
362 add %o0, 32, %o0
363 sta %o0, [%o0 + %o2] ASI_M_BCOPY
364 add %o0, 32, %o0
365 sta %o0, [%o0 + %o2] ASI_M_BCOPY
366 add %o0, 32, %o0
367 sta %o0, [%o0 + %o2] ASI_M_BCOPY
368 add %o0, 32, %o0
369 sta %o0, [%o0 + %o2] ASI_M_BCOPY
370 add %o0, 32, %o0
371 sta %o0, [%o0 + %o2] ASI_M_BCOPY
372 add %o0, 32, %o0
373 sta %o0, [%o0 + %o2] ASI_M_BCOPY
374 add %o0, 32, %o0
375 sta %o0, [%o0 + %o2] ASI_M_BCOPY
376 subcc %g1, 1, %g1
377 bne 1b
378 add %o0, 32, %o0
379
380 retl
381 nop
382
383 .globl hypersparc_setup_blockops
384hypersparc_setup_blockops:
385 sethi %hi(bzero_1page), %o0
386 or %o0, %lo(bzero_1page), %o0
387 sethi %hi(hypersparc_bzero_1page), %o1
388 or %o1, %lo(hypersparc_bzero_1page), %o1
389 sethi %hi(hypersparc_copy_1page), %o2
390 or %o2, %lo(hypersparc_copy_1page), %o2
391 ld [%o1], %o4
3921:
393 add %o1, 4, %o1
394 st %o4, [%o0]
395 add %o0, 4, %o0
396 cmp %o1, %o2
397 bne 1b
398 ld [%o1], %o4
399 sethi %hi(__copy_1page), %o0
400 or %o0, %lo(__copy_1page), %o0
401 sethi %hi(hypersparc_setup_blockops), %o2
402 or %o2, %lo(hypersparc_setup_blockops), %o2
403 ld [%o1], %o4
4041:
405 add %o1, 4, %o1
406 st %o4, [%o0]
407 add %o0, 4, %o0
408 cmp %o1, %o2
409 bne 1b
410 ld [%o1], %o4
411 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
412 retl
413 nop
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * hypersparc.S: High speed Hypersparc mmu/cache operations.
4 *
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#include <asm/ptrace.h>
9#include <asm/psr.h>
10#include <asm/asm-offsets.h>
11#include <asm/asi.h>
12#include <asm/page.h>
13#include <asm/pgtable.h>
14#include <asm/pgtsrmmu.h>
15#include <linux/init.h>
16
17 .text
18 .align 4
19
20 .globl hypersparc_flush_cache_all, hypersparc_flush_cache_mm
21 .globl hypersparc_flush_cache_range, hypersparc_flush_cache_page
22 .globl hypersparc_flush_page_to_ram
23 .globl hypersparc_flush_page_for_dma, hypersparc_flush_sig_insns
24 .globl hypersparc_flush_tlb_all, hypersparc_flush_tlb_mm
25 .globl hypersparc_flush_tlb_range, hypersparc_flush_tlb_page
26
27hypersparc_flush_cache_all:
28 WINDOW_FLUSH(%g4, %g5)
29 sethi %hi(vac_cache_size), %g4
30 ld [%g4 + %lo(vac_cache_size)], %g5
31 sethi %hi(vac_line_size), %g1
32 ld [%g1 + %lo(vac_line_size)], %g2
331:
34 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
35 bne 1b
36 sta %g0, [%g5] ASI_M_FLUSH_CTX
37 retl
38 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE ! hyper_flush_whole_icache
39
40 /* We expand the window flush to get maximum performance. */
41hypersparc_flush_cache_mm:
42#ifndef CONFIG_SMP
43 ld [%o0 + AOFF_mm_context], %g1
44 cmp %g1, -1
45 be hypersparc_flush_cache_mm_out
46#endif
47 WINDOW_FLUSH(%g4, %g5)
48
49 sethi %hi(vac_line_size), %g1
50 ld [%g1 + %lo(vac_line_size)], %o1
51 sethi %hi(vac_cache_size), %g2
52 ld [%g2 + %lo(vac_cache_size)], %o0
53 add %o1, %o1, %g1
54 add %o1, %g1, %g2
55 add %o1, %g2, %g3
56 add %o1, %g3, %g4
57 add %o1, %g4, %g5
58 add %o1, %g5, %o4
59 add %o1, %o4, %o5
60
61 /* BLAMMO! */
621:
63 subcc %o0, %o5, %o0 ! hyper_flush_cache_user
64 sta %g0, [%o0 + %g0] ASI_M_FLUSH_USER
65 sta %g0, [%o0 + %o1] ASI_M_FLUSH_USER
66 sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER
67 sta %g0, [%o0 + %g2] ASI_M_FLUSH_USER
68 sta %g0, [%o0 + %g3] ASI_M_FLUSH_USER
69 sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
70 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
71 bne 1b
72 sta %g0, [%o0 + %o4] ASI_M_FLUSH_USER
73hypersparc_flush_cache_mm_out:
74 retl
75 nop
76
77 /* The things we do for performance... */
78hypersparc_flush_cache_range:
79 ld [%o0 + VMA_VM_MM], %o0
80#ifndef CONFIG_SMP
81 ld [%o0 + AOFF_mm_context], %g1
82 cmp %g1, -1
83 be hypersparc_flush_cache_range_out
84#endif
85 WINDOW_FLUSH(%g4, %g5)
86
87 sethi %hi(vac_line_size), %g1
88 ld [%g1 + %lo(vac_line_size)], %o4
89 sethi %hi(vac_cache_size), %g2
90 ld [%g2 + %lo(vac_cache_size)], %o3
91
92 /* Here comes the fun part... */
93 add %o2, (PAGE_SIZE - 1), %o2
94 andn %o1, (PAGE_SIZE - 1), %o1
95 add %o4, %o4, %o5
96 andn %o2, (PAGE_SIZE - 1), %o2
97 add %o4, %o5, %g1
98 sub %o2, %o1, %g4
99 add %o4, %g1, %g2
100 sll %o3, 2, %g5
101 add %o4, %g2, %g3
102 cmp %g4, %g5
103 add %o4, %g3, %g4
104 blu 0f
105 add %o4, %g4, %g5
106 add %o4, %g5, %g7
107
108 /* Flush entire user space, believe it or not this is quicker
109 * than page at a time flushings for range > (cache_size<<2).
110 */
1111:
112 subcc %o3, %g7, %o3
113 sta %g0, [%o3 + %g0] ASI_M_FLUSH_USER
114 sta %g0, [%o3 + %o4] ASI_M_FLUSH_USER
115 sta %g0, [%o3 + %o5] ASI_M_FLUSH_USER
116 sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER
117 sta %g0, [%o3 + %g2] ASI_M_FLUSH_USER
118 sta %g0, [%o3 + %g3] ASI_M_FLUSH_USER
119 sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
120 bne 1b
121 sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
122 retl
123 nop
124
125 /* Below our threshold, flush one page at a time. */
1260:
127 ld [%o0 + AOFF_mm_context], %o0
128 mov SRMMU_CTX_REG, %g7
129 lda [%g7] ASI_M_MMUREGS, %o3
130 sta %o0, [%g7] ASI_M_MMUREGS
131 add %o2, -PAGE_SIZE, %o0
1321:
133 or %o0, 0x400, %g7
134 lda [%g7] ASI_M_FLUSH_PROBE, %g7
135 orcc %g7, 0, %g0
136 be,a 3f
137 mov %o0, %o2
138 add %o4, %g5, %g7
1392:
140 sub %o2, %g7, %o2
141 sta %g0, [%o2 + %g0] ASI_M_FLUSH_PAGE
142 sta %g0, [%o2 + %o4] ASI_M_FLUSH_PAGE
143 sta %g0, [%o2 + %o5] ASI_M_FLUSH_PAGE
144 sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE
145 sta %g0, [%o2 + %g2] ASI_M_FLUSH_PAGE
146 sta %g0, [%o2 + %g3] ASI_M_FLUSH_PAGE
147 andcc %o2, 0xffc, %g0
148 sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
149 bne 2b
150 sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
1513:
152 cmp %o2, %o1
153 bne 1b
154 add %o2, -PAGE_SIZE, %o0
155 mov SRMMU_FAULT_STATUS, %g5
156 lda [%g5] ASI_M_MMUREGS, %g0
157 mov SRMMU_CTX_REG, %g7
158 sta %o3, [%g7] ASI_M_MMUREGS
159hypersparc_flush_cache_range_out:
160 retl
161 nop
162
163 /* HyperSparc requires a valid mapping where we are about to flush
164 * in order to check for a physical tag match during the flush.
165 */
166 /* Verified, my ass... */
167hypersparc_flush_cache_page:
168 ld [%o0 + VMA_VM_MM], %o0
169 ld [%o0 + AOFF_mm_context], %g2
170#ifndef CONFIG_SMP
171 cmp %g2, -1
172 be hypersparc_flush_cache_page_out
173#endif
174 WINDOW_FLUSH(%g4, %g5)
175
176 sethi %hi(vac_line_size), %g1
177 ld [%g1 + %lo(vac_line_size)], %o4
178 mov SRMMU_CTX_REG, %o3
179 andn %o1, (PAGE_SIZE - 1), %o1
180 lda [%o3] ASI_M_MMUREGS, %o2
181 sta %g2, [%o3] ASI_M_MMUREGS
182 or %o1, 0x400, %o5
183 lda [%o5] ASI_M_FLUSH_PROBE, %g1
184 orcc %g0, %g1, %g0
185 be 2f
186 add %o4, %o4, %o5
187 sub %o1, -PAGE_SIZE, %o1
188 add %o4, %o5, %g1
189 add %o4, %g1, %g2
190 add %o4, %g2, %g3
191 add %o4, %g3, %g4
192 add %o4, %g4, %g5
193 add %o4, %g5, %g7
194
195 /* BLAMMO! */
1961:
197 sub %o1, %g7, %o1
198 sta %g0, [%o1 + %g0] ASI_M_FLUSH_PAGE
199 sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
200 sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
201 sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE
202 sta %g0, [%o1 + %g2] ASI_M_FLUSH_PAGE
203 sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
204 andcc %o1, 0xffc, %g0
205 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
206 bne 1b
207 sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
2082:
209 mov SRMMU_FAULT_STATUS, %g7
210 mov SRMMU_CTX_REG, %g4
211 lda [%g7] ASI_M_MMUREGS, %g0
212 sta %o2, [%g4] ASI_M_MMUREGS
213hypersparc_flush_cache_page_out:
214 retl
215 nop
216
217hypersparc_flush_sig_insns:
218 flush %o1
219 retl
220 flush %o1 + 4
221
222 /* HyperSparc is copy-back. */
223hypersparc_flush_page_to_ram:
224 sethi %hi(vac_line_size), %g1
225 ld [%g1 + %lo(vac_line_size)], %o4
226 andn %o0, (PAGE_SIZE - 1), %o0
227 add %o4, %o4, %o5
228 or %o0, 0x400, %g7
229 lda [%g7] ASI_M_FLUSH_PROBE, %g5
230 add %o4, %o5, %g1
231 orcc %g5, 0, %g0
232 be 2f
233 add %o4, %g1, %g2
234 add %o4, %g2, %g3
235 sub %o0, -PAGE_SIZE, %o0
236 add %o4, %g3, %g4
237 add %o4, %g4, %g5
238 add %o4, %g5, %g7
239
240 /* BLAMMO! */
2411:
242 sub %o0, %g7, %o0
243 sta %g0, [%o0 + %g0] ASI_M_FLUSH_PAGE
244 sta %g0, [%o0 + %o4] ASI_M_FLUSH_PAGE
245 sta %g0, [%o0 + %o5] ASI_M_FLUSH_PAGE
246 sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE
247 sta %g0, [%o0 + %g2] ASI_M_FLUSH_PAGE
248 sta %g0, [%o0 + %g3] ASI_M_FLUSH_PAGE
249 andcc %o0, 0xffc, %g0
250 sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
251 bne 1b
252 sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
2532:
254 mov SRMMU_FAULT_STATUS, %g1
255 retl
256 lda [%g1] ASI_M_MMUREGS, %g0
257
258 /* HyperSparc is IO cache coherent. */
259hypersparc_flush_page_for_dma:
260 retl
261 nop
262
263 /* It was noted that at boot time a TLB flush all in a delay slot
264 * can deliver an illegal instruction to the processor if the timing
265 * is just right...
266 */
267hypersparc_flush_tlb_all:
268 mov 0x400, %g1
269 sta %g0, [%g1] ASI_M_FLUSH_PROBE
270 retl
271 nop
272
273hypersparc_flush_tlb_mm:
274 mov SRMMU_CTX_REG, %g1
275 ld [%o0 + AOFF_mm_context], %o1
276 lda [%g1] ASI_M_MMUREGS, %g5
277#ifndef CONFIG_SMP
278 cmp %o1, -1
279 be hypersparc_flush_tlb_mm_out
280#endif
281 mov 0x300, %g2
282 sta %o1, [%g1] ASI_M_MMUREGS
283 sta %g0, [%g2] ASI_M_FLUSH_PROBE
284hypersparc_flush_tlb_mm_out:
285 retl
286 sta %g5, [%g1] ASI_M_MMUREGS
287
288hypersparc_flush_tlb_range:
289 ld [%o0 + VMA_VM_MM], %o0
290 mov SRMMU_CTX_REG, %g1
291 ld [%o0 + AOFF_mm_context], %o3
292 lda [%g1] ASI_M_MMUREGS, %g5
293#ifndef CONFIG_SMP
294 cmp %o3, -1
295 be hypersparc_flush_tlb_range_out
296#endif
297 sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
298 sta %o3, [%g1] ASI_M_MMUREGS
299 and %o1, %o4, %o1
300 add %o1, 0x200, %o1
301 sta %g0, [%o1] ASI_M_FLUSH_PROBE
3021:
303 sub %o1, %o4, %o1
304 cmp %o1, %o2
305 blu,a 1b
306 sta %g0, [%o1] ASI_M_FLUSH_PROBE
307hypersparc_flush_tlb_range_out:
308 retl
309 sta %g5, [%g1] ASI_M_MMUREGS
310
311hypersparc_flush_tlb_page:
312 ld [%o0 + VMA_VM_MM], %o0
313 mov SRMMU_CTX_REG, %g1
314 ld [%o0 + AOFF_mm_context], %o3
315 andn %o1, (PAGE_SIZE - 1), %o1
316#ifndef CONFIG_SMP
317 cmp %o3, -1
318 be hypersparc_flush_tlb_page_out
319#endif
320 lda [%g1] ASI_M_MMUREGS, %g5
321 sta %o3, [%g1] ASI_M_MMUREGS
322 sta %g0, [%o1] ASI_M_FLUSH_PROBE
323hypersparc_flush_tlb_page_out:
324 retl
325 sta %g5, [%g1] ASI_M_MMUREGS
326
327 __INIT
328
329 /* High speed page clear/copy. */
330hypersparc_bzero_1page:
331/* NOTE: This routine has to be shorter than 40insns --jj */
332 clr %g1
333 mov 32, %g2
334 mov 64, %g3
335 mov 96, %g4
336 mov 128, %g5
337 mov 160, %g7
338 mov 192, %o2
339 mov 224, %o3
340 mov 16, %o1
3411:
342 stda %g0, [%o0 + %g0] ASI_M_BFILL
343 stda %g0, [%o0 + %g2] ASI_M_BFILL
344 stda %g0, [%o0 + %g3] ASI_M_BFILL
345 stda %g0, [%o0 + %g4] ASI_M_BFILL
346 stda %g0, [%o0 + %g5] ASI_M_BFILL
347 stda %g0, [%o0 + %g7] ASI_M_BFILL
348 stda %g0, [%o0 + %o2] ASI_M_BFILL
349 stda %g0, [%o0 + %o3] ASI_M_BFILL
350 subcc %o1, 1, %o1
351 bne 1b
352 add %o0, 256, %o0
353
354 retl
355 nop
356
357hypersparc_copy_1page:
358/* NOTE: This routine has to be shorter than 70insns --jj */
359 sub %o1, %o0, %o2 ! difference
360 mov 16, %g1
3611:
362 sta %o0, [%o0 + %o2] ASI_M_BCOPY
363 add %o0, 32, %o0
364 sta %o0, [%o0 + %o2] ASI_M_BCOPY
365 add %o0, 32, %o0
366 sta %o0, [%o0 + %o2] ASI_M_BCOPY
367 add %o0, 32, %o0
368 sta %o0, [%o0 + %o2] ASI_M_BCOPY
369 add %o0, 32, %o0
370 sta %o0, [%o0 + %o2] ASI_M_BCOPY
371 add %o0, 32, %o0
372 sta %o0, [%o0 + %o2] ASI_M_BCOPY
373 add %o0, 32, %o0
374 sta %o0, [%o0 + %o2] ASI_M_BCOPY
375 add %o0, 32, %o0
376 sta %o0, [%o0 + %o2] ASI_M_BCOPY
377 subcc %g1, 1, %g1
378 bne 1b
379 add %o0, 32, %o0
380
381 retl
382 nop
383
384 .globl hypersparc_setup_blockops
385hypersparc_setup_blockops:
386 sethi %hi(bzero_1page), %o0
387 or %o0, %lo(bzero_1page), %o0
388 sethi %hi(hypersparc_bzero_1page), %o1
389 or %o1, %lo(hypersparc_bzero_1page), %o1
390 sethi %hi(hypersparc_copy_1page), %o2
391 or %o2, %lo(hypersparc_copy_1page), %o2
392 ld [%o1], %o4
3931:
394 add %o1, 4, %o1
395 st %o4, [%o0]
396 add %o0, 4, %o0
397 cmp %o1, %o2
398 bne 1b
399 ld [%o1], %o4
400 sethi %hi(__copy_1page), %o0
401 or %o0, %lo(__copy_1page), %o0
402 sethi %hi(hypersparc_setup_blockops), %o2
403 or %o2, %lo(hypersparc_setup_blockops), %o2
404 ld [%o1], %o4
4051:
406 add %o1, 4, %o1
407 st %o4, [%o0]
408 add %o0, 4, %o0
409 cmp %o1, %o2
410 bne 1b
411 ld [%o1], %o4
412 sta %g0, [%g0] ASI_M_FLUSH_IWHOLE
413 retl
414 nop