1// SPDX-License-Identifier: GPL-2.0
  2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
  3// Copyright 2018 Google, Inc.
  4
  5#include <dt-bindings/interrupt-controller/arm-gic.h>
  6
  7/ {
  8	#address-cells = <1>;
  9	#size-cells = <1>;
 10	interrupt-parent = <&gic>;
 11
 12	/* external reference clock */
 13	clk_refclk: clk_refclk {
 14		compatible = "fixed-clock";
 15		#clock-cells = <0>;
 16		clock-frequency = <25000000>;
 17		clock-output-names = "refclk";
 18	};
 19
 20	/* external reference clock for cpu. float in normal operation */
 21	clk_sysbypck: clk_sysbypck {
 22		compatible = "fixed-clock";
 23		#clock-cells = <0>;
 24		clock-frequency = <800000000>;
 25		clock-output-names = "sysbypck";
 26	};
 27
 28	/* external reference clock for MC. float in normal operation */
 29	clk_mcbypck: clk_mcbypck {
 30		compatible = "fixed-clock";
 31		#clock-cells = <0>;
 32		clock-frequency = <800000000>;
 33		clock-output-names = "mcbypck";
 34	};
 35
 36	 /* external clock signal rg1refck, supplied by the phy */
 37	clk_rg1refck: clk_rg1refck {
 38		compatible = "fixed-clock";
 39		#clock-cells = <0>;
 40		clock-frequency = <125000000>;
 41		clock-output-names = "clk_rg1refck";
 42	};
 43
 44	 /* external clock signal rg2refck, supplied by the phy */
 45	clk_rg2refck: clk_rg2refck {
 46		compatible = "fixed-clock";
 47		#clock-cells = <0>;
 48		clock-frequency = <125000000>;
 49		clock-output-names = "clk_rg2refck";
 50	};
 51
 52	clk_xin: clk_xin {
 53		compatible = "fixed-clock";
 54		#clock-cells = <0>;
 55		clock-frequency = <50000000>;
 56		clock-output-names = "clk_xin";
 57	};
 58
 59	soc {
 60		#address-cells = <1>;
 61		#size-cells = <1>;
 62		compatible = "simple-bus";
 63		interrupt-parent = <&gic>;
 64		ranges = <0x0 0xf0000000 0x00900000>;
 65
 66		gcr: gcr@800000 {
 67			compatible = "nuvoton,npcm750-gcr", "syscon",
 68				"simple-mfd";
 69			reg = <0x800000 0x1000>;
 70		};
 71
 72		scu: scu@3fe000 {
 73			compatible = "arm,cortex-a9-scu";
 74			reg = <0x3fe000 0x1000>;
 75		};
 76
 77		l2: cache-controller@3fc000 {
 78			compatible = "arm,pl310-cache";
 79			reg = <0x3fc000 0x1000>;
 80			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 81			cache-unified;
 82			cache-level = <2>;
 83			clocks = <&clk 10>;
 84			arm,shared-override;
 85		};
 86
 87		gic: interrupt-controller@3ff000 {
 88			compatible = "arm,cortex-a9-gic";
 89			interrupt-controller;
 90			#interrupt-cells = <3>;
 91			reg = <0x3ff000 0x1000>,
 92				<0x3fe100 0x100>;
 93		};
 94	};
 95
 96	ahb {
 97		#address-cells = <1>;
 98		#size-cells = <1>;
 99		compatible = "simple-bus";
100		interrupt-parent = <&gic>;
101		ranges;
102
103		clk: clock-controller@f0801000 {
104			compatible = "nuvoton,npcm750-clk", "syscon";
105			#clock-cells = <1>;
106			clock-controller;
107			reg = <0xf0801000 0x1000>;
108			clock-names = "refclk", "sysbypck", "mcbypck";
109			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
110		};
111
112		apb {
113			#address-cells = <1>;
114			#size-cells = <1>;
115			compatible = "simple-bus";
116			interrupt-parent = <&gic>;
117			ranges = <0x0 0xf0000000 0x00300000>;
118
119			timer0: timer@8000 {
120				compatible = "nuvoton,npcm750-timer";
121				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
122				reg = <0x8000 0x50>;
123				clocks = <&clk 5>;
124			};
125
126			watchdog0: watchdog@801C {
127				compatible = "nuvoton,npcm750-wdt";
128				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
129				reg = <0x801C 0x4>;
130				status = "disabled";
131				clocks = <&clk 5>;
132			};
133
134			watchdog1: watchdog@901C {
135				compatible = "nuvoton,npcm750-wdt";
136				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
137				reg = <0x901C 0x4>;
138				status = "disabled";
139				clocks = <&clk 5>;
140			};
141
142			watchdog2: watchdog@a01C {
143				compatible = "nuvoton,npcm750-wdt";
144				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
145				reg = <0xa01C 0x4>;
146				status = "disabled";
147				clocks = <&clk 5>;
148			};
149
150			serial0: serial@1000 {
151				compatible = "nuvoton,npcm750-uart";
152				reg = <0x1000 0x1000>;
153				clocks = <&clk 6>;
154				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
155				reg-shift = <2>;
156				status = "disabled";
157			};
158
159			serial1: serial@2000 {
160				compatible = "nuvoton,npcm750-uart";
161				reg = <0x2000 0x1000>;
162				clocks = <&clk 6>;
163				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
164				reg-shift = <2>;
165				status = "disabled";
166			};
167
168			serial2: serial@3000 {
169				compatible = "nuvoton,npcm750-uart";
170				reg = <0x3000 0x1000>;
171				clocks = <&clk 6>;
172				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
173				reg-shift = <2>;
174				status = "disabled";
175			};
176
177			serial3: serial@4000 {
178				compatible = "nuvoton,npcm750-uart";
179				reg = <0x4000 0x1000>;
180				clocks = <&clk 6>;
181				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
182				reg-shift = <2>;
183				status = "disabled";
184			};
185		};
186	};
187};