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1/*
2 * Copyright 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/clock/meson8b-clkc.h>
48#include <dt-bindings/gpio/meson8b-gpio.h>
49#include <dt-bindings/reset/amlogic,meson8b-reset.h>
50#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
51#include "meson.dtsi"
52
53/ {
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
62 reg = <0x200>;
63 enable-method = "amlogic,meson8b-smp";
64 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
65 };
66
67 cpu@201 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a5";
70 next-level-cache = <&L2>;
71 reg = <0x201>;
72 enable-method = "amlogic,meson8b-smp";
73 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
74 };
75
76 cpu@202 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a5";
79 next-level-cache = <&L2>;
80 reg = <0x202>;
81 enable-method = "amlogic,meson8b-smp";
82 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
83 };
84
85 cpu@203 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a5";
88 next-level-cache = <&L2>;
89 reg = <0x203>;
90 enable-method = "amlogic,meson8b-smp";
91 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
92 };
93 };
94
95 reserved-memory {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99
100 /* 2 MiB reserved for Hardware ROM Firmware? */
101 hwrom@0 {
102 reg = <0x0 0x200000>;
103 no-map;
104 };
105 };
106
107 scu@c4300000 {
108 compatible = "arm,cortex-a5-scu";
109 reg = <0xc4300000 0x100>;
110 };
111}; /* end of / */
112
113&aobus {
114 pmu: pmu@e0 {
115 compatible = "amlogic,meson8b-pmu", "syscon";
116 reg = <0xe0 0x18>;
117 };
118
119 pinctrl_aobus: pinctrl@84 {
120 compatible = "amlogic,meson8b-aobus-pinctrl";
121 reg = <0x84 0xc>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges;
125
126 gpio_ao: ao-bank@14 {
127 reg = <0x14 0x4>,
128 <0x2c 0x4>,
129 <0x24 0x8>;
130 reg-names = "mux", "pull", "gpio";
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinctrl_aobus 0 0 16>;
134 };
135
136 uart_ao_a_pins: uart_ao_a {
137 mux {
138 groups = "uart_tx_ao_a", "uart_rx_ao_a";
139 function = "uart_ao";
140 };
141 };
142 };
143};
144
145&cbus {
146 clkc: clock-controller@4000 {
147 #clock-cells = <1>;
148 #reset-cells = <1>;
149 compatible = "amlogic,meson8b-clkc";
150 reg = <0x8000 0x4>, <0x4000 0x460>;
151 };
152
153 reset: reset-controller@4404 {
154 compatible = "amlogic,meson8b-reset";
155 reg = <0x4404 0x9c>;
156 #reset-cells = <1>;
157 };
158
159 analog_top: analog-top@81a8 {
160 compatible = "amlogic,meson8b-analog-top", "syscon";
161 reg = <0x81a8 0x14>;
162 };
163
164 pwm_ef: pwm@86c0 {
165 compatible = "amlogic,meson8b-pwm";
166 reg = <0x86c0 0x10>;
167 #pwm-cells = <3>;
168 status = "disabled";
169 };
170
171 pinctrl_cbus: pinctrl@9880 {
172 compatible = "amlogic,meson8b-cbus-pinctrl";
173 reg = <0x9880 0x10>;
174 #address-cells = <1>;
175 #size-cells = <1>;
176 ranges;
177
178 gpio: banks@80b0 {
179 reg = <0x80b0 0x28>,
180 <0x80e8 0x18>,
181 <0x8120 0x18>,
182 <0x8030 0x38>;
183 reg-names = "mux", "pull", "pull-enable", "gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
186 gpio-ranges = <&pinctrl_cbus 0 0 83>;
187 };
188
189 eth_rgmii_pins: eth-rgmii {
190 mux {
191 groups = "eth_tx_clk",
192 "eth_tx_en",
193 "eth_txd1_0",
194 "eth_txd1_1",
195 "eth_txd0_0",
196 "eth_txd0_1",
197 "eth_rx_clk",
198 "eth_rx_dv",
199 "eth_rxd1",
200 "eth_rxd0",
201 "eth_mdio_en",
202 "eth_mdc",
203 "eth_ref_clk",
204 "eth_txd2",
205 "eth_txd3";
206 function = "ethernet";
207 };
208 };
209
210 sd_b_pins: sd-b {
211 mux {
212 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
213 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
214 function = "sd_b";
215 };
216 };
217 };
218};
219
220&ahb_sram {
221 smp-sram@1ff80 {
222 compatible = "amlogic,meson8b-smp-sram";
223 reg = <0x1ff80 0x8>;
224 };
225};
226
227
228&efuse {
229 compatible = "amlogic,meson8b-efuse";
230 clocks = <&clkc CLKID_EFUSE>;
231 clock-names = "core";
232};
233
234ðmac {
235 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
236
237 reg = <0xc9410000 0x10000
238 0xc1108140 0x4>;
239
240 clocks = <&clkc CLKID_ETH>,
241 <&clkc CLKID_MPLL2>,
242 <&clkc CLKID_MPLL2>;
243 clock-names = "stmmaceth", "clkin0", "clkin1";
244
245 resets = <&reset RESET_ETHERNET>;
246 reset-names = "stmmaceth";
247};
248
249&gpio_intc {
250 compatible = "amlogic,meson-gpio-intc",
251 "amlogic,meson8b-gpio-intc";
252 status = "okay";
253};
254
255&hwrng {
256 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
257 clocks = <&clkc CLKID_RNG0>;
258 clock-names = "core";
259};
260
261&i2c_AO {
262 clocks = <&clkc CLKID_CLK81>;
263};
264
265&i2c_A {
266 clocks = <&clkc CLKID_I2C>;
267};
268
269&i2c_B {
270 clocks = <&clkc CLKID_I2C>;
271};
272
273&L2 {
274 arm,data-latency = <3 3 3>;
275 arm,tag-latency = <2 2 2>;
276 arm,filter-ranges = <0x100000 0xc0000000>;
277 prefetch-data = <1>;
278 prefetch-instr = <1>;
279 arm,shared-override;
280};
281
282&pwm_ab {
283 compatible = "amlogic,meson8b-pwm";
284};
285
286&pwm_cd {
287 compatible = "amlogic,meson8b-pwm";
288};
289
290&saradc {
291 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
292 clocks = <&clkc CLKID_XTAL>,
293 <&clkc CLKID_SAR_ADC>;
294 clock-names = "clkin", "core";
295};
296
297&sdio {
298 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
299 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
300 clock-names = "core", "clkin";
301};
302
303&uart_AO {
304 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
305 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
306 clock-names = "baud", "xtal", "pclk";
307};
308
309&uart_A {
310 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
311 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
312 clock-names = "baud", "xtal", "pclk";
313};
314
315&uart_B {
316 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
317 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
318 clock-names = "baud", "xtal", "pclk";
319};
320
321&uart_C {
322 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
323 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
324 clock-names = "baud", "xtal", "pclk";
325};
326
327&usb0 {
328 compatible = "amlogic,meson8b-usb", "snps,dwc2";
329 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
330 clock-names = "otg";
331};
332
333&usb1 {
334 compatible = "amlogic,meson8b-usb", "snps,dwc2";
335 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
336 clock-names = "otg";
337};
338
339&usb0_phy {
340 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
341 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
342 clock-names = "usb_general", "usb";
343 resets = <&reset RESET_USB_OTG>;
344};
345
346&usb1_phy {
347 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
348 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
349 clock-names = "usb_general", "usb";
350 resets = <&reset RESET_USB_OTG>;
351};
352
353&wdt {
354 compatible = "amlogic,meson8b-wdt";
355};