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1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 nand = &gpmi;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 leds {
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_leds>;
32
33 led0: user1 {
34 label = "user1";
35 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39
40 led1: user2 {
41 label = "user2";
42 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
43 default-state = "off";
44 };
45 };
46
47 memory@10000000 {
48 reg = <0x10000000 0x20000000>;
49 };
50
51 pps {
52 compatible = "pps-gpio";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_pps>;
55 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
56 status = "okay";
57 };
58
59 reg_3p3v: regulator-3p3v {
60 compatible = "regulator-fixed";
61 regulator-name = "3P3V";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 regulator-always-on;
65 };
66
67 reg_5p0v: regulator-5p0v {
68 compatible = "regulator-fixed";
69 regulator-name = "5P0V";
70 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <5000000>;
72 regulator-always-on;
73 };
74
75 reg_usb_otg_vbus: regulator-usb-otg-vbus {
76 compatible = "regulator-fixed";
77 regulator-name = "usb_otg_vbus";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
81 enable-active-high;
82 };
83};
84
85&fec {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_enet>;
88 phy-mode = "rgmii-id";
89 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
90 status = "okay";
91};
92
93&gpmi {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_gpmi_nand>;
96 status = "okay";
97};
98
99&hdmi {
100 ddc-i2c-bus = <&i2c3>;
101 status = "okay";
102};
103
104&i2c1 {
105 clock-frequency = <100000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c1>;
108 status = "okay";
109
110 eeprom1: eeprom@50 {
111 compatible = "atmel,24c02";
112 reg = <0x50>;
113 pagesize = <16>;
114 };
115
116 eeprom2: eeprom@51 {
117 compatible = "atmel,24c02";
118 reg = <0x51>;
119 pagesize = <16>;
120 };
121
122 eeprom3: eeprom@52 {
123 compatible = "atmel,24c02";
124 reg = <0x52>;
125 pagesize = <16>;
126 };
127
128 eeprom4: eeprom@53 {
129 compatible = "atmel,24c02";
130 reg = <0x53>;
131 pagesize = <16>;
132 };
133
134 gpio: pca9555@23 {
135 compatible = "nxp,pca9555";
136 reg = <0x23>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 rtc: ds1672@68 {
142 compatible = "dallas,ds1672";
143 reg = <0x68>;
144 };
145};
146
147&i2c2 {
148 clock-frequency = <100000>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_i2c2>;
151 status = "okay";
152
153 ltc3676: pmic@3c {
154 compatible = "lltc,ltc3676";
155 reg = <0x3c>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_pmic>;
158 interrupt-parent = <&gpio1>;
159 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
160
161 regulators {
162 /* VDD_SOC (1+R1/R2 = 1.635) */
163 reg_vdd_soc: sw1 {
164 regulator-name = "vddsoc";
165 regulator-min-microvolt = <674400>;
166 regulator-max-microvolt = <1308000>;
167 lltc,fb-voltage-divider = <127000 200000>;
168 regulator-ramp-delay = <7000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
174 reg_1p8v: sw2 {
175 regulator-name = "vdd1p8";
176 regulator-min-microvolt = <1033310>;
177 regulator-max-microvolt = <2004000>;
178 lltc,fb-voltage-divider = <301000 200000>;
179 regulator-ramp-delay = <7000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 /* VDD_ARM (1+R1/R2 = 1.635) */
185 reg_vdd_arm: sw3 {
186 regulator-name = "vddarm";
187 regulator-min-microvolt = <674400>;
188 regulator-max-microvolt = <1308000>;
189 lltc,fb-voltage-divider = <127000 200000>;
190 regulator-ramp-delay = <7000>;
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 /* VDD_DDR (1+R1/R2 = 2.105) */
196 reg_vdd_ddr: sw4 {
197 regulator-name = "vddddr";
198 regulator-min-microvolt = <868310>;
199 regulator-max-microvolt = <1684000>;
200 lltc,fb-voltage-divider = <221000 200000>;
201 regulator-ramp-delay = <7000>;
202 regulator-boot-on;
203 regulator-always-on;
204 };
205
206 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
207 reg_2p5v: ldo2 {
208 regulator-name = "vdd2p5";
209 regulator-min-microvolt = <2490375>;
210 regulator-max-microvolt = <2490375>;
211 lltc,fb-voltage-divider = <487000 200000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215
216 /* VDD_HIGH (1+R1/R2 = 4.17) */
217 reg_3p0v: ldo4 {
218 regulator-name = "vdd3p0";
219 regulator-min-microvolt = <3023250>;
220 regulator-max-microvolt = <3023250>;
221 lltc,fb-voltage-divider = <634000 200000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225 };
226 };
227};
228
229&i2c3 {
230 clock-frequency = <100000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c3>;
233 status = "okay";
234
235 adv7180: camera@20 {
236 compatible = "adi,adv7180";
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_adv7180>;
239 reg = <0x20>;
240 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
241 interrupt-parent = <&gpio5>;
242 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
243
244 port {
245 adv7180_to_ipu1_csi0_mux: endpoint {
246 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
247 bus-width = <8>;
248 };
249 };
250 };
251};
252
253&ipu1_csi0_from_ipu1_csi0_mux {
254 bus-width = <8>;
255};
256
257&ipu1_csi0_mux_from_parallel_sensor {
258 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
259 bus-width = <8>;
260};
261
262&ipu1_csi0 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_ipu1_csi0>;
265};
266
267&pcie {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_pcie>;
270 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
271 status = "okay";
272};
273
274&pwm2 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
277 status = "disabled";
278};
279
280&pwm3 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
283 status = "disabled";
284};
285
286&pwm4 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
289 status = "disabled";
290};
291
292&uart1 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart1>;
295 status = "okay";
296};
297
298&uart2 {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_uart2>;
301 status = "okay";
302};
303
304&uart3 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_uart3>;
307 status = "okay";
308};
309
310&uart5 {
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_uart5>;
313 status = "okay";
314};
315
316&usbotg {
317 vbus-supply = <®_usb_otg_vbus>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usbotg>;
320 disable-over-current;
321 status = "okay";
322};
323
324&usbh1 {
325 status = "okay";
326};
327
328&wdog1 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_wdog>;
331 fsl,ext-reset-output;
332};
333
334&iomuxc {
335 pinctrl_adv7180: adv7180grp {
336 fsl,pins = <
337 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
338 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
339 >;
340 };
341
342 pinctrl_enet: enetgrp {
343 fsl,pins = <
344 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
345 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
346 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
347 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
348 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
349 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
350 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
351 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
352 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
353 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
354 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
355 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
356 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
357 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
358 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
359 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
360 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
361 >;
362 };
363
364 pinctrl_gpio_leds: gpioledsgrp {
365 fsl,pins = <
366 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
367 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
368 >;
369 };
370
371 pinctrl_gpmi_nand: gpminandgrp {
372 fsl,pins = <
373 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
374 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
375 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
376 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
377 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
378 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
379 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
380 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
381 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
382 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
383 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
384 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
385 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
386 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
387 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
388 >;
389 };
390
391 pinctrl_i2c1: i2c1grp {
392 fsl,pins = <
393 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
394 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
395 >;
396 };
397
398 pinctrl_i2c2: i2c2grp {
399 fsl,pins = <
400 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
401 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
402 >;
403 };
404
405 pinctrl_i2c3: i2c3grp {
406 fsl,pins = <
407 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
408 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
409 >;
410 };
411
412 pinctrl_ipu1_csi0: ipu1csi0grp {
413 fsl,pins = <
414 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
415 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
416 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
417 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
418 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
419 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
420 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
421 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
422 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
423 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
424 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
425 >;
426 };
427
428 pinctrl_pcie: pciegrp {
429 fsl,pins = <
430 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
431 >;
432 };
433
434 pinctrl_pmic: pmicgrp {
435 fsl,pins = <
436 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
437 >;
438 };
439
440 pinctrl_pps: ppsgrp {
441 fsl,pins = <
442 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
443 >;
444 };
445
446 pinctrl_pwm2: pwm2grp {
447 fsl,pins = <
448 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
449 >;
450 };
451
452 pinctrl_pwm3: pwm3grp {
453 fsl,pins = <
454 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
455 >;
456 };
457
458 pinctrl_pwm4: pwm4grp {
459 fsl,pins = <
460 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
461 >;
462 };
463
464 pinctrl_uart1: uart1grp {
465 fsl,pins = <
466 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
467 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
468 >;
469 };
470
471 pinctrl_uart2: uart2grp {
472 fsl,pins = <
473 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
474 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
475 >;
476 };
477
478 pinctrl_uart3: uart3grp {
479 fsl,pins = <
480 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
481 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
482 >;
483 };
484
485 pinctrl_uart5: uart5grp {
486 fsl,pins = <
487 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
488 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
489 >;
490 };
491
492 pinctrl_usbotg: usbotggrp {
493 fsl,pins = <
494 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
495 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
496 >;
497 };
498
499 pinctrl_wdog: wdoggrp {
500 fsl,pins = <
501 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
502 >;
503 };
504};