1/*
  2 * Hisilicon Ltd. HiP01 SoC
  3 *
  4 * Copyright (c) 2014 Hisilicon Ltd.
  5 * Copyright (c) 2014 Huawei Ltd.
  6 *
  7 * Author: Wang Long <long.wanglong@huawei.com>
  8 *
  9 * This program is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License version 2 as
 11 * published by the Free Software Foundation.
 12 */
 13
 14/ {
 15	interrupt-parent = <&gic>;
 16	#address-cells = <1>;
 17	#size-cells = <1>;
 18
 19	gic: interrupt-controller@1e001000 {
 20		compatible = "arm,cortex-a9-gic";
 21		#interrupt-cells = <3>;
 22		#address-cells = <0>;
 23		interrupt-controller;
 24		reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
 25	};
 26
 27	hisi_refclk144mhz: refclk144mkhz {
 28		compatible = "fixed-clock";
 29		#clock-cells = <0>;
 30		clock-frequency = <144000000>;
 31		clock-output-names = "hisi:refclk144khz";
 32	};
 33
 34	soc {
 35		#address-cells = <1>;
 36		#size-cells = <1>;
 37		compatible = "simple-bus";
 38		interrupt-parent = <&gic>;
 39		ranges = <0 0x10000000 0x20000000>;
 40
 41		amba {
 42			#address-cells = <1>;
 43			#size-cells = <1>;
 44			compatible = "simple-bus";
 45			ranges;
 46
 47			uart0: uart@10001000 {
 48				compatible = "snps,dw-apb-uart";
 49				reg = <0x10001000 0x1000>;
 50				clocks = <&hisi_refclk144mhz>;
 51				clock-names = "apb_pclk";
 52				reg-shift = <2>;
 53				interrupts = <0 32 4>;
 54				status = "disabled";
 55			};
 56
 57			uart1: uart@10002000 {
 58				compatible = "snps,dw-apb-uart";
 59				reg = <0x10002000 0x1000>;
 60				clocks = <&hisi_refclk144mhz>;
 61				clock-names = "apb_pclk";
 62				reg-shift = <2>;
 63				interrupts = <0 33 4>;
 64				status = "disabled";
 65			};
 66
 67			uart2: uart@10003000 {
 68				compatible = "snps,dw-apb-uart";
 69				reg = <0x10003000 0x1000>;
 70				clocks = <&hisi_refclk144mhz>;
 71				clock-names = "apb_pclk";
 72				reg-shift = <2>;
 73				interrupts = <0 34 4>;
 74				status = "disabled";
 75			};
 76
 77			uart3: uart@10006000 {
 78				compatible = "snps,dw-apb-uart";
 79				reg = <0x10006000 0x1000>;
 80				clocks = <&hisi_refclk144mhz>;
 81				clock-names = "apb_pclk";
 82				reg-shift = <2>;
 83				interrupts = <0 4 4>;
 84				status = "disabled";
 85			};
 86		};
 87
 88		system-controller@10000000 {
 89			compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
 90			reg = <0x10000000 0x1000>;
 91			reboot-offset = <0x4>;
 92		};
 93
 94		global_timer@a000200 {
 95			compatible = "arm,cortex-a9-global-timer";
 96			reg = <0x0a000200 0x100>;
 97			interrupts = <1 11 0xf04>;
 98			clocks = <&hisi_refclk144mhz>;
 99		};
100
101		local_timer@a000600 {
102			compatible = "arm,cortex-a9-twd-timer";
103			reg = <0x0a000600 0x100>;
104			interrupts = <1 13 0xf04>;
105			clocks = <&hisi_refclk144mhz>;
106		};
107	};
108};