1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung's Exynos54xx SoC series common device tree source
  4 *
  5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 * Copyright (c) 2016 Krzysztof Kozlowski
  8 *
  9 * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
 10 * Exynos 54xx SoCs should include this file and customize it further
 11 * (e.g. with clocks).
 12 */
 13
 14#include "exynos5.dtsi"
 15
 16/ {
 17	compatible = "samsung,exynos5";
 18
 19	aliases {
 20		i2c4 = &hsi2c_4;
 21		i2c5 = &hsi2c_5;
 22		i2c6 = &hsi2c_6;
 23		i2c7 = &hsi2c_7;
 24		usbdrdphy0 = &usbdrd_phy0;
 25		usbdrdphy1 = &usbdrd_phy1;
 26	};
 27
 28	soc: soc {
 29		arm_a7_pmu: arm-a7-pmu {
 30			compatible = "arm,cortex-a7-pmu";
 31			interrupt-parent = <&gic>;
 32			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 33				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 34				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 35				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 36			status = "disabled";
 37		};
 38
 39		arm_a15_pmu: arm-a15-pmu {
 40			compatible = "arm,cortex-a15-pmu";
 41			interrupt-parent = <&combiner>;
 42			interrupts = <1 2>,
 43				     <7 0>,
 44				     <16 6>,
 45				     <19 2>;
 46			status = "disabled";
 47		};
 48
 49		sysram@2020000 {
 50			compatible = "mmio-sram";
 51			reg = <0x02020000 0x54000>;
 52			#address-cells = <1>;
 53			#size-cells = <1>;
 54			ranges = <0 0x02020000 0x54000>;
 55
 56			smp-sysram@0 {
 57				compatible = "samsung,exynos4210-sysram";
 58				reg = <0x0 0x1000>;
 59			};
 60
 61			smp-sysram@53000 {
 62				compatible = "samsung,exynos4210-sysram-ns";
 63				reg = <0x53000 0x1000>;
 64			};
 65		};
 66
 67		mct: mct@101c0000 {
 68			compatible = "samsung,exynos4210-mct";
 69			reg = <0x101c0000 0xb00>;
 70			interrupt-parent = <&mct_map>;
 71			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 72					<8>, <9>, <10>, <11>;
 73
 74			mct_map: mct-map {
 75				#interrupt-cells = <1>;
 76				#address-cells = <0>;
 77				#size-cells = <0>;
 78				interrupt-map = <0 &combiner 23 3>,
 79						<1 &combiner 23 4>,
 80						<2 &combiner 25 2>,
 81						<3 &combiner 25 3>,
 82						<4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 83						<5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
 84						<6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
 85						<7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
 86						<8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
 87						<9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
 88						<10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
 89						<11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
 90			};
 91		};
 92
 93		watchdog: watchdog@101d0000 {
 94			compatible = "samsung,exynos5420-wdt";
 95			reg = <0x101d0000 0x100>;
 96			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 97		};
 98
 99		/* i2c_0-3 are defined in exynos5.dtsi */
100		hsi2c_4: i2c@12ca0000 {
101			compatible = "samsung,exynos5250-hsi2c";
102			reg = <0x12ca0000 0x1000>;
103			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
104			#address-cells = <1>;
105			#size-cells = <0>;
106			status = "disabled";
107		};
108
109		hsi2c_5: i2c@12cb0000 {
110			compatible = "samsung,exynos5250-hsi2c";
111			reg = <0x12cb0000 0x1000>;
112			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
113			#address-cells = <1>;
114			#size-cells = <0>;
115			status = "disabled";
116		};
117
118		hsi2c_6: i2c@12cc0000 {
119			compatible = "samsung,exynos5250-hsi2c";
120			reg = <0x12cc0000 0x1000>;
121			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
122			#address-cells = <1>;
123			#size-cells = <0>;
124			status = "disabled";
125		};
126
127		hsi2c_7: i2c@12cd0000 {
128			compatible = "samsung,exynos5250-hsi2c";
129			reg = <0x12cd0000 0x1000>;
130			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
131			#address-cells = <1>;
132			#size-cells = <0>;
133			status = "disabled";
134		};
135
136		usbdrd3_0: usb3-0 {
137			compatible = "samsung,exynos5250-dwusb3";
138			#address-cells = <1>;
139			#size-cells = <1>;
140			ranges;
141
142			usbdrd_dwc3_0: dwc3@12000000 {
143				compatible = "snps,dwc3";
144				reg = <0x12000000 0x10000>;
145				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
146				phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
147				phy-names = "usb2-phy", "usb3-phy";
148				snps,dis_u3_susphy_quirk;
149			};
150		};
151
152		usbdrd_phy0: phy@12100000 {
153			compatible = "samsung,exynos5420-usbdrd-phy";
154			reg = <0x12100000 0x100>;
155			#phy-cells = <1>;
156		};
157
158		usbdrd3_1: usb3-1 {
159			compatible = "samsung,exynos5250-dwusb3";
160			#address-cells = <1>;
161			#size-cells = <1>;
162			ranges;
163
164			usbdrd_dwc3_1: dwc3@12400000 {
165				compatible = "snps,dwc3";
166				reg = <0x12400000 0x10000>;
167				phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
168				phy-names = "usb2-phy", "usb3-phy";
169				snps,dis_u3_susphy_quirk;
170			};
171		};
172
173		usbdrd_phy1: phy@12500000 {
174			compatible = "samsung,exynos5420-usbdrd-phy";
175			reg = <0x12500000 0x100>;
176			#phy-cells = <1>;
177		};
178
179		usbhost2: usb@12110000 {
180			compatible = "samsung,exynos4210-ehci";
181			reg = <0x12110000 0x100>;
182			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
183
184			#address-cells = <1>;
185			#size-cells = <0>;
186			port@0 {
187				reg = <0>;
188				phys = <&usb2_phy 1>;
189			};
190		};
191
192		usbhost1: usb@12120000 {
193			compatible = "samsung,exynos4210-ohci";
194			reg = <0x12120000 0x100>;
195			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
196
197			#address-cells = <1>;
198			#size-cells = <0>;
199			port@0 {
200				reg = <0>;
201				phys = <&usb2_phy 1>;
202			};
203		};
204
205		usb2_phy: phy@12130000 {
206			compatible = "samsung,exynos5250-usb2-phy";
207			reg = <0x12130000 0x100>;
208			#phy-cells = <1>;
209		};
210	};
211};