1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * SAMSUNG EXYNOS5420 SoC cpu device tree source
  4 *
  5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 *
  8 * This file provides desired ordering for Exynos5420 and Exynos5800
  9 * boards: CPU[0123] being the A15.
 10 *
 11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
 12 * but particular boards choose different booting order.
 13 *
 14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
 15 * booting cluster (big or LITTLE) is chosen by IROM code by reading
 16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
 17 * from the LITTLE: Cortex-A7.
 18 */
 19
 20/ {
 21	cpus {
 22		#address-cells = <1>;
 23		#size-cells = <0>;
 24
 25		cpu0: cpu@0 {
 26			device_type = "cpu";
 27			compatible = "arm,cortex-a15";
 28			reg = <0x0>;
 29			clocks = <&clock CLK_ARM_CLK>;
 30			clock-frequency = <1800000000>;
 31			cci-control-port = <&cci_control1>;
 32			operating-points-v2 = <&cluster_a15_opp_table>;
 33			#cooling-cells = <2>; /* min followed by max */
 34			capacity-dmips-mhz = <1024>;
 35		};
 36
 37		cpu1: cpu@1 {
 38			device_type = "cpu";
 39			compatible = "arm,cortex-a15";
 40			reg = <0x1>;
 41			clock-frequency = <1800000000>;
 42			cci-control-port = <&cci_control1>;
 43			operating-points-v2 = <&cluster_a15_opp_table>;
 44			#cooling-cells = <2>; /* min followed by max */
 45			capacity-dmips-mhz = <1024>;
 46		};
 47
 48		cpu2: cpu@2 {
 49			device_type = "cpu";
 50			compatible = "arm,cortex-a15";
 51			reg = <0x2>;
 52			clock-frequency = <1800000000>;
 53			cci-control-port = <&cci_control1>;
 54			operating-points-v2 = <&cluster_a15_opp_table>;
 55			#cooling-cells = <2>; /* min followed by max */
 56			capacity-dmips-mhz = <1024>;
 57		};
 58
 59		cpu3: cpu@3 {
 60			device_type = "cpu";
 61			compatible = "arm,cortex-a15";
 62			reg = <0x3>;
 63			clock-frequency = <1800000000>;
 64			cci-control-port = <&cci_control1>;
 65			operating-points-v2 = <&cluster_a15_opp_table>;
 66			#cooling-cells = <2>; /* min followed by max */
 67			capacity-dmips-mhz = <1024>;
 68		};
 69
 70		cpu4: cpu@100 {
 71			device_type = "cpu";
 72			compatible = "arm,cortex-a7";
 73			reg = <0x100>;
 74			clocks = <&clock CLK_KFC_CLK>;
 75			clock-frequency = <1000000000>;
 76			cci-control-port = <&cci_control0>;
 77			operating-points-v2 = <&cluster_a7_opp_table>;
 78			#cooling-cells = <2>; /* min followed by max */
 79			capacity-dmips-mhz = <539>;
 80		};
 81
 82		cpu5: cpu@101 {
 83			device_type = "cpu";
 84			compatible = "arm,cortex-a7";
 85			reg = <0x101>;
 86			clock-frequency = <1000000000>;
 87			cci-control-port = <&cci_control0>;
 88			operating-points-v2 = <&cluster_a7_opp_table>;
 89			#cooling-cells = <2>; /* min followed by max */
 90			capacity-dmips-mhz = <539>;
 91		};
 92
 93		cpu6: cpu@102 {
 94			device_type = "cpu";
 95			compatible = "arm,cortex-a7";
 96			reg = <0x102>;
 97			clock-frequency = <1000000000>;
 98			cci-control-port = <&cci_control0>;
 99			operating-points-v2 = <&cluster_a7_opp_table>;
100			#cooling-cells = <2>; /* min followed by max */
101			capacity-dmips-mhz = <539>;
102		};
103
104		cpu7: cpu@103 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a7";
107			reg = <0x103>;
108			clock-frequency = <1000000000>;
109			cci-control-port = <&cci_control0>;
110			operating-points-v2 = <&cluster_a7_opp_table>;
111			#cooling-cells = <2>; /* min followed by max */
112			capacity-dmips-mhz = <539>;
113		};
114	};
115};
116
117&arm_a7_pmu {
118	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
119	status = "okay";
120};
121
122&arm_a15_pmu {
123	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
124	status = "okay";
125};