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1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13
14/ {
15 compatible = "renesas,emev2";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
26 i2c0 = &iic0;
27 i2c1 = &iic1;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 clock-frequency = <533000000>;
39 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 clock-frequency = <533000000>;
45 };
46 };
47
48 gic: interrupt-controller@e0020000 {
49 compatible = "arm,pl390";
50 interrupt-controller;
51 #interrupt-cells = <3>;
52 reg = <0xe0028000 0x1000>,
53 <0xe0020000 0x0100>;
54 };
55
56 pmu {
57 compatible = "arm,cortex-a9-pmu";
58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
60 };
61
62 clocks@e0110000 {
63 compatible = "renesas,emev2-smu";
64 reg = <0xe0110000 0x10000>;
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 c32ki: c32ki {
69 compatible = "fixed-clock";
70 clock-frequency = <32768>;
71 #clock-cells = <0>;
72 };
73 iic0_sclkdiv: iic0_sclkdiv@624,0 {
74 compatible = "renesas,emev2-smu-clkdiv";
75 reg = <0x624 0>;
76 clocks = <&pll3_fo>;
77 #clock-cells = <0>;
78 };
79 iic0_sclk: iic0_sclk@48c,1 {
80 compatible = "renesas,emev2-smu-gclk";
81 reg = <0x48c 1>;
82 clocks = <&iic0_sclkdiv>;
83 #clock-cells = <0>;
84 };
85 iic1_sclkdiv: iic1_sclkdiv@624,16 {
86 compatible = "renesas,emev2-smu-clkdiv";
87 reg = <0x624 16>;
88 clocks = <&pll3_fo>;
89 #clock-cells = <0>;
90 };
91 iic1_sclk: iic1_sclk@490,1 {
92 compatible = "renesas,emev2-smu-gclk";
93 reg = <0x490 1>;
94 clocks = <&iic1_sclkdiv>;
95 #clock-cells = <0>;
96 };
97 pll3_fo: pll3_fo {
98 compatible = "fixed-factor-clock";
99 clocks = <&c32ki>;
100 clock-div = <1>;
101 clock-mult = <7000>;
102 #clock-cells = <0>;
103 };
104 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
105 compatible = "renesas,emev2-smu-clkdiv";
106 reg = <0x610 0>;
107 clocks = <&pll3_fo>;
108 #clock-cells = <0>;
109 };
110 usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
111 compatible = "renesas,emev2-smu-clkdiv";
112 reg = <0x65c 0>;
113 clocks = <&pll3_fo>;
114 #clock-cells = <0>;
115 };
116 usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
117 compatible = "renesas,emev2-smu-clkdiv";
118 reg = <0x65c 16>;
119 clocks = <&pll3_fo>;
120 #clock-cells = <0>;
121 };
122 usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
123 compatible = "renesas,emev2-smu-clkdiv";
124 reg = <0x660 0>;
125 clocks = <&pll3_fo>;
126 #clock-cells = <0>;
127 };
128 usia_u0_sclk: usia_u0_sclk@4a0,1 {
129 compatible = "renesas,emev2-smu-gclk";
130 reg = <0x4a0 1>;
131 clocks = <&usia_u0_sclkdiv>;
132 #clock-cells = <0>;
133 };
134 usib_u1_sclk: usib_u1_sclk@4b8,1 {
135 compatible = "renesas,emev2-smu-gclk";
136 reg = <0x4b8 1>;
137 clocks = <&usib_u1_sclkdiv>;
138 #clock-cells = <0>;
139 };
140 usib_u2_sclk: usib_u2_sclk@4bc,1 {
141 compatible = "renesas,emev2-smu-gclk";
142 reg = <0x4bc 1>;
143 clocks = <&usib_u2_sclkdiv>;
144 #clock-cells = <0>;
145 };
146 usib_u3_sclk: usib_u3_sclk@4c0,1 {
147 compatible = "renesas,emev2-smu-gclk";
148 reg = <0x4c0 1>;
149 clocks = <&usib_u3_sclkdiv>;
150 #clock-cells = <0>;
151 };
152 sti_sclk: sti_sclk@528,1 {
153 compatible = "renesas,emev2-smu-gclk";
154 reg = <0x528 1>;
155 clocks = <&c32ki>;
156 #clock-cells = <0>;
157 };
158 };
159
160 timer@e0180000 {
161 compatible = "renesas,em-sti";
162 reg = <0xe0180000 0x54>;
163 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&sti_sclk>;
165 clock-names = "sclk";
166 };
167
168 uart0: serial@e1020000 {
169 compatible = "renesas,em-uart";
170 reg = <0xe1020000 0x38>;
171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&usia_u0_sclk>;
173 clock-names = "sclk";
174 };
175
176 uart1: serial@e1030000 {
177 compatible = "renesas,em-uart";
178 reg = <0xe1030000 0x38>;
179 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&usib_u1_sclk>;
181 clock-names = "sclk";
182 };
183
184 uart2: serial@e1040000 {
185 compatible = "renesas,em-uart";
186 reg = <0xe1040000 0x38>;
187 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&usib_u2_sclk>;
189 clock-names = "sclk";
190 };
191
192 uart3: serial@e1050000 {
193 compatible = "renesas,em-uart";
194 reg = <0xe1050000 0x38>;
195 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&usib_u3_sclk>;
197 clock-names = "sclk";
198 };
199
200 pfc: pin-controller@e0140200 {
201 compatible = "renesas,pfc-emev2";
202 reg = <0xe0140200 0x100>;
203 };
204
205 gpio0: gpio@e0050000 {
206 compatible = "renesas,em-gio";
207 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
208 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 0 32>;
212 #gpio-cells = <2>;
213 ngpios = <32>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
216 };
217 gpio1: gpio@e0050080 {
218 compatible = "renesas,em-gio";
219 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
220 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
222 gpio-controller;
223 gpio-ranges = <&pfc 0 32 32>;
224 #gpio-cells = <2>;
225 ngpios = <32>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
229 gpio2: gpio@e0050100 {
230 compatible = "renesas,em-gio";
231 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
232 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 64 32>;
236 #gpio-cells = <2>;
237 ngpios = <32>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241 gpio3: gpio@e0050180 {
242 compatible = "renesas,em-gio";
243 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
244 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 gpio-controller;
247 gpio-ranges = <&pfc 0 96 32>;
248 #gpio-cells = <2>;
249 ngpios = <32>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253 gpio4: gpio@e0050200 {
254 compatible = "renesas,em-gio";
255 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
256 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
258 gpio-controller;
259 gpio-ranges = <&pfc 0 128 31>;
260 #gpio-cells = <2>;
261 ngpios = <31>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265
266 iic0: i2c@e0070000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "renesas,iic-emev2";
270 reg = <0xe0070000 0x28>;
271 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
272 clocks = <&iic0_sclk>;
273 clock-names = "sclk";
274 status = "disabled";
275 };
276
277 iic1: i2c@e10a0000 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "renesas,iic-emev2";
281 reg = <0xe10a0000 0x28>;
282 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
283 clocks = <&iic1_sclk>;
284 clock-names = "sclk";
285 status = "disabled";
286 };
287};