1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2/*
  3 * Device Tree file for Marvell Armada 385 Access Point Development board
  4 * (DB-88F6820-AP)
  5 *
  6 *  Copyright (C) 2014 Marvell
  7 *
  8 * Nadav Haklai <nadavh@marvell.com>
  9 */
 10
 11/dts-v1/;
 12#include "armada-385.dtsi"
 13
 14#include <dt-bindings/gpio/gpio.h>
 15
 16/ {
 17	model = "Marvell Armada 385 Access Point Development Board";
 18	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
 19
 20	chosen {
 21		stdout-path = "serial1:115200n8";
 22	};
 23
 24	memory {
 25		device_type = "memory";
 26		reg = <0x00000000 0x80000000>; /* 2GB */
 27	};
 28
 29	soc {
 30		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 31			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 32			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
 33			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
 34			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 35
 36		internal-regs {
 37			i2c0: i2c@11000 {
 38				pinctrl-names = "default";
 39				pinctrl-0 = <&i2c0_pins>;
 40				status = "okay";
 41
 42				/*
 43				 * This bus is wired to two EEPROM
 44				 * sockets, one of which holding the
 45				 * board ID used by the	bootloader.
 46				 * Erasing this EEPROM's content will
 47				 * brick the board.
 48				 * Use this bus with caution.
 49				 */
 50			};
 51
 52			mdio@72004 {
 53				pinctrl-names = "default";
 54				pinctrl-0 = <&mdio_pins>;
 55
 56				phy0: ethernet-phy@1 {
 57					reg = <1>;
 58				};
 59
 60				phy1: ethernet-phy@4 {
 61					reg = <4>;
 62				};
 63
 64				phy2: ethernet-phy@6 {
 65					reg = <6>;
 66				};
 67			};
 68
 69			/* UART0 is exposed through the JP8 connector */
 70			uart0: serial@12000 {
 71				pinctrl-names = "default";
 72				pinctrl-0 = <&uart0_pins>;
 73				status = "okay";
 74			};
 75
 76			/*
 77			 * UART1 is exposed through a FTDI chip
 78			 * wired to the mini-USB connector
 79			 */
 80			uart1: serial@12100 {
 81				pinctrl-names = "default";
 82				pinctrl-0 = <&uart1_pins>;
 83				status = "okay";
 84			};
 85
 86			pinctrl@18000 {
 87				xhci0_vbus_pins: xhci0-vbus-pins {
 88					marvell,pins = "mpp44";
 89					marvell,function = "gpio";
 90				};
 91			};
 92
 93			/* CON3 */
 94			ethernet@30000 {
 95				status = "okay";
 96				phy = <&phy2>;
 97				phy-mode = "sgmii";
 98				buffer-manager = <&bm>;
 99				bm,pool-long = <1>;
100				bm,pool-short = <3>;
101			};
102
103			/* CON2 */
104			ethernet@34000 {
105				status = "okay";
106				phy = <&phy1>;
107				phy-mode = "sgmii";
108				buffer-manager = <&bm>;
109				bm,pool-long = <2>;
110				bm,pool-short = <3>;
111			};
112
113			usb@58000 {
114				status = "okay";
115			};
116
117			/* CON4 */
118			ethernet@70000 {
119				pinctrl-names = "default";
120
121				/*
122				 * The Reference Clock 0 is used to
123				 * provide a clock to the PHY
124				 */
125				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
126				status = "okay";
127				phy = <&phy0>;
128				phy-mode = "rgmii-id";
129				buffer-manager = <&bm>;
130				bm,pool-long = <0>;
131				bm,pool-short = <3>;
132			};
133
134			bm@c8000 {
135				status = "okay";
136			};
137
138			nfc: flash@d0000 {
139				status = "okay";
140				num-cs = <1>;
141				nand-ecc-strength = <4>;
142				nand-ecc-step-size = <512>;
143				marvell,nand-keep-config;
144				marvell,nand-enable-arbiter;
145				nand-on-flash-bbt;
146
147				partitions {
148					compatible = "fixed-partitions";
149					#address-cells = <1>;
150					#size-cells = <1>;
151
152					partition@0 {
153						label = "U-Boot";
154						reg = <0x00000000 0x00800000>;
155						read-only;
156					};
157
158					partition@800000 {
159						label = "uImage";
160						reg = <0x00800000 0x00400000>;
161						read-only;
162					};
163
164					partition@c00000 {
165						label = "Root";
166						reg = <0x00c00000 0x3f400000>;
167					};
168				};
169			};
170
171			usb3@f0000 {
172				status = "okay";
173				usb-phy = <&usb3_phy>;
174			};
175		};
176
177		bm-bppi {
178			status = "okay";
179		};
180
181		pcie {
182			status = "okay";
183
184			/*
185			 * The three PCIe units are accessible through
186			 * standard mini-PCIe slots on the board.
187			 */
188			pcie@1,0 {
189				/* Port 0, Lane 0 */
190				status = "okay";
191			};
192
193			pcie@2,0 {
194				/* Port 1, Lane 0 */
195				status = "okay";
196			};
197
198			pcie@3,0 {
199				/* Port 2, Lane 0 */
200				status = "okay";
201			};
202		};
203	};
204
205	usb3_phy: usb3_phy {
206		compatible = "usb-nop-xceiv";
207		vcc-supply = <&reg_xhci0_vbus>;
208		#phy-cells = <0>;
209	};
210
211	reg_xhci0_vbus: xhci0-vbus {
212		compatible = "regulator-fixed";
213		pinctrl-names = "default";
214		pinctrl-0 = <&xhci0_vbus_pins>;
215		regulator-name = "xhci0-vbus";
216		regulator-min-microvolt = <5000000>;
217		regulator-max-microvolt = <5000000>;
218		enable-active-high;
219		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
220	};
221};
222
223&spi1 {
224	pinctrl-names = "default";
225	pinctrl-0 = <&spi1_pins>;
226	status = "okay";
227
228	spi-flash@0 {
229		#address-cells = <1>;
230		#size-cells = <1>;
231		compatible = "st,m25p128", "jedec,spi-nor";
232		reg = <0>; /* Chip select 0 */
233		spi-max-frequency = <54000000>;
234	};
235};