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1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#include <dt-bindings/interrupt-controller/irq.h>
24#include <dt-bindings/gpio/gpio.h>
25#include "skeleton.dtsi"
26
27/ {
28 compatible = "arm,realview-eb";
29
30 chosen { };
31
32 aliases {
33 serial0 = &serial0;
34 serial1 = &serial1;
35 serial2 = &serial2;
36 serial3 = &serial3;
37 i2c0 = &i2c;
38 };
39
40 memory {
41 /* 128 MiB memory @ 0x0 */
42 reg = <0x00000000 0x08000000>;
43 };
44
45 /* The voltage to the MMC card is hardwired at 3.3V */
46 vmmc: fixedregulator@0 {
47 compatible = "regulator-fixed";
48 regulator-name = "vmmc";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 };
53
54 xtal24mhz: xtal24mhz@24M {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59
60 timclk: timclk@1M {
61 #clock-cells = <0>;
62 compatible = "fixed-factor-clock";
63 clock-div = <24>;
64 clock-mult = <1>;
65 clocks = <&xtal24mhz>;
66 };
67
68 mclk: mclk@24M {
69 #clock-cells = <0>;
70 compatible = "fixed-factor-clock";
71 clock-div = <1>;
72 clock-mult = <1>;
73 clocks = <&xtal24mhz>;
74 };
75
76 kmiclk: kmiclk@24M {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clock-div = <1>;
80 clock-mult = <1>;
81 clocks = <&xtal24mhz>;
82 };
83
84 sspclk: sspclk@24M {
85 #clock-cells = <0>;
86 compatible = "fixed-factor-clock";
87 clock-div = <1>;
88 clock-mult = <1>;
89 clocks = <&xtal24mhz>;
90 };
91
92 uartclk: uartclk@24M {
93 #clock-cells = <0>;
94 compatible = "fixed-factor-clock";
95 clock-div = <1>;
96 clock-mult = <1>;
97 clocks = <&xtal24mhz>;
98 };
99
100 wdogclk: wdogclk@24M {
101 #clock-cells = <0>;
102 compatible = "fixed-factor-clock";
103 clock-div = <1>;
104 clock-mult = <1>;
105 clocks = <&xtal24mhz>;
106 };
107
108 /* FIXME: this actually hangs off the PLL clocks */
109 pclk: pclk@0 {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <0>;
113 };
114
115 flash0@40000000 {
116 /* 2 * 32MiB NOR Flash memory */
117 compatible = "arm,versatile-flash", "cfi-flash";
118 reg = <0x40000000 0x04000000>;
119 bank-width = <4>;
120 };
121
122 flash1@44000000 {
123 /* 2 * 32MiB NOR Flash memory */
124 compatible = "arm,versatile-flash", "cfi-flash";
125 reg = <0x44000000 0x04000000>;
126 bank-width = <4>;
127 };
128
129 /* SMSC LAN91C111 ethernet with PHY and EEPROM */
130 ethernet: ethernet@4e000000 {
131 compatible = "smsc,lan91c111";
132 reg = <0x4e000000 0x10000>;
133 /*
134 * This means the adapter can be accessed with 8, 16 or
135 * 32 bit reads/writes.
136 */
137 reg-io-width = <7>;
138 };
139
140 usb: usb@4f000000 {
141 compatible = "nxp,usb-isp1761";
142 reg = <0x4f000000 0x20000>;
143 port1-otg;
144 };
145
146 bridge {
147 compatible = "ti,ths8134a", "ti,ths8134";
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 ports {
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 port@0 {
156 reg = <0>;
157
158 vga_bridge_in: endpoint {
159 remote-endpoint = <&clcd_pads>;
160 };
161 };
162
163 port@1 {
164 reg = <1>;
165
166 vga_bridge_out: endpoint {
167 remote-endpoint = <&vga_con_in>;
168 };
169 };
170 };
171 };
172
173 vga {
174 compatible = "vga-connector";
175
176 port {
177 vga_con_in: endpoint {
178 remote-endpoint = <&vga_bridge_out>;
179 };
180 };
181 };
182
183 /* These peripherals are inside the FPGA */
184 fpga {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 compatible = "simple-bus";
188 ranges;
189
190 syscon: syscon@10000000 {
191 compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
192 reg = <0x10000000 0x1000>;
193
194 led@08.0 {
195 compatible = "register-bit-led";
196 offset = <0x08>;
197 mask = <0x01>;
198 label = "versatile:0";
199 linux,default-trigger = "heartbeat";
200 default-state = "on";
201 };
202 led@08.1 {
203 compatible = "register-bit-led";
204 offset = <0x08>;
205 mask = <0x02>;
206 label = "versatile:1";
207 linux,default-trigger = "mmc0";
208 default-state = "off";
209 };
210 led@08.2 {
211 compatible = "register-bit-led";
212 offset = <0x08>;
213 mask = <0x04>;
214 label = "versatile:2";
215 linux,default-trigger = "cpu0";
216 default-state = "off";
217 };
218 led@08.3 {
219 compatible = "register-bit-led";
220 offset = <0x08>;
221 mask = <0x08>;
222 label = "versatile:3";
223 default-state = "off";
224 };
225 led@08.4 {
226 compatible = "register-bit-led";
227 offset = <0x08>;
228 mask = <0x10>;
229 label = "versatile:4";
230 default-state = "off";
231 };
232 led@08.5 {
233 compatible = "register-bit-led";
234 offset = <0x08>;
235 mask = <0x20>;
236 label = "versatile:5";
237 default-state = "off";
238 };
239 led@08.6 {
240 compatible = "register-bit-led";
241 offset = <0x08>;
242 mask = <0x40>;
243 label = "versatile:6";
244 default-state = "off";
245 };
246 led@08.7 {
247 compatible = "register-bit-led";
248 offset = <0x08>;
249 mask = <0x80>;
250 label = "versatile:7";
251 default-state = "off";
252 };
253 oscclk0: osc0@0c {
254 compatible = "arm,syscon-icst307";
255 #clock-cells = <0>;
256 lock-offset = <0x20>;
257 vco-offset = <0x0C>;
258 clocks = <&xtal24mhz>;
259 };
260 oscclk1: osc1@10 {
261 compatible = "arm,syscon-icst307";
262 #clock-cells = <0>;
263 lock-offset = <0x20>;
264 vco-offset = <0x10>;
265 clocks = <&xtal24mhz>;
266 };
267 oscclk2: osc2@14 {
268 compatible = "arm,syscon-icst307";
269 #clock-cells = <0>;
270 lock-offset = <0x20>;
271 vco-offset = <0x14>;
272 clocks = <&xtal24mhz>;
273 };
274 oscclk3: osc3@18 {
275 compatible = "arm,syscon-icst307";
276 #clock-cells = <0>;
277 lock-offset = <0x20>;
278 vco-offset = <0x18>;
279 clocks = <&xtal24mhz>;
280 };
281 oscclk4: osc4@1c {
282 compatible = "arm,syscon-icst307";
283 #clock-cells = <0>;
284 lock-offset = <0x20>;
285 vco-offset = <0x1c>;
286 clocks = <&xtal24mhz>;
287 };
288 };
289
290 i2c: i2c@10002000 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "arm,versatile-i2c";
294 reg = <0x10002000 0x1000>;
295
296 rtc@68 {
297 compatible = "dallas,ds1338";
298 reg = <0x68>;
299 };
300 };
301
302 aaci: aaci@10004000 {
303 compatible = "arm,pl041", "arm,primecell";
304 reg = <0x10004000 0x1000>;
305 clocks = <&pclk>;
306 clock-names = "apb_pclk";
307 };
308
309 mmc: mmcsd@10005000 {
310 compatible = "arm,pl18x", "arm,primecell";
311 reg = <0x10005000 0x1000>;
312
313 /* Due to frequent FIFO overruns, use just 500 kHz */
314 max-frequency = <500000>;
315 bus-width = <4>;
316 cap-sd-highspeed;
317 cap-mmc-highspeed;
318 clocks = <&mclk>, <&pclk>;
319 clock-names = "mclk", "apb_pclk";
320 vmmc-supply = <&vmmc>;
321 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
322 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
323 };
324
325 kmi0: kmi@10006000 {
326 compatible = "arm,pl050", "arm,primecell";
327 reg = <0x10006000 0x1000>;
328 clocks = <&kmiclk>, <&pclk>;
329 clock-names = "KMIREFCLK", "apb_pclk";
330 };
331
332 kmi1: kmi@10007000 {
333 compatible = "arm,pl050", "arm,primecell";
334 reg = <0x10007000 0x1000>;
335 clocks = <&kmiclk>, <&pclk>;
336 clock-names = "KMIREFCLK", "apb_pclk";
337 };
338
339 charlcd: fpga_charlcd: charlcd@10008000 {
340 compatible = "arm,versatile-lcd";
341 reg = <0x10008000 0x1000>;
342 clocks = <&pclk>;
343 clock-names = "apb_pclk";
344 };
345
346 serial0: serial@10009000 {
347 compatible = "arm,pl011", "arm,primecell";
348 reg = <0x10009000 0x1000>;
349 clocks = <&uartclk>, <&pclk>;
350 clock-names = "uartclk", "apb_pclk";
351 };
352
353 serial1: serial@1000a000 {
354 compatible = "arm,pl011", "arm,primecell";
355 reg = <0x1000a000 0x1000>;
356 clocks = <&uartclk>, <&pclk>;
357 clock-names = "uartclk", "apb_pclk";
358 };
359
360 serial2: serial@1000b000 {
361 compatible = "arm,pl011", "arm,primecell";
362 reg = <0x1000b000 0x1000>;
363 clocks = <&uartclk>, <&pclk>;
364 clock-names = "uartclk", "apb_pclk";
365 };
366
367 serial3: serial@1000c000 {
368 compatible = "arm,pl011", "arm,primecell";
369 reg = <0x1000c000 0x1000>;
370 clocks = <&uartclk>, <&pclk>;
371 clock-names = "uartclk", "apb_pclk";
372 };
373
374 ssp: ssp@1000d000 {
375 compatible = "arm,pl022", "arm,primecell";
376 reg = <0x1000d000 0x1000>;
377 clocks = <&sspclk>, <&pclk>;
378 clock-names = "SSPCLK", "apb_pclk";
379 };
380
381 wdog: watchdog@10010000 {
382 compatible = "arm,sp805", "arm,primecell";
383 reg = <0x10010000 0x1000>;
384 clocks = <&wdogclk>, <&pclk>;
385 clock-names = "wdogclk", "apb_pclk";
386 status = "disabled";
387 };
388
389 timer01: timer@10011000 {
390 compatible = "arm,sp804", "arm,primecell";
391 reg = <0x10011000 0x1000>;
392 clocks = <&timclk>, <&timclk>, <&pclk>;
393 clock-names = "timer1", "timer2", "apb_pclk";
394 };
395
396 timer23: timer@10012000 {
397 compatible = "arm,sp804", "arm,primecell";
398 reg = <0x10012000 0x1000>;
399 clocks = <&timclk>, <&timclk>, <&pclk>;
400 clock-names = "timer1", "timer2", "apb_pclk";
401 };
402
403 gpio0: gpio@10013000 {
404 compatible = "arm,pl061", "arm,primecell";
405 reg = <0x10013000 0x1000>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 clocks = <&pclk>;
411 clock-names = "apb_pclk";
412 };
413
414 gpio1: gpio@10014000 {
415 compatible = "arm,pl061", "arm,primecell";
416 reg = <0x10014000 0x1000>;
417 gpio-controller;
418 #gpio-cells = <2>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
421 clocks = <&pclk>;
422 clock-names = "apb_pclk";
423 };
424
425 gpio2: gpio@10015000 {
426 compatible = "arm,pl061", "arm,primecell";
427 reg = <0x10015000 0x1000>;
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 clocks = <&pclk>;
433 clock-names = "apb_pclk";
434 };
435
436 rtc: rtc@10017000 {
437 compatible = "arm,pl031", "arm,primecell";
438 reg = <0x10017000 0x1000>;
439 clocks = <&pclk>;
440 clock-names = "apb_pclk";
441 };
442
443 clcd: clcd@10020000 {
444 compatible = "arm,pl111", "arm,primecell";
445 reg = <0x10020000 0x1000>;
446 interrupt-names = "combined";
447 clocks = <&oscclk0>, <&pclk>;
448 clock-names = "clcdclk", "apb_pclk";
449 /* 1024x768 16bpp @65MHz works fine */
450 max-memory-bandwidth = <95000000>;
451
452 port {
453 clcd_pads: endpoint {
454 remote-endpoint = <&vga_bridge_in>;
455 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
456 };
457 };
458 };
459 };
460};