1/*
  2 * Copyright 2016 Linaro Ltd
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a copy
  5 * of this software and associated documentation files (the "Software"), to deal
  6 * in the Software without restriction, including without limitation the rights
  7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  8 * copies of the Software, and to permit persons to whom the Software is
  9 * furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 20 * THE SOFTWARE.
 21 */
 22
 23#include <dt-bindings/interrupt-controller/irq.h>
 24#include <dt-bindings/gpio/gpio.h>
 25#include "arm-realview-eb.dtsi"
 26
 27/*
 28 * This is the common include file for all MPCore variants of the
 29 * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B
 30 * and Cortex-A9 MPCore.
 31 */
 32/ {
 33	soc {
 34		#address-cells = <1>;
 35		#size-cells = <1>;
 36		compatible = "arm,realview-eb-soc", "simple-bus";
 37		regmap = <&syscon>;
 38		ranges;
 39
 40		/* Primary interrupt controller in the test chip */
 41		intc: interrupt-controller@1f000100 {
 42			compatible = "arm,eb11mp-gic";
 43			#interrupt-cells = <3>;
 44			#address-cells = <1>;
 45			interrupt-controller;
 46			reg = <0x1f001000 0x1000>,
 47			      <0x1f000100 0x100>;
 48		};
 49
 50		/* Secondary interrupt controller on the FPGA */
 51		intc_second: interrupt-controller@10040000 {
 52			compatible = "arm,pl390";
 53			#interrupt-cells = <3>;
 54			#address-cells = <1>;
 55			interrupt-controller;
 56			reg = <0x10041000 0x1000>,
 57			      <0x10040000 0x100>;
 58			interrupt-parent = <&intc>;
 59			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 60		};
 61
 62		L2: l2-cache {
 63			compatible = "arm,l220-cache";
 64			reg = <0x1f002000 0x1000>;
 65			interrupt-parent = <&intc>;
 66			interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
 67			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
 68			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
 69			cache-unified;
 70			cache-level = <2>;
 71			/*
 72			 * Override default cache size, sets and
 73			 * associativity as these may be erroneously set
 74			 * up by boot loader(s), probably for safety
 75			 * since th outer sync operation can cause the
 76			 * cache to hang unless disabled.
 77			 */
 78			cache-size = <1048576>; // 1MB
 79			cache-sets = <4096>;
 80			cache-line-size = <32>;
 81			arm,shared-override;
 82			arm,parity-enable;
 83			arm,outer-sync-disable;
 84		};
 85
 86		scu: scu@1f000000 {
 87			compatible = "arm,arm11mp-scu";
 88			reg = <0x1f000000 0x100>;
 89		};
 90
 91		twd_timer: timer@1f000600 {
 92			compatible = "arm,arm11mp-twd-timer";
 93			reg = <0x1f000600 0x20>;
 94			interrupt-parent = <&intc>;
 95			interrupts = <1 13 0xf04>;
 96		};
 97
 98		twd_wdog: watchdog@1f000620 {
 99			compatible = "arm,arm11mp-twd-wdt";
100			reg = <0x1f000620 0x20>;
101			interrupt-parent = <&intc>;
102			interrupts = <1 14 0xf04>;
103		};
104
105		/* PMU with one IRQ line per core */
106		pmu: pmu@0 {
107			compatible = "arm,arm11mpcore-pmu";
108			interrupt-parent = <&intc>;
109			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
110			     <0 18 IRQ_TYPE_LEVEL_HIGH>,
111			     <0 19 IRQ_TYPE_LEVEL_HIGH>,
112			     <0 20 IRQ_TYPE_LEVEL_HIGH>;
113		};
114	};
115};
116
117/*
118 * This adapts all the peripherals to the interrupt routing
119 * to the GIC on the core tile.
120 */
121
122&ethernet {
123	interrupt-parent = <&intc>;
124	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
125};
126
127&usb {
128	interrupt-parent = <&intc>;
129	interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
130};
131
132&aaci {
133	interrupt-parent = <&intc>;
134	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&mmc {
138	interrupt-parent = <&intc>;
139	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
140			<0 15 IRQ_TYPE_LEVEL_HIGH>;
141};
142
143&kmi0 {
144	interrupt-parent = <&intc>;
145	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
146};
147
148&kmi1 {
149	interrupt-parent = <&intc>;
150	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&serial0 {
154	interrupt-parent = <&intc>;
155	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
156};
157
158&serial1 {
159	interrupt-parent = <&intc>;
160	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
161};
162
163&timer01 {
164	interrupt-parent = <&intc>;
165	interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
166};
167
168&timer23 {
169	interrupt-parent = <&intc>;
170	interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
171};
172
173&rtc {
174	interrupt-parent = <&intc>;
175	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
176};
177
178/*
179 * On revision A, these peripherals does not have their IRQ lines
180 * routed to the core tile, but they can be reached on the secondary
181 * GIC.
182 */
183&gpio0 {
184	interrupt-parent = <&intc_second>;
185	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
186};
187
188&gpio1 {
189	interrupt-parent = <&intc_second>;
190	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
191};
192
193&gpio2 {
194	interrupt-parent = <&intc_second>;
195	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
196};
197
198&serial2 {
199	interrupt-parent = <&intc_second>;
200	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
201	status = "okay";
202};
203
204&serial3 {
205	interrupt-parent = <&intc_second>;
206	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
207	status = "okay";
208};
209
210&ssp {
211	interrupt-parent = <&intc_second>;
212	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
213	status = "okay";
214};
215
216&wdog {
217	interrupt-parent = <&intc_second>;
218	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
219	status = "okay";
220};