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1/*
2 * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7/dts-v1/;
8#include <dt-bindings/input/input.h>
9#include "mt7623.dtsi"
10#include "mt6323.dtsi"
11
12/ {
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
15
16 aliases {
17 serial2 = &uart2;
18 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 };
23
24 cpus {
25 cpu@0 {
26 proc-supply = <&mt6323_vproc_reg>;
27 };
28
29 cpu@1 {
30 proc-supply = <&mt6323_vproc_reg>;
31 };
32
33 cpu@2 {
34 proc-supply = <&mt6323_vproc_reg>;
35 };
36
37 cpu@3 {
38 proc-supply = <&mt6323_vproc_reg>;
39 };
40 };
41
42 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
44 regulator-name = "fixed-1.8V";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50
51 reg_3p3v: regulator-3p3v {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-3.3V";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
60 reg_5v: regulator-5v {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-5V";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 regulator-boot-on;
66 regulator-always-on;
67 };
68
69 gpio-keys {
70 compatible = "gpio-keys";
71 pinctrl-names = "default";
72 pinctrl-0 = <&key_pins_a>;
73
74 factory {
75 label = "factory";
76 linux,code = <BTN_0>;
77 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
78 };
79
80 wps {
81 label = "wps";
82 linux,code = <KEY_WPS_BUTTON>;
83 gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
84 };
85 };
86
87 leds {
88 compatible = "gpio-leds";
89 pinctrl-names = "default";
90 pinctrl-0 = <&led_pins_a>;
91
92 blue {
93 label = "bpi-r2:pio:blue";
94 gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
95 default-state = "off";
96 };
97
98 green {
99 label = "bpi-r2:pio:green";
100 gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
101 default-state = "off";
102 };
103
104 red {
105 label = "bpi-r2:pio:red";
106 gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
107 default-state = "off";
108 };
109 };
110
111 memory@80000000 {
112 reg = <0 0x80000000 0 0x40000000>;
113 };
114};
115
116&cir {
117 pinctrl-names = "default";
118 pinctrl-0 = <&cir_pins_a>;
119 status = "okay";
120};
121
122&crypto {
123 status = "okay";
124};
125
126ð {
127 status = "okay";
128
129 gmac0: mac@0 {
130 compatible = "mediatek,eth-mac";
131 reg = <0>;
132 phy-mode = "trgmii";
133
134 fixed-link {
135 speed = <1000>;
136 full-duplex;
137 pause;
138 };
139 };
140
141 mdio: mdio-bus {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 switch@0 {
146 compatible = "mediatek,mt7530";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0>;
150 reset-gpios = <&pio 33 0>;
151 core-supply = <&mt6323_vpa_reg>;
152 io-supply = <&mt6323_vemc3v3_reg>;
153
154 ports {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 reg = <0>;
158
159 port@0 {
160 reg = <0>;
161 label = "wan";
162 };
163
164 port@1 {
165 reg = <1>;
166 label = "lan0";
167 };
168
169 port@2 {
170 reg = <2>;
171 label = "lan1";
172 };
173
174 port@3 {
175 reg = <3>;
176 label = "lan2";
177 };
178
179 port@4 {
180 reg = <4>;
181 label = "lan3";
182 };
183
184 port@6 {
185 reg = <6>;
186 label = "cpu";
187 ethernet = <&gmac0>;
188 phy-mode = "trgmii";
189
190 fixed-link {
191 speed = <1000>;
192 full-duplex;
193 };
194 };
195 };
196 };
197 };
198};
199
200&i2c0 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&i2c0_pins_a>;
203 status = "okay";
204};
205
206&i2c1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&i2c1_pins_a>;
209 status = "okay";
210};
211
212&mmc0 {
213 pinctrl-names = "default", "state_uhs";
214 pinctrl-0 = <&mmc0_pins_default>;
215 pinctrl-1 = <&mmc0_pins_uhs>;
216 status = "okay";
217 bus-width = <8>;
218 max-frequency = <50000000>;
219 cap-mmc-highspeed;
220 vmmc-supply = <®_3p3v>;
221 vqmmc-supply = <®_1p8v>;
222 non-removable;
223};
224
225&mmc1 {
226 pinctrl-names = "default", "state_uhs";
227 pinctrl-0 = <&mmc1_pins_default>;
228 pinctrl-1 = <&mmc1_pins_uhs>;
229 status = "okay";
230 bus-width = <4>;
231 max-frequency = <50000000>;
232 cap-sd-highspeed;
233 cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
234 vmmc-supply = <®_3p3v>;
235 vqmmc-supply = <®_3p3v>;
236};
237
238&pcie {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pcie_default>;
241 status = "okay";
242
243 pcie@0,0 {
244 status = "okay";
245 };
246
247 pcie@1,0 {
248 status = "okay";
249 };
250};
251
252&pcie0_phy {
253 status = "okay";
254};
255
256&pcie1_phy {
257 status = "okay";
258};
259
260&pio {
261 cir_pins_a:cir@0 {
262 pins-cir {
263 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
264 bias-disable;
265 };
266 };
267
268 i2c0_pins_a: i2c@0 {
269 pins-i2c0 {
270 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
271 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
272 bias-disable;
273 };
274 };
275
276 i2c1_pins_a: i2c@1 {
277 pin-i2c1 {
278 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
279 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
280 bias-disable;
281 };
282 };
283
284 i2s0_pins_a: i2s@0 {
285 pin-i2s0 {
286 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
287 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
288 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
289 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
290 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
291 drive-strength = <MTK_DRIVE_12mA>;
292 bias-pull-down;
293 };
294 };
295
296 i2s1_pins_a: i2s@1 {
297 pin-i2s1 {
298 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
299 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
300 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
301 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
302 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
303 drive-strength = <MTK_DRIVE_12mA>;
304 bias-pull-down;
305 };
306 };
307
308 key_pins_a: keys@0 {
309 pins-keys {
310 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
311 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
312 input-enable;
313 };
314 };
315
316 led_pins_a: leds@0 {
317 pins-leds {
318 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
319 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
320 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
321 };
322 };
323
324 mmc0_pins_default: mmc0default {
325 pins-cmd-dat {
326 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
327 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
328 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
329 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
330 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
331 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
332 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
333 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
334 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
335 input-enable;
336 bias-pull-up;
337 };
338
339 pins-clk {
340 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
341 bias-pull-down;
342 };
343
344 pins-rst {
345 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
346 bias-pull-up;
347 };
348 };
349
350 mmc0_pins_uhs: mmc0 {
351 pins-cmd-dat {
352 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
353 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
354 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
355 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
356 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
357 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
358 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
359 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
360 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
361 input-enable;
362 drive-strength = <MTK_DRIVE_2mA>;
363 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
364 };
365
366 pins-clk {
367 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
368 drive-strength = <MTK_DRIVE_2mA>;
369 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
370 };
371
372 pins-rst {
373 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
374 bias-pull-up;
375 };
376 };
377
378 mmc1_pins_default: mmc1default {
379 pins-cmd-dat {
380 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
381 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
382 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
383 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
384 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
385 input-enable;
386 drive-strength = <MTK_DRIVE_4mA>;
387 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
388 };
389
390 pins-clk {
391 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
392 bias-pull-down;
393 drive-strength = <MTK_DRIVE_4mA>;
394 };
395
396 pins-wp {
397 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
398 input-enable;
399 bias-pull-up;
400 };
401
402 pins-insert {
403 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
404 bias-pull-up;
405 };
406 };
407
408 mmc1_pins_uhs: mmc1 {
409 pins-cmd-dat {
410 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
411 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
412 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
413 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
414 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
415 input-enable;
416 drive-strength = <MTK_DRIVE_4mA>;
417 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
418 };
419
420 pins-clk {
421 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
422 drive-strength = <MTK_DRIVE_4mA>;
423 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
424 };
425 };
426
427 pcie_default: pcie_pin_default {
428 pins_cmd_dat {
429 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
430 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
431 bias-disable;
432 };
433 };
434
435 pwm_pins_a: pwm@0 {
436 pins-pwm {
437 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
438 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
439 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
440 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
441 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
442 };
443 };
444
445 spi0_pins_a: spi@0 {
446 pins-spi {
447 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
448 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
449 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
450 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
451 bias-disable;
452 };
453 };
454
455 uart0_pins_a: uart@0 {
456 pins-dat {
457 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
458 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
459 };
460 };
461
462 uart1_pins_a: uart@1 {
463 pins-dat {
464 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
465 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
466 };
467 };
468
469 uart2_pins_a: uart@2 {
470 pins-dat {
471 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
472 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
473 };
474 };
475};
476
477&pwm {
478 pinctrl-names = "default";
479 pinctrl-0 = <&pwm_pins_a>;
480 status = "okay";
481};
482
483&pwrap {
484 mt6323 {
485 mt6323led: led {
486 compatible = "mediatek,mt6323-led";
487 #address-cells = <1>;
488 #size-cells = <0>;
489
490 led@0 {
491 reg = <0>;
492 label = "bpi-r2:isink:green";
493 default-state = "off";
494 };
495
496 led@1 {
497 reg = <1>;
498 label = "bpi-r2:isink:red";
499 default-state = "off";
500 };
501
502 led@2 {
503 reg = <2>;
504 label = "bpi-r2:isink:blue";
505 default-state = "off";
506 };
507 };
508 };
509};
510
511&spi0 {
512 pinctrl-names = "default";
513 pinctrl-0 = <&spi0_pins_a>;
514 status = "okay";
515};
516
517&uart0 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&uart0_pins_a>;
520 status = "okay";
521};
522
523&uart1 {
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart1_pins_a>;
526 status = "okay";
527};
528
529&uart2 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart2_pins_a>;
532 status = "okay";
533};
534
535&usb1 {
536 vusb33-supply = <®_3p3v>;
537 vbus-supply = <®_5v>;
538 status = "okay";
539};
540
541&usb2 {
542 vusb33-supply = <®_3p3v>;
543 vbus-supply = <®_5v>;
544 status = "okay";
545};
546
547&u3phy1 {
548 status = "okay";
549};
550
551&u3phy2 {
552 status = "okay";
553};
554