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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * HD-audio core stuff
4 */
5
6#ifndef __SOUND_HDAUDIO_H
7#define __SOUND_HDAUDIO_H
8
9#include <linux/device.h>
10#include <linux/interrupt.h>
11#include <linux/timecounter.h>
12#include <sound/core.h>
13#include <sound/memalloc.h>
14#include <sound/hda_verbs.h>
15#include <drm/i915_component.h>
16
17/* codec node id */
18typedef u16 hda_nid_t;
19
20struct hdac_bus;
21struct hdac_stream;
22struct hdac_device;
23struct hdac_driver;
24struct hdac_widget_tree;
25struct hda_device_id;
26
27/*
28 * exported bus type
29 */
30extern struct bus_type snd_hda_bus_type;
31
32/*
33 * generic arrays
34 */
35struct snd_array {
36 unsigned int used;
37 unsigned int alloced;
38 unsigned int elem_size;
39 unsigned int alloc_align;
40 void *list;
41};
42
43/*
44 * HD-audio codec base device
45 */
46struct hdac_device {
47 struct device dev;
48 int type;
49 struct hdac_bus *bus;
50 unsigned int addr; /* codec address */
51 struct list_head list; /* list point for bus codec_list */
52
53 hda_nid_t afg; /* AFG node id */
54 hda_nid_t mfg; /* MFG node id */
55
56 /* ids */
57 unsigned int vendor_id;
58 unsigned int subsystem_id;
59 unsigned int revision_id;
60 unsigned int afg_function_id;
61 unsigned int mfg_function_id;
62 unsigned int afg_unsol:1;
63 unsigned int mfg_unsol:1;
64
65 unsigned int power_caps; /* FG power caps */
66
67 const char *vendor_name; /* codec vendor name */
68 const char *chip_name; /* codec chip name */
69
70 /* verb exec op override */
71 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
72 unsigned int flags, unsigned int *res);
73
74 /* widgets */
75 unsigned int num_nodes;
76 hda_nid_t start_nid, end_nid;
77
78 /* misc flags */
79 atomic_t in_pm; /* suspend/resume being performed */
80 bool link_power_control:1;
81
82 /* sysfs */
83 struct hdac_widget_tree *widgets;
84
85 /* regmap */
86 struct regmap *regmap;
87 struct snd_array vendor_verbs;
88 bool lazy_cache:1; /* don't wake up for writes */
89 bool caps_overwriting:1; /* caps overwrite being in process */
90 bool cache_coef:1; /* cache COEF read/write too */
91};
92
93/* device/driver type used for matching */
94enum {
95 HDA_DEV_CORE,
96 HDA_DEV_LEGACY,
97 HDA_DEV_ASOC,
98};
99
100/* direction */
101enum {
102 HDA_INPUT, HDA_OUTPUT
103};
104
105#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
106
107int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
108 const char *name, unsigned int addr);
109void snd_hdac_device_exit(struct hdac_device *dev);
110int snd_hdac_device_register(struct hdac_device *codec);
111void snd_hdac_device_unregister(struct hdac_device *codec);
112int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
113int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size);
114
115int snd_hdac_refresh_widgets(struct hdac_device *codec, bool sysfs);
116
117unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid,
118 unsigned int verb, unsigned int parm);
119int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd,
120 unsigned int flags, unsigned int *res);
121int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
122 unsigned int verb, unsigned int parm, unsigned int *res);
123int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
124 unsigned int *res);
125int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
126 int parm);
127int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
128 unsigned int parm, unsigned int val);
129int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
130 hda_nid_t *conn_list, int max_conns);
131int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
132 hda_nid_t *start_id);
133unsigned int snd_hdac_calc_stream_format(unsigned int rate,
134 unsigned int channels,
135 unsigned int format,
136 unsigned int maxbps,
137 unsigned short spdif_ctls);
138int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
139 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
140bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
141 unsigned int format);
142
143int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
144 int flags, unsigned int verb, unsigned int parm);
145int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
146 int flags, unsigned int verb, unsigned int parm);
147bool snd_hdac_check_power_state(struct hdac_device *hdac,
148 hda_nid_t nid, unsigned int target_state);
149unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
150 hda_nid_t nid, unsigned int target_state);
151/**
152 * snd_hdac_read_parm - read a codec parameter
153 * @codec: the codec object
154 * @nid: NID to read a parameter
155 * @parm: parameter to read
156 *
157 * Returns -1 for error. If you need to distinguish the error more
158 * strictly, use _snd_hdac_read_parm() directly.
159 */
160static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
161 int parm)
162{
163 unsigned int val;
164
165 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
166}
167
168#ifdef CONFIG_PM
169int snd_hdac_power_up(struct hdac_device *codec);
170int snd_hdac_power_down(struct hdac_device *codec);
171int snd_hdac_power_up_pm(struct hdac_device *codec);
172int snd_hdac_power_down_pm(struct hdac_device *codec);
173int snd_hdac_keep_power_up(struct hdac_device *codec);
174#else
175static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
176static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
177static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
178static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
179static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
180#endif
181
182/*
183 * HD-audio codec base driver
184 */
185struct hdac_driver {
186 struct device_driver driver;
187 int type;
188 const struct hda_device_id *id_table;
189 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
190 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
191};
192
193#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
194
195const struct hda_device_id *
196hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
197
198/*
199 * Bus verb operators
200 */
201struct hdac_bus_ops {
202 /* send a single command */
203 int (*command)(struct hdac_bus *bus, unsigned int cmd);
204 /* get a response from the last command */
205 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
206 unsigned int *res);
207 /* control the link power */
208 int (*link_power)(struct hdac_bus *bus, bool enable);
209};
210
211/*
212 * Lowlevel I/O operators
213 */
214struct hdac_io_ops {
215 /* mapped register accesses */
216 void (*reg_writel)(u32 value, u32 __iomem *addr);
217 u32 (*reg_readl)(u32 __iomem *addr);
218 void (*reg_writew)(u16 value, u16 __iomem *addr);
219 u16 (*reg_readw)(u16 __iomem *addr);
220 void (*reg_writeb)(u8 value, u8 __iomem *addr);
221 u8 (*reg_readb)(u8 __iomem *addr);
222 /* Allocation ops */
223 int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size,
224 struct snd_dma_buffer *buf);
225 void (*dma_free_pages)(struct hdac_bus *bus,
226 struct snd_dma_buffer *buf);
227};
228
229#define HDA_UNSOL_QUEUE_SIZE 64
230#define HDA_MAX_CODECS 8 /* limit by controller side */
231
232/*
233 * CORB/RIRB
234 *
235 * Each CORB entry is 4byte, RIRB is 8byte
236 */
237struct hdac_rb {
238 __le32 *buf; /* virtual address of CORB/RIRB buffer */
239 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
240 unsigned short rp, wp; /* RIRB read/write pointers */
241 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
242 u32 res[HDA_MAX_CODECS]; /* last read value */
243};
244
245/*
246 * HD-audio bus base driver
247 *
248 * @ppcap: pp capabilities pointer
249 * @spbcap: SPIB capabilities pointer
250 * @mlcap: MultiLink capabilities pointer
251 * @gtscap: gts capabilities pointer
252 * @drsmcap: dma resume capabilities pointer
253 */
254struct hdac_bus {
255 struct device *dev;
256 const struct hdac_bus_ops *ops;
257 const struct hdac_io_ops *io_ops;
258
259 /* h/w resources */
260 unsigned long addr;
261 void __iomem *remap_addr;
262 int irq;
263
264 void __iomem *ppcap;
265 void __iomem *spbcap;
266 void __iomem *mlcap;
267 void __iomem *gtscap;
268 void __iomem *drsmcap;
269
270 /* codec linked list */
271 struct list_head codec_list;
272 unsigned int num_codecs;
273
274 /* link caddr -> codec */
275 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
276
277 /* unsolicited event queue */
278 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
279 unsigned int unsol_rp, unsol_wp;
280 struct work_struct unsol_work;
281
282 /* bit flags of detected codecs */
283 unsigned long codec_mask;
284
285 /* bit flags of powered codecs */
286 unsigned long codec_powered;
287
288 /* CORB/RIRB */
289 struct hdac_rb corb;
290 struct hdac_rb rirb;
291 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
292
293 /* CORB/RIRB and position buffers */
294 struct snd_dma_buffer rb;
295 struct snd_dma_buffer posbuf;
296
297 /* hdac_stream linked list */
298 struct list_head stream_list;
299
300 /* operation state */
301 bool chip_init:1; /* h/w initialized */
302
303 /* behavior flags */
304 bool sync_write:1; /* sync after verb write */
305 bool use_posbuf:1; /* use position buffer */
306 bool snoop:1; /* enable snooping */
307 bool align_bdle_4k:1; /* BDLE align 4K boundary */
308 bool reverse_assign:1; /* assign devices in reverse order */
309 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
310
311 int bdl_pos_adj; /* BDL position adjustment */
312
313 /* locks */
314 spinlock_t reg_lock;
315 struct mutex cmd_mutex;
316
317 /* i915 component interface */
318 struct i915_audio_component *audio_component;
319 int i915_power_refcount;
320};
321
322int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
323 const struct hdac_bus_ops *ops,
324 const struct hdac_io_ops *io_ops);
325void snd_hdac_bus_exit(struct hdac_bus *bus);
326int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
327 unsigned int cmd, unsigned int *res);
328int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
329 unsigned int cmd, unsigned int *res);
330void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex);
331
332int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec);
333void snd_hdac_bus_remove_device(struct hdac_bus *bus,
334 struct hdac_device *codec);
335
336static inline void snd_hdac_codec_link_up(struct hdac_device *codec)
337{
338 set_bit(codec->addr, &codec->bus->codec_powered);
339}
340
341static inline void snd_hdac_codec_link_down(struct hdac_device *codec)
342{
343 clear_bit(codec->addr, &codec->bus->codec_powered);
344}
345
346int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
347int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
348 unsigned int *res);
349int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
350int snd_hdac_link_power(struct hdac_device *codec, bool enable);
351
352bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
353void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
354void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
355void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
356void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
357void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
358
359void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
360int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
361 void (*ack)(struct hdac_bus *,
362 struct hdac_stream *));
363
364int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
365void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
366
367/*
368 * macros for easy use
369 */
370#define _snd_hdac_chip_writeb(chip, reg, value) \
371 ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg)))
372#define _snd_hdac_chip_readb(chip, reg) \
373 ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg)))
374#define _snd_hdac_chip_writew(chip, reg, value) \
375 ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg)))
376#define _snd_hdac_chip_readw(chip, reg) \
377 ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg)))
378#define _snd_hdac_chip_writel(chip, reg, value) \
379 ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg)))
380#define _snd_hdac_chip_readl(chip, reg) \
381 ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg)))
382
383/* read/write a register, pass without AZX_REG_ prefix */
384#define snd_hdac_chip_writel(chip, reg, value) \
385 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
386#define snd_hdac_chip_writew(chip, reg, value) \
387 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
388#define snd_hdac_chip_writeb(chip, reg, value) \
389 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
390#define snd_hdac_chip_readl(chip, reg) \
391 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
392#define snd_hdac_chip_readw(chip, reg) \
393 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
394#define snd_hdac_chip_readb(chip, reg) \
395 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
396
397/* update a register, pass without AZX_REG_ prefix */
398#define snd_hdac_chip_updatel(chip, reg, mask, val) \
399 snd_hdac_chip_writel(chip, reg, \
400 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
401#define snd_hdac_chip_updatew(chip, reg, mask, val) \
402 snd_hdac_chip_writew(chip, reg, \
403 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
404#define snd_hdac_chip_updateb(chip, reg, mask, val) \
405 snd_hdac_chip_writeb(chip, reg, \
406 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
407
408/*
409 * HD-audio stream
410 */
411struct hdac_stream {
412 struct hdac_bus *bus;
413 struct snd_dma_buffer bdl; /* BDL buffer */
414 __le32 *posbuf; /* position buffer pointer */
415 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
416
417 unsigned int bufsize; /* size of the play buffer in bytes */
418 unsigned int period_bytes; /* size of the period in bytes */
419 unsigned int frags; /* number for period in the play buffer */
420 unsigned int fifo_size; /* FIFO size */
421
422 void __iomem *sd_addr; /* stream descriptor pointer */
423
424 u32 sd_int_sta_mask; /* stream int status mask */
425
426 /* pcm support */
427 struct snd_pcm_substream *substream; /* assigned substream,
428 * set in PCM open
429 */
430 unsigned int format_val; /* format value to be set in the
431 * controller and the codec
432 */
433 unsigned char stream_tag; /* assigned stream */
434 unsigned char index; /* stream index */
435 int assigned_key; /* last device# key assigned to */
436
437 bool opened:1;
438 bool running:1;
439 bool prepared:1;
440 bool no_period_wakeup:1;
441 bool locked:1;
442
443 /* timestamp */
444 unsigned long start_wallclk; /* start + minimum wallclk */
445 unsigned long period_wallclk; /* wallclk for period */
446 struct timecounter tc;
447 struct cyclecounter cc;
448 int delay_negative_threshold;
449
450 struct list_head list;
451#ifdef CONFIG_SND_HDA_DSP_LOADER
452 /* DSP access mutex */
453 struct mutex dsp_mutex;
454#endif
455};
456
457void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
458 int idx, int direction, int tag);
459struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
460 struct snd_pcm_substream *substream);
461void snd_hdac_stream_release(struct hdac_stream *azx_dev);
462struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
463 int dir, int stream_tag);
464
465int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
466void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
467int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
468int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
469 unsigned int format_val);
470void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
471void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
472void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
473void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
474void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
475 unsigned int streams, unsigned int reg);
476void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
477 unsigned int streams);
478void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
479 unsigned int streams);
480/*
481 * macros for easy use
482 */
483#define _snd_hdac_stream_write(type, dev, reg, value) \
484 ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg)))
485#define _snd_hdac_stream_read(type, dev, reg) \
486 ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg)))
487
488/* read/write a register, pass without AZX_REG_ prefix */
489#define snd_hdac_stream_writel(dev, reg, value) \
490 _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value)
491#define snd_hdac_stream_writew(dev, reg, value) \
492 _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value)
493#define snd_hdac_stream_writeb(dev, reg, value) \
494 _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value)
495#define snd_hdac_stream_readl(dev, reg) \
496 _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg)
497#define snd_hdac_stream_readw(dev, reg) \
498 _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg)
499#define snd_hdac_stream_readb(dev, reg) \
500 _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg)
501
502/* update a register, pass without AZX_REG_ prefix */
503#define snd_hdac_stream_updatel(dev, reg, mask, val) \
504 snd_hdac_stream_writel(dev, reg, \
505 (snd_hdac_stream_readl(dev, reg) & \
506 ~(mask)) | (val))
507#define snd_hdac_stream_updatew(dev, reg, mask, val) \
508 snd_hdac_stream_writew(dev, reg, \
509 (snd_hdac_stream_readw(dev, reg) & \
510 ~(mask)) | (val))
511#define snd_hdac_stream_updateb(dev, reg, mask, val) \
512 snd_hdac_stream_writeb(dev, reg, \
513 (snd_hdac_stream_readb(dev, reg) & \
514 ~(mask)) | (val))
515
516#ifdef CONFIG_SND_HDA_DSP_LOADER
517/* DSP lock helpers */
518#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
519#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
520#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
521#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
522/* DSP loader helpers */
523int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
524 unsigned int byte_size, struct snd_dma_buffer *bufp);
525void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
526void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
527 struct snd_dma_buffer *dmab);
528#else /* CONFIG_SND_HDA_DSP_LOADER */
529#define snd_hdac_dsp_lock_init(dev) do {} while (0)
530#define snd_hdac_dsp_lock(dev) do {} while (0)
531#define snd_hdac_dsp_unlock(dev) do {} while (0)
532#define snd_hdac_stream_is_locked(dev) 0
533
534static inline int
535snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
536 unsigned int byte_size, struct snd_dma_buffer *bufp)
537{
538 return 0;
539}
540
541static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
542{
543}
544
545static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
546 struct snd_dma_buffer *dmab)
547{
548}
549#endif /* CONFIG_SND_HDA_DSP_LOADER */
550
551
552/*
553 * generic array helpers
554 */
555void *snd_array_new(struct snd_array *array);
556void snd_array_free(struct snd_array *array);
557static inline void snd_array_init(struct snd_array *array, unsigned int size,
558 unsigned int align)
559{
560 array->elem_size = size;
561 array->alloc_align = align;
562}
563
564static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
565{
566 return array->list + idx * array->elem_size;
567}
568
569static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
570{
571 return (unsigned long)(ptr - array->list) / array->elem_size;
572}
573
574#endif /* __SOUND_HDAUDIO_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * HD-audio core stuff
4 */
5
6#ifndef __SOUND_HDAUDIO_H
7#define __SOUND_HDAUDIO_H
8
9#include <linux/device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/io-64-nonatomic-lo-hi.h>
13#include <linux/iopoll.h>
14#include <linux/pci.h>
15#include <linux/pm_runtime.h>
16#include <linux/timecounter.h>
17#include <sound/core.h>
18#include <sound/pcm.h>
19#include <sound/memalloc.h>
20#include <sound/hda_verbs.h>
21#include <drm/i915_component.h>
22
23/* codec node id */
24typedef u16 hda_nid_t;
25
26struct hdac_bus;
27struct hdac_stream;
28struct hdac_device;
29struct hdac_driver;
30struct hdac_widget_tree;
31struct hda_device_id;
32
33/*
34 * exported bus type
35 */
36extern const struct bus_type snd_hda_bus_type;
37
38/*
39 * generic arrays
40 */
41struct snd_array {
42 unsigned int used;
43 unsigned int alloced;
44 unsigned int elem_size;
45 unsigned int alloc_align;
46 void *list;
47};
48
49/*
50 * HD-audio codec base device
51 */
52struct hdac_device {
53 struct device dev;
54 int type;
55 struct hdac_bus *bus;
56 unsigned int addr; /* codec address */
57 struct list_head list; /* list point for bus codec_list */
58
59 hda_nid_t afg; /* AFG node id */
60 hda_nid_t mfg; /* MFG node id */
61
62 /* ids */
63 unsigned int vendor_id;
64 unsigned int subsystem_id;
65 unsigned int revision_id;
66 unsigned int afg_function_id;
67 unsigned int mfg_function_id;
68 unsigned int afg_unsol:1;
69 unsigned int mfg_unsol:1;
70
71 unsigned int power_caps; /* FG power caps */
72
73 const char *vendor_name; /* codec vendor name */
74 const char *chip_name; /* codec chip name */
75
76 /* verb exec op override */
77 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
78 unsigned int flags, unsigned int *res);
79
80 /* widgets */
81 unsigned int num_nodes;
82 hda_nid_t start_nid, end_nid;
83
84 /* misc flags */
85 atomic_t in_pm; /* suspend/resume being performed */
86
87 /* sysfs */
88 struct mutex widget_lock;
89 struct hdac_widget_tree *widgets;
90
91 /* regmap */
92 struct regmap *regmap;
93 struct mutex regmap_lock;
94 struct snd_array vendor_verbs;
95 bool lazy_cache:1; /* don't wake up for writes */
96 bool caps_overwriting:1; /* caps overwrite being in process */
97 bool cache_coef:1; /* cache COEF read/write too */
98 unsigned int registered:1; /* codec was registered */
99};
100
101/* device/driver type used for matching */
102enum {
103 HDA_DEV_CORE,
104 HDA_DEV_LEGACY,
105 HDA_DEV_ASOC,
106};
107
108enum {
109 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */
110 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
111 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */
112};
113
114/* direction */
115enum {
116 HDA_INPUT, HDA_OUTPUT
117};
118
119#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
120
121int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
122 const char *name, unsigned int addr);
123void snd_hdac_device_exit(struct hdac_device *dev);
124int snd_hdac_device_register(struct hdac_device *codec);
125void snd_hdac_device_unregister(struct hdac_device *codec);
126int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
127int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
128
129int snd_hdac_refresh_widgets(struct hdac_device *codec);
130
131int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
132 unsigned int verb, unsigned int parm, unsigned int *res);
133int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
134 unsigned int *res);
135int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
136 int parm);
137int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
138 unsigned int parm, unsigned int val);
139int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
140 hda_nid_t *conn_list, int max_conns);
141int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
142 hda_nid_t *start_id);
143unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat,
144 unsigned int maxbits);
145unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate);
146unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits,
147 unsigned int rate, unsigned short spdif_ctls);
148int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
149 u32 *ratesp, u64 *formatsp, u32 *subformatsp,
150 unsigned int *bpsp);
151bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
152 unsigned int format);
153
154int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
155 int flags, unsigned int verb, unsigned int parm);
156int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
157 int flags, unsigned int verb, unsigned int parm);
158bool snd_hdac_check_power_state(struct hdac_device *hdac,
159 hda_nid_t nid, unsigned int target_state);
160unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
161 hda_nid_t nid, unsigned int target_state);
162/**
163 * snd_hdac_read_parm - read a codec parameter
164 * @codec: the codec object
165 * @nid: NID to read a parameter
166 * @parm: parameter to read
167 *
168 * Returns -1 for error. If you need to distinguish the error more
169 * strictly, use _snd_hdac_read_parm() directly.
170 */
171static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
172 int parm)
173{
174 unsigned int val;
175
176 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
177}
178
179#ifdef CONFIG_PM
180int snd_hdac_power_up(struct hdac_device *codec);
181int snd_hdac_power_down(struct hdac_device *codec);
182int snd_hdac_power_up_pm(struct hdac_device *codec);
183int snd_hdac_power_down_pm(struct hdac_device *codec);
184int snd_hdac_keep_power_up(struct hdac_device *codec);
185
186/* call this at entering into suspend/resume callbacks in codec driver */
187static inline void snd_hdac_enter_pm(struct hdac_device *codec)
188{
189 atomic_inc(&codec->in_pm);
190}
191
192/* call this at leaving from suspend/resume callbacks in codec driver */
193static inline void snd_hdac_leave_pm(struct hdac_device *codec)
194{
195 atomic_dec(&codec->in_pm);
196}
197
198static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
199{
200 return atomic_read(&codec->in_pm);
201}
202
203static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
204{
205 return !pm_runtime_suspended(&codec->dev);
206}
207#else
208static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
209static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
210static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
211static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
212static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
213static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
214static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
215static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
216static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
217#endif
218
219/*
220 * HD-audio codec base driver
221 */
222struct hdac_driver {
223 struct device_driver driver;
224 int type;
225 const struct hda_device_id *id_table;
226 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
227 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
228
229 /* fields used by ext bus APIs */
230 int (*probe)(struct hdac_device *dev);
231 int (*remove)(struct hdac_device *dev);
232 void (*shutdown)(struct hdac_device *dev);
233};
234
235#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
236
237const struct hda_device_id *
238hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
239
240/*
241 * Bus verb operators
242 */
243struct hdac_bus_ops {
244 /* send a single command */
245 int (*command)(struct hdac_bus *bus, unsigned int cmd);
246 /* get a response from the last command */
247 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
248 unsigned int *res);
249 /* notify of codec link power-up/down */
250 void (*link_power)(struct hdac_device *hdev, bool enable);
251};
252
253/*
254 * ops used for ASoC HDA codec drivers
255 */
256struct hdac_ext_bus_ops {
257 int (*hdev_attach)(struct hdac_device *hdev);
258 int (*hdev_detach)(struct hdac_device *hdev);
259};
260
261#define HDA_UNSOL_QUEUE_SIZE 64
262#define HDA_MAX_CODECS 8 /* limit by controller side */
263
264/*
265 * CORB/RIRB
266 *
267 * Each CORB entry is 4byte, RIRB is 8byte
268 */
269struct hdac_rb {
270 __le32 *buf; /* virtual address of CORB/RIRB buffer */
271 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
272 unsigned short rp, wp; /* RIRB read/write pointers */
273 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
274 u32 res[HDA_MAX_CODECS]; /* last read value */
275};
276
277/*
278 * HD-audio bus base driver
279 *
280 * @ppcap: pp capabilities pointer
281 * @spbcap: SPIB capabilities pointer
282 * @mlcap: MultiLink capabilities pointer
283 * @gtscap: gts capabilities pointer
284 * @drsmcap: dma resume capabilities pointer
285 * @num_streams: streams supported
286 * @idx: HDA link index
287 * @hlink_list: link list of HDA links
288 * @lock: lock for link and display power mgmt
289 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
290 */
291struct hdac_bus {
292 struct device *dev;
293 const struct hdac_bus_ops *ops;
294 const struct hdac_ext_bus_ops *ext_ops;
295
296 /* h/w resources */
297 unsigned long addr;
298 void __iomem *remap_addr;
299 int irq;
300
301 void __iomem *ppcap;
302 void __iomem *spbcap;
303 void __iomem *mlcap;
304 void __iomem *gtscap;
305 void __iomem *drsmcap;
306
307 /* codec linked list */
308 struct list_head codec_list;
309 unsigned int num_codecs;
310
311 /* link caddr -> codec */
312 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
313
314 /* unsolicited event queue */
315 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
316 unsigned int unsol_rp, unsol_wp;
317 struct work_struct unsol_work;
318
319 /* bit flags of detected codecs */
320 unsigned long codec_mask;
321
322 /* bit flags of powered codecs */
323 unsigned long codec_powered;
324
325 /* CORB/RIRB */
326 struct hdac_rb corb;
327 struct hdac_rb rirb;
328 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
329 wait_queue_head_t rirb_wq;
330
331 /* CORB/RIRB and position buffers */
332 struct snd_dma_buffer rb;
333 struct snd_dma_buffer posbuf;
334 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
335
336 /* hdac_stream linked list */
337 struct list_head stream_list;
338
339 /* operation state */
340 bool chip_init:1; /* h/w initialized */
341
342 /* behavior flags */
343 bool aligned_mmio:1; /* aligned MMIO access */
344 bool sync_write:1; /* sync after verb write */
345 bool use_posbuf:1; /* use position buffer */
346 bool snoop:1; /* enable snooping */
347 bool align_bdle_4k:1; /* BDLE align 4K boundary */
348 bool reverse_assign:1; /* assign devices in reverse order */
349 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
350 bool polling_mode:1;
351 bool needs_damn_long_delay:1;
352 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */
353 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */
354
355 int poll_count;
356
357 int bdl_pos_adj; /* BDL position adjustment */
358
359 /* delay time in us for dma stop */
360 unsigned int dma_stop_delay;
361
362 /* locks */
363 spinlock_t reg_lock;
364 struct mutex cmd_mutex;
365 struct mutex lock;
366
367 /* DRM component interface */
368 struct drm_audio_component *audio_component;
369 long display_power_status;
370 unsigned long display_power_active;
371
372 /* parameters required for enhanced capabilities */
373 int num_streams;
374 int idx;
375
376 /* link management */
377 struct list_head hlink_list;
378 bool cmd_dma_state;
379
380 /* factor used to derive STRIPE control value */
381 unsigned int sdo_limit;
382};
383
384int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
385 const struct hdac_bus_ops *ops);
386void snd_hdac_bus_exit(struct hdac_bus *bus);
387int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
388 unsigned int cmd, unsigned int *res);
389
390void snd_hdac_codec_link_up(struct hdac_device *codec);
391void snd_hdac_codec_link_down(struct hdac_device *codec);
392
393int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
394int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
395 unsigned int *res);
396int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
397
398bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
399void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
400void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
401void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
402void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
403void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
404int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
405void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
406
407void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
408int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
409 void (*ack)(struct hdac_bus *,
410 struct hdac_stream *));
411
412int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
413void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
414
415#ifdef CONFIG_SND_HDA_ALIGNED_MMIO
416unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
417void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
418 unsigned int mask);
419#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio
420#else
421#define snd_hdac_aligned_mmio(bus) false
422#define snd_hdac_aligned_read(addr, mask) 0
423#define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
424#endif
425
426static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
427 u8 val)
428{
429 if (snd_hdac_aligned_mmio(bus))
430 snd_hdac_aligned_write(val, addr, 0xff);
431 else
432 writeb(val, addr);
433}
434
435static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
436 u16 val)
437{
438 if (snd_hdac_aligned_mmio(bus))
439 snd_hdac_aligned_write(val, addr, 0xffff);
440 else
441 writew(val, addr);
442}
443
444static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
445{
446 return snd_hdac_aligned_mmio(bus) ?
447 snd_hdac_aligned_read(addr, 0xff) : readb(addr);
448}
449
450static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
451{
452 return snd_hdac_aligned_mmio(bus) ?
453 snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
454}
455
456#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
457#define snd_hdac_reg_readl(bus, addr) readl(addr)
458#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
459#define snd_hdac_reg_readq(bus, addr) readq(addr)
460
461/*
462 * macros for easy use
463 */
464#define _snd_hdac_chip_writeb(chip, reg, value) \
465 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
466#define _snd_hdac_chip_readb(chip, reg) \
467 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
468#define _snd_hdac_chip_writew(chip, reg, value) \
469 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
470#define _snd_hdac_chip_readw(chip, reg) \
471 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
472#define _snd_hdac_chip_writel(chip, reg, value) \
473 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
474#define _snd_hdac_chip_readl(chip, reg) \
475 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
476
477/* read/write a register, pass without AZX_REG_ prefix */
478#define snd_hdac_chip_writel(chip, reg, value) \
479 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
480#define snd_hdac_chip_writew(chip, reg, value) \
481 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
482#define snd_hdac_chip_writeb(chip, reg, value) \
483 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
484#define snd_hdac_chip_readl(chip, reg) \
485 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
486#define snd_hdac_chip_readw(chip, reg) \
487 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
488#define snd_hdac_chip_readb(chip, reg) \
489 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
490
491/* update a register, pass without AZX_REG_ prefix */
492#define snd_hdac_chip_updatel(chip, reg, mask, val) \
493 snd_hdac_chip_writel(chip, reg, \
494 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
495#define snd_hdac_chip_updatew(chip, reg, mask, val) \
496 snd_hdac_chip_writew(chip, reg, \
497 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
498#define snd_hdac_chip_updateb(chip, reg, mask, val) \
499 snd_hdac_chip_writeb(chip, reg, \
500 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
501
502/* update register macro */
503#define snd_hdac_updatel(addr, reg, mask, val) \
504 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
505
506#define snd_hdac_updatew(addr, reg, mask, val) \
507 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
508
509/*
510 * HD-audio stream
511 */
512struct hdac_stream {
513 struct hdac_bus *bus;
514 struct snd_dma_buffer bdl; /* BDL buffer */
515 __le32 *posbuf; /* position buffer pointer */
516 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
517
518 unsigned int bufsize; /* size of the play buffer in bytes */
519 unsigned int period_bytes; /* size of the period in bytes */
520 unsigned int frags; /* number for period in the play buffer */
521 unsigned int fifo_size; /* FIFO size */
522
523 void __iomem *sd_addr; /* stream descriptor pointer */
524
525 void __iomem *spib_addr; /* software position in buffers stream pointer */
526 void __iomem *fifo_addr; /* software position Max fifos stream pointer */
527
528 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
529 u32 dpib; /* DMA position in buffer */
530 u32 lpib; /* Linear position in buffer */
531
532 u32 sd_int_sta_mask; /* stream int status mask */
533
534 /* pcm support */
535 struct snd_pcm_substream *substream; /* assigned substream,
536 * set in PCM open
537 */
538 struct snd_compr_stream *cstream;
539 unsigned int format_val; /* format value to be set in the
540 * controller and the codec
541 */
542 unsigned char stream_tag; /* assigned stream */
543 unsigned char index; /* stream index */
544 int assigned_key; /* last device# key assigned to */
545
546 bool opened:1;
547 bool running:1;
548 bool prepared:1;
549 bool no_period_wakeup:1;
550 bool locked:1;
551 bool stripe:1; /* apply stripe control */
552
553 u64 curr_pos;
554 /* timestamp */
555 unsigned long start_wallclk; /* start + minimum wallclk */
556 unsigned long period_wallclk; /* wallclk for period */
557 struct timecounter tc;
558 struct cyclecounter cc;
559 int delay_negative_threshold;
560
561 struct list_head list;
562#ifdef CONFIG_SND_HDA_DSP_LOADER
563 /* DSP access mutex */
564 struct mutex dsp_mutex;
565#endif
566};
567
568void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
569 int idx, int direction, int tag);
570struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
571 struct snd_pcm_substream *substream);
572void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
573void snd_hdac_stream_release(struct hdac_stream *azx_dev);
574struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
575 int dir, int stream_tag);
576
577int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading);
578void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
579int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
580int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
581 unsigned int format_val);
582void snd_hdac_stream_start(struct hdac_stream *azx_dev);
583void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
584void snd_hdac_stop_streams(struct hdac_bus *bus);
585void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
586void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
587void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
588 unsigned int streams, unsigned int reg);
589void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
590 unsigned int streams);
591void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
592 unsigned int streams);
593int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
594 struct snd_pcm_substream *substream);
595
596void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
597 bool enable, int index);
598int snd_hdac_stream_set_spib(struct hdac_bus *bus,
599 struct hdac_stream *azx_dev, u32 value);
600int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
601 struct hdac_stream *azx_dev);
602void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
603 bool enable, int index);
604int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
605int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
606 struct hdac_stream *azx_dev, u32 value);
607int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
608
609/*
610 * macros for easy use
611 */
612/* read/write a register, pass without AZX_REG_ prefix */
613#define snd_hdac_stream_writel(dev, reg, value) \
614 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
615#define snd_hdac_stream_writew(dev, reg, value) \
616 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
617#define snd_hdac_stream_writeb(dev, reg, value) \
618 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
619#define snd_hdac_stream_readl(dev, reg) \
620 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
621#define snd_hdac_stream_readw(dev, reg) \
622 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
623#define snd_hdac_stream_readb(dev, reg) \
624 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
625#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
626 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
627 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
628#define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \
629 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \
630 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
631#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
632 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
633 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
634
635/* update a register, pass without AZX_REG_ prefix */
636#define snd_hdac_stream_updatel(dev, reg, mask, val) \
637 snd_hdac_stream_writel(dev, reg, \
638 (snd_hdac_stream_readl(dev, reg) & \
639 ~(mask)) | (val))
640#define snd_hdac_stream_updatew(dev, reg, mask, val) \
641 snd_hdac_stream_writew(dev, reg, \
642 (snd_hdac_stream_readw(dev, reg) & \
643 ~(mask)) | (val))
644#define snd_hdac_stream_updateb(dev, reg, mask, val) \
645 snd_hdac_stream_writeb(dev, reg, \
646 (snd_hdac_stream_readb(dev, reg) & \
647 ~(mask)) | (val))
648
649#ifdef CONFIG_SND_HDA_DSP_LOADER
650/* DSP lock helpers */
651#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
652#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
653#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
654#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
655/* DSP loader helpers */
656int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
657 unsigned int byte_size, struct snd_dma_buffer *bufp);
658void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
659void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
660 struct snd_dma_buffer *dmab);
661#else /* CONFIG_SND_HDA_DSP_LOADER */
662#define snd_hdac_dsp_lock_init(dev) do {} while (0)
663#define snd_hdac_dsp_lock(dev) do {} while (0)
664#define snd_hdac_dsp_unlock(dev) do {} while (0)
665#define snd_hdac_stream_is_locked(dev) 0
666
667static inline int
668snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
669 unsigned int byte_size, struct snd_dma_buffer *bufp)
670{
671 return 0;
672}
673
674static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
675{
676}
677
678static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
679 struct snd_dma_buffer *dmab)
680{
681}
682#endif /* CONFIG_SND_HDA_DSP_LOADER */
683
684
685/*
686 * generic array helpers
687 */
688void *snd_array_new(struct snd_array *array);
689void snd_array_free(struct snd_array *array);
690static inline void snd_array_init(struct snd_array *array, unsigned int size,
691 unsigned int align)
692{
693 array->elem_size = size;
694 array->alloc_align = align;
695}
696
697static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
698{
699 return array->list + idx * array->elem_size;
700}
701
702static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
703{
704 return (unsigned long)(ptr - array->list) / array->elem_size;
705}
706
707/* a helper macro to iterate for each snd_array element */
708#define snd_array_for_each(array, idx, ptr) \
709 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
710 (ptr) = snd_array_elem(array, ++(idx)))
711
712/*
713 * Device matching
714 */
715
716#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
717 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
718 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \
719 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \
720 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \
721 { } \
722 }, pci))
723
724#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \
725 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \
726 { } \
727 }, pci))
728
729#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \
730 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \
731 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \
732 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \
733 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \
734 { } \
735 }, pci) || HDA_CONTROLLER_IS_HSW(pci))
736
737#endif /* __SOUND_HDAUDIO_H */