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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2023, Linaro Limited
5 */
6
7#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
8#define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
9
10/* GCC clocks */
11#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
12#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
13#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
14#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
15#define GCC_BOOT_ROM_AHB_CLK 4
16#define GCC_CAMERA_AHB_CLK 5
17#define GCC_CAMERA_HF_AXI_CLK 6
18#define GCC_CAMERA_SF_AXI_CLK 7
19#define GCC_CAMERA_XO_CLK 8
20#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
21#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
22#define GCC_CNOC_PCIE_SF_AXI_CLK 11
23#define GCC_DDRSS_GPU_AXI_CLK 12
24#define GCC_DDRSS_PCIE_SF_QTB_CLK 13
25#define GCC_DISP_AHB_CLK 14
26#define GCC_DISP_HF_AXI_CLK 15
27#define GCC_DISP_XO_CLK 16
28#define GCC_GP1_CLK 17
29#define GCC_GP1_CLK_SRC 18
30#define GCC_GP2_CLK 19
31#define GCC_GP2_CLK_SRC 20
32#define GCC_GP3_CLK 21
33#define GCC_GP3_CLK_SRC 22
34#define GCC_GPLL0 23
35#define GCC_GPLL0_OUT_EVEN 24
36#define GCC_GPLL1 25
37#define GCC_GPLL3 26
38#define GCC_GPLL4 27
39#define GCC_GPLL6 28
40#define GCC_GPLL7 29
41#define GCC_GPLL9 30
42#define GCC_GPU_CFG_AHB_CLK 31
43#define GCC_GPU_GPLL0_CLK_SRC 32
44#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
45#define GCC_GPU_MEMNOC_GFX_CLK 34
46#define GCC_GPU_SNOC_DVM_GFX_CLK 35
47#define GCC_PCIE_0_AUX_CLK 36
48#define GCC_PCIE_0_AUX_CLK_SRC 37
49#define GCC_PCIE_0_CFG_AHB_CLK 38
50#define GCC_PCIE_0_MSTR_AXI_CLK 39
51#define GCC_PCIE_0_PHY_RCHNG_CLK 40
52#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41
53#define GCC_PCIE_0_PIPE_CLK 42
54#define GCC_PCIE_0_PIPE_CLK_SRC 43
55#define GCC_PCIE_0_SLV_AXI_CLK 44
56#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
57#define GCC_PCIE_1_AUX_CLK 46
58#define GCC_PCIE_1_AUX_CLK_SRC 47
59#define GCC_PCIE_1_CFG_AHB_CLK 48
60#define GCC_PCIE_1_MSTR_AXI_CLK 49
61#define GCC_PCIE_1_PHY_AUX_CLK 50
62#define GCC_PCIE_1_PHY_AUX_CLK_SRC 51
63#define GCC_PCIE_1_PHY_RCHNG_CLK 52
64#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53
65#define GCC_PCIE_1_PIPE_CLK 54
66#define GCC_PCIE_1_PIPE_CLK_SRC 55
67#define GCC_PCIE_1_SLV_AXI_CLK 56
68#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57
69#define GCC_PDM2_CLK 58
70#define GCC_PDM2_CLK_SRC 59
71#define GCC_PDM_AHB_CLK 60
72#define GCC_PDM_XO4_CLK 61
73#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
74#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
75#define GCC_QMIP_DISP_AHB_CLK 64
76#define GCC_QMIP_GPU_AHB_CLK 65
77#define GCC_QMIP_PCIE_AHB_CLK 66
78#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67
79#define GCC_QMIP_VIDEO_CVP_AHB_CLK 68
80#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69
81#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70
82#define GCC_QUPV3_I2C_CORE_CLK 71
83#define GCC_QUPV3_I2C_S0_CLK 72
84#define GCC_QUPV3_I2C_S0_CLK_SRC 73
85#define GCC_QUPV3_I2C_S1_CLK 74
86#define GCC_QUPV3_I2C_S1_CLK_SRC 75
87#define GCC_QUPV3_I2C_S2_CLK 76
88#define GCC_QUPV3_I2C_S2_CLK_SRC 77
89#define GCC_QUPV3_I2C_S3_CLK 78
90#define GCC_QUPV3_I2C_S3_CLK_SRC 79
91#define GCC_QUPV3_I2C_S4_CLK 80
92#define GCC_QUPV3_I2C_S4_CLK_SRC 81
93#define GCC_QUPV3_I2C_S5_CLK 82
94#define GCC_QUPV3_I2C_S5_CLK_SRC 83
95#define GCC_QUPV3_I2C_S6_CLK 84
96#define GCC_QUPV3_I2C_S6_CLK_SRC 85
97#define GCC_QUPV3_I2C_S7_CLK 86
98#define GCC_QUPV3_I2C_S7_CLK_SRC 87
99#define GCC_QUPV3_I2C_S8_CLK 88
100#define GCC_QUPV3_I2C_S8_CLK_SRC 89
101#define GCC_QUPV3_I2C_S9_CLK 90
102#define GCC_QUPV3_I2C_S9_CLK_SRC 91
103#define GCC_QUPV3_I2C_S_AHB_CLK 92
104#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
105#define GCC_QUPV3_WRAP1_CORE_CLK 94
106#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95
107#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96
108#define GCC_QUPV3_WRAP1_S0_CLK 97
109#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
110#define GCC_QUPV3_WRAP1_S1_CLK 99
111#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
112#define GCC_QUPV3_WRAP1_S2_CLK 101
113#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
114#define GCC_QUPV3_WRAP1_S3_CLK 103
115#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
116#define GCC_QUPV3_WRAP1_S4_CLK 105
117#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
118#define GCC_QUPV3_WRAP1_S5_CLK 107
119#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
120#define GCC_QUPV3_WRAP1_S6_CLK 109
121#define GCC_QUPV3_WRAP1_S6_CLK_SRC 110
122#define GCC_QUPV3_WRAP1_S7_CLK 111
123#define GCC_QUPV3_WRAP1_S7_CLK_SRC 112
124#define GCC_QUPV3_WRAP2_CORE_2X_CLK 113
125#define GCC_QUPV3_WRAP2_CORE_CLK 114
126#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115
127#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116
128#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117
129#define GCC_QUPV3_WRAP2_S0_CLK 118
130#define GCC_QUPV3_WRAP2_S0_CLK_SRC 119
131#define GCC_QUPV3_WRAP2_S1_CLK 120
132#define GCC_QUPV3_WRAP2_S1_CLK_SRC 121
133#define GCC_QUPV3_WRAP2_S2_CLK 122
134#define GCC_QUPV3_WRAP2_S2_CLK_SRC 123
135#define GCC_QUPV3_WRAP2_S3_CLK 124
136#define GCC_QUPV3_WRAP2_S3_CLK_SRC 125
137#define GCC_QUPV3_WRAP2_S4_CLK 126
138#define GCC_QUPV3_WRAP2_S4_CLK_SRC 127
139#define GCC_QUPV3_WRAP2_S5_CLK 128
140#define GCC_QUPV3_WRAP2_S5_CLK_SRC 129
141#define GCC_QUPV3_WRAP2_S6_CLK 130
142#define GCC_QUPV3_WRAP2_S6_CLK_SRC 131
143#define GCC_QUPV3_WRAP2_S7_CLK 132
144#define GCC_QUPV3_WRAP2_S7_CLK_SRC 133
145#define GCC_QUPV3_WRAP3_CORE_2X_CLK 134
146#define GCC_QUPV3_WRAP3_CORE_CLK 135
147#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136
148#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137
149#define GCC_QUPV3_WRAP3_S0_CLK 138
150#define GCC_QUPV3_WRAP3_S0_CLK_SRC 139
151#define GCC_QUPV3_WRAP_1_M_AHB_CLK 140
152#define GCC_QUPV3_WRAP_1_S_AHB_CLK 141
153#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142
154#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143
155#define GCC_QUPV3_WRAP_2_M_AHB_CLK 144
156#define GCC_QUPV3_WRAP_2_S_AHB_CLK 145
157#define GCC_QUPV3_WRAP_3_M_AHB_CLK 146
158#define GCC_QUPV3_WRAP_3_S_AHB_CLK 147
159#define GCC_SDCC2_AHB_CLK 148
160#define GCC_SDCC2_APPS_CLK 149
161#define GCC_SDCC2_APPS_CLK_SRC 150
162#define GCC_SDCC4_AHB_CLK 151
163#define GCC_SDCC4_APPS_CLK 152
164#define GCC_SDCC4_APPS_CLK_SRC 153
165#define GCC_UFS_PHY_AHB_CLK 154
166#define GCC_UFS_PHY_AXI_CLK 155
167#define GCC_UFS_PHY_AXI_CLK_SRC 156
168#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157
169#define GCC_UFS_PHY_ICE_CORE_CLK 158
170#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159
171#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
172#define GCC_UFS_PHY_PHY_AUX_CLK 161
173#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162
174#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163
175#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
176#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165
177#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166
178#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167
179#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
180#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169
181#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170
182#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171
183#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172
184#define GCC_USB30_PRIM_MASTER_CLK 173
185#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
186#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
187#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
188#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
189#define GCC_USB30_PRIM_SLEEP_CLK 178
190#define GCC_USB3_PRIM_PHY_AUX_CLK 179
191#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
192#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
193#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
194#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
195#define GCC_VIDEO_AHB_CLK 184
196#define GCC_VIDEO_AXI0_CLK 185
197#define GCC_VIDEO_AXI1_CLK 186
198#define GCC_VIDEO_XO_CLK 187
199#define GCC_GPLL0_AO 188
200#define GCC_GPLL0_OUT_EVEN_AO 189
201#define GCC_GPLL1_AO 190
202#define GCC_GPLL3_AO 191
203#define GCC_GPLL4_AO 192
204#define GCC_GPLL6_AO 193
205
206/* GCC resets */
207#define GCC_CAMERA_BCR 0
208#define GCC_DISPLAY_BCR 1
209#define GCC_GPU_BCR 2
210#define GCC_PCIE_0_BCR 3
211#define GCC_PCIE_0_LINK_DOWN_BCR 4
212#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
213#define GCC_PCIE_0_PHY_BCR 6
214#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
215#define GCC_PCIE_1_BCR 8
216#define GCC_PCIE_1_LINK_DOWN_BCR 9
217#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
218#define GCC_PCIE_1_PHY_BCR 11
219#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
220#define GCC_PCIE_PHY_BCR 13
221#define GCC_PCIE_PHY_CFG_AHB_BCR 14
222#define GCC_PCIE_PHY_COM_BCR 15
223#define GCC_PDM_BCR 16
224#define GCC_QUPV3_WRAPPER_1_BCR 17
225#define GCC_QUPV3_WRAPPER_2_BCR 18
226#define GCC_QUPV3_WRAPPER_3_BCR 19
227#define GCC_QUPV3_WRAPPER_I2C_BCR 20
228#define GCC_QUSB2PHY_PRIM_BCR 21
229#define GCC_QUSB2PHY_SEC_BCR 22
230#define GCC_SDCC2_BCR 23
231#define GCC_SDCC4_BCR 24
232#define GCC_UFS_PHY_BCR 25
233#define GCC_USB30_PRIM_BCR 26
234#define GCC_USB3_DP_PHY_PRIM_BCR 27
235#define GCC_USB3_DP_PHY_SEC_BCR 28
236#define GCC_USB3_PHY_PRIM_BCR 29
237#define GCC_USB3_PHY_SEC_BCR 30
238#define GCC_USB3PHY_PHY_PRIM_BCR 31
239#define GCC_USB3PHY_PHY_SEC_BCR 32
240#define GCC_VIDEO_AXI0_CLK_ARES 33
241#define GCC_VIDEO_AXI1_CLK_ARES 34
242#define GCC_VIDEO_BCR 35
243
244/* GCC power domains */
245#define PCIE_0_GDSC 0
246#define PCIE_0_PHY_GDSC 1
247#define PCIE_1_GDSC 2
248#define PCIE_1_PHY_GDSC 3
249#define UFS_PHY_GDSC 4
250#define UFS_MEM_PHY_GDSC 5
251#define USB30_PRIM_GDSC 6
252#define USB3_PHY_GDSC 7
253
254#endif